diff --git a/Source/HBIOS/Config/RCEZ80_std.asm b/Source/HBIOS/Config/RCEZ80_std.asm
index 923c2b32..f916d410 100644
--- a/Source/HBIOS/Config/RCEZ80_std.asm
+++ b/Source/HBIOS/Config/RCEZ80_std.asm
@@ -26,19 +26,21 @@
 ;
 #include "cfg_rcez80.asm"
 ;
-CPUOSC		.SET	7372800		; CPU OSC FREQ IN MHZ
+CPUOSC		.SET	18432000	; CPU OSC FREQ IN MHZ
+;
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
 FPLED_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL LEDS
 FPSW_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL SWITCHES
 ;
-DSRTCENABLE	.SET	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+DSRTCENABLE	.SET	FALSE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
 RP5RTCENABLE	.SET	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
 ;
-UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
-ACIAENABLE	.SET	TRUE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
-SIOENABLE	.SET	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+UARTENABLE	.SET	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+ACIAENABLE	.SET	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+SIOENABLE	.SET	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
+EZ80UARTENABLE	.SET	TRUE		; EZ80UART: ENABLE EZ80 UART DRIVER (EZ80UART.ASM)
 ;
 LPTENABLE	.SET	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
 ;
@@ -54,11 +56,11 @@ AY38910ENABLE	.SET	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
 AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC]
 SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
 ;
-FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDENABLE	.SET	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
 ;
-IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
-PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+IDEENABLE	.SET	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+PPIDEENABLE	.SET	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
 SDENABLE	.SET	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
 SDMODE		.SET	SDMODE_PIO	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|USR]
 SDCNT		.SET	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT SC ONLY
diff --git a/Source/HBIOS/cfg_rcez80.asm b/Source/HBIOS/cfg_rcez80.asm
index 629de8cb..93bcea3c 100644
--- a/Source/HBIOS/cfg_rcez80.asm
+++ b/Source/HBIOS/cfg_rcez80.asm
@@ -31,7 +31,7 @@ AUTOCON		.EQU	TRUE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
 CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
 CPUOSC		.EQU	7372800		; CPU OSC FREQ IN MHZ
-INTMODE		.EQU	1		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
+INTMODE		.EQU	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
 DEFSERCFG	.EQU	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
@@ -165,7 +165,8 @@ ACIA1CLK	.EQU	CPUOSC		; ACIA 1: OSC FREQ IN HZ
 ACIA1DIV	.EQU	1		; ACIA 1: SERIAL CLOCK DIVIDER
 ACIA1CFG	.EQU	DEFSERCFG	; ACIA 1: SERIAL LINE CONFIG  (SEE STD.ASM)
 ;
-SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+EZ80UARTENABLE	.EQU	TRUE		; EZ80UART: ENABLE EZ80 UART SERIAL DRIVER (EZ80UART.ASM)
+SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
diff --git a/Source/HBIOS/ez80uart.asm b/Source/HBIOS/ez80uart.asm
new file mode 100644
index 00000000..c9239c30
--- /dev/null
+++ b/Source/HBIOS/ez80uart.asm
@@ -0,0 +1,87 @@
+;
+;==================================================================================================
+; eZ80 UART DRIVER (SERIAL PORT)
+;==================================================================================================
+;
+
+UART0_LSR	.EQU	$C5
+UART0_THR       .EQU	$C0
+
+LSR_THRE	.EQU	$20
+
+#DEFINE IN0_A(p)	.DB	$ED,$38,p
+#DEFINE OUT0_A(p)	.DB	$ED,$39,p
+
+; #DEFINE CALLIL(a,b)	.DB	$5B,$CD \	.DW b	\ .DB b
+
+EZUART_PREINIT:
+	LD	E, 'A'
+	CALL	EZUART_OUT
+	LD	E, 'B'
+	CALL	EZUART_OUT
+	LD	E, 'C'
+	CALL	EZUART_OUT
+	LD	E, 'D'
+	CALL	EZUART_OUT
+	LD	E, 13
+	CALL	EZUART_OUT
+	LD	E, 10
+	CALL	EZUART_OUT
+	RET
+
+EZUART_INIT:
+	LD	E, '1'
+	CALL	EZUART_OUT
+	LD	E, '2'
+	CALL	EZUART_OUT
+	LD	E, '3'
+	CALL	EZUART_OUT
+	LD	E, '4'
+	CALL	EZUART_OUT
+	LD	E, 13
+	CALL	EZUART_OUT
+	LD	E, 10
+	CALL	EZUART_OUT
+
+	;call.il, $001000
+	.db	$5B,$CD
+	.dw	$1000
+	.db	$00
+
+	RET
+
+EZUART_IN:
+
+;
+; OUT CHAR IN E
+EZUART_OUT:
+	; WAIT FOR UART TO BE READY FOR TX
+WAIT_FOR_TX_READY:
+	; IN0	A,(UART0_LSR)		; /*ED38C5*/
+	IN0_A	(UART0_LSR)
+	AND	LSR_THRE
+	JR	Z,WAIT_FOR_TX_READY
+     
+	; SEND THE CHAR
+	LD	A, E
+	; OUT0	(UART0_LSR),A		; ED39C0
+	OUT0_A	(UART0_THR)
+	RET
+
+EZUART_IST:
+EZUART_OST:
+EZUART_INITDEV:
+EZUART_QUERY:
+EZUART_DEVICE:
+	RET
+	
+EZUART_FNTBL:
+	.DW	EZUART_IN
+	.DW	EZUART_OUT
+	.DW	EZUART_IST
+	.DW	EZUART_OST
+	.DW	EZUART_INITDEV
+	.DW	EZUART_QUERY
+	.DW	EZUART_DEVICE
+#IF (($ - EZUART_FNTBL) != (CIO_FNCNT * 2))
+	.ECHO	"*** INVALID EZUART FUNCTION TABLE ***\n"
diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm
index b588ae73..160bbb00 100644
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@@ -623,11 +623,20 @@ HBX_ROM:
 ;
 HBX_ROM:
 	RLCA				; TIMES 2 - GET 16K PAGE INSTEAD OF 32K
+ #IF (CPU_FAM == CPU_EZ80)
+	PUSH	BC
+	LD	BC,EZ80IOBASE<<8+MPGSEL_0
+	OUT	(C),A			; BANK_0: 0K - 16K
+	INC	A
+	INC	BC			; BC = MPGSEL_0
+	OUT	(C),A			; BANK_1: 16K - 32K
+ #ELSE
 	OUT	(MPGSEL_0),A		; BANK_0: 0K - 16K
 	INC	A			;
 	OUT	(MPGSEL_1),A		; BANK_1: 16K - 32K
-  #IF (CPUFAM == CPU_Z280)
+    #IF (CPUFAM == CPU_Z280)
 	PCACHE
+    #ENDIF
   #ENDIF
 	RET				; DONE
 #ENDIF
@@ -1809,7 +1818,7 @@ ROMRESUME:
 ; THEN IT MEANS THE S100 MONITOR IS ATTEMPTING TO REBOOT INTO ROMWBW
 ; HBIOS AND WE ABORT THE TRANSITION TO THE S100 MONITOR.
 ;
-#IF ((PLATFORM == PLT_S100) & TRUE)
+#IF (PLATFORM == PLT_S100)
 	; CHECK S100 BOARD DIP SWITCH, BIT 1
 	IN	A,($75)			; READ SWITCHES
 	BIT	1,A			; CHECK BIT 1
@@ -1843,9 +1852,19 @@ S100MON_SKIP:
 ; SEE COMMENTS ABOVE REGARDING THE FUNKY WAY THAT THE RTCDEFVAL IS
 ; CREATED.
 ;
+#IF (CPUFAM == CPU_EZ80)
+#DEFINE OUTA(p)	PUSH BC 
+#DEFCONT \ 		LD	BC,EZ80IOBASE << 8 + p
+#DEFCONT \ 		OUT	(C),A 
+#DEFCONT \ 		POP BC
+#ELSE
+#DEFINE OUTA(P) OUT	(RTCIO),A
+#ENDIF
+
+
 	LD	A,(RTCDEFVAL)
 	LD	(HB_RTCVAL),A
-	OUT	(RTCIO),A		; SET IT
+	OUTA(RTCIO)			; SET IT
 	DIAG(1)				; REAPPLY CURRENT DIAG LED SETUP
 ;
 ;--------------------------------------------------------------------------------------------------
@@ -1991,7 +2010,7 @@ HB_START1:				; BNKCALL ARRIVES HERE, BUT NOW RUNNING IN RAM BANK
 ;
 	; NOTIFY THAT WE MADE THE TRANSITION!
 	FPLEDS(DIAG_03)
-	DIAG(2)
+	DIAG(2)	
 ;
 	; RECOVER DATA PASSED PRIOR TO RAM TRANSITION
 	; (HBX_LOC - 1) = BATCOND
@@ -3614,6 +3633,9 @@ HB_PCINITTBL:
 #IF (SIOENABLE)
 	.DW	SIO_PREINIT
 #ENDIF
+#IF (EZ80UARTENABLE)
+	.DW	EZUART_PREINIT
+#ENDIF
 #IF (ACIAENABLE)
 	.DW	ACIA_PREINIT
 #ENDIF
@@ -3692,6 +3714,9 @@ HB_INITTBL:
 #IF (SIOENABLE)
 	.DW	SIO_INIT
 #ENDIF
+#IF (EZ80UARTENABLE)
+	.DW	EZUART_INIT
+#ENDIF
 #IF (ACIAENABLE)
 	.DW	ACIA_INIT
 #ENDIF
@@ -8050,6 +8075,15 @@ SIZ_SIO		.EQU	$ - ORG_SIO
 		MEMECHO	" bytes.\n"
 #ENDIF
 ;
+#IF (EZ80UARTENABLE)
+ORG_EZU	.EQU	$
+  #INCLUDE "ez80uart.asm"
+SIZ_EZU		.EQU	$ - ORG_EZU
+		MEMECHO	"EZ80 UART occupies "
+		MEMECHO	SIZ_EZU
+		MEMECHO	" bytes.\n"
+#ENDIF
+;
 #IF (ACIAENABLE)
 ORG_ACIA	.EQU	$
   #INCLUDE "acia.asm"