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CTC driver fine tuning

patch
Wayne Warthen 6 years ago
parent
8ad2bdbb29
commit
57f78d1a6b
13 changed files with 98 additions and 50 deletions
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  1. 4
      Source/HBIOS/Config/RCZ80_kio.asm
  2. 11
      Source/HBIOS/cfg_ezz80.asm
  3. 11
      Source/HBIOS/cfg_master.asm
  4. 3
      Source/HBIOS/cfg_mk4.asm
  5. 3
      Source/HBIOS/cfg_n8.asm
  6. 11
      Source/HBIOS/cfg_rcz180.asm
  7. 11
      Source/HBIOS/cfg_rcz80.asm
  8. 10
      Source/HBIOS/cfg_sbc.asm
  9. 11
      Source/HBIOS/cfg_scz180.asm
  10. 3
      Source/HBIOS/cfg_zeta2.asm
  11. 66
      Source/HBIOS/ctc.asm
  12. 2
      Source/ver.inc
  13. 2
      Source/ver.lib

4
Source/HBIOS/Config/RCZ80_kio.asm
View File

@ -42,6 +42,6 @@ SIOCNT .SET 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
SIO0MODE .SET SIOMODE_STD ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
SIO0BASE .SET KIOBASE+$08 ; SIO 0: REGISTERS BASE ADR
SIO0ACLK .SET 1843200 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO0ACTCC .SET 0 ; SIO 0A: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE
SIO0ACTCC .SET 0 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
SIO0BCLK .SET 1843200 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO0BCTCC .SET 1 ; SIO 0A: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE
SIO0BCTCC .SET 1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE

11
Source/HBIOS/cfg_ezz80.asm
View File

@ -41,8 +41,9 @@ KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT
KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS
;
CTCENABLE .EQU TRUE ; ENABLE ZILOG CTC SUPPORT
CTCMODE .EQU CTCMODE_EZ ; CTC MODE: CTCMODE_[ZP|Z2|EZ|RC]
CTCBASE .EQU $88 ; CTC BASE I/O ADDRESS
CTCTIMER .EQU TRUE ; ENABLE CTC PERIODIC TIMER
CTCMODE .EQU CTCMODE_EZ ; CTC MODE: CTCMODE_[ZP|Z2|EZ|RC]
;
DIAGENABLE .EQU FALSE ; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS
@ -90,18 +91,18 @@ SIO0MODE .EQU SIOMODE_STD ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR
SIO0ACLK .EQU 1843200 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO0ACFG .EQU DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG
SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE
SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
SIO0BCLK .EQU 1843200 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO0BCFG .EQU DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG
SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE
SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR
SIO1ACLK .EQU 7372800 ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO1ACFG .EQU DEFSERCFG ; SIO 1A: SERIAL LINE CONFIG
SIO1ACTCC .EQU -1 ; SIO 1A: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE
SIO1ACTCC .EQU -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
SIO1BCLK .EQU 7372800 ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO1BCFG .EQU DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG
SIO1BCTCC .EQU -1 ; SIO 1B: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE
SIO1BCTCC .EQU -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
;
XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG
;

11
Source/HBIOS/cfg_master.asm
View File

@ -59,8 +59,9 @@ KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT
KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS
;
CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT
CTCBASE .EQU $B0 ; CTC BASE I/O ADDRESS
CTCTIMER .EQU FALSE ; ENABLE CTC PERIODIC TIMER
CTCMODE .EQU CTCMODE_ZP ; CTC MODE: CTCMODE_[ZP|Z2|EZ|RC]
CTCBASE .EQU $20 ; CTC BASE I/O ADDRESS
;
DIAGENABLE .EQU FALSE ; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS
@ -125,18 +126,18 @@ SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR
SIO0ACLK .EQU CPUOSC ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO0ACFG .EQU DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG
SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE
SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
SIO0BCLK .EQU CPUOSC ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO0BCFG .EQU DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG
SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE
SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR
SIO1ACLK .EQU CPUOSC ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO1ACFG .EQU DEFSERCFG ; SIO 1A: SERIAL LINE CONFIG
SIO1ACTCC .EQU -1 ; SIO 1A: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE
SIO1ACTCC .EQU -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
SIO1BCLK .EQU CPUOSC ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO1BCFG .EQU DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG
SIO1BCTCC .EQU -1 ; SIO 1B: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE
SIO1BCTCC .EQU -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
;
XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG
;

3
Source/HBIOS/cfg_mk4.asm
View File

@ -46,6 +46,9 @@ KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT
KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS
;
CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT
CTCBASE .EQU $B0 ; CTC BASE I/O ADDRESS
CTCTIMER .EQU FALSE ; ENABLE CTC PERIODIC TIMER
CTCMODE .EQU CTCMODE_ZP ; CTC MODE: CTCMODE_[ZP|Z2|EZ|RC]
;
DIAGENABLE .EQU FALSE ; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS

3
Source/HBIOS/cfg_n8.asm
View File

@ -49,6 +49,9 @@ KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT
KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS
;
CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT
CTCBASE .EQU $B0 ; CTC BASE I/O ADDRESS
CTCTIMER .EQU FALSE ; ENABLE CTC PERIODIC TIMER
CTCMODE .EQU CTCMODE_ZP ; CTC MODE: CTCMODE_[ZP|Z2|EZ|RC]
;
DIAGENABLE .EQU FALSE ; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS

11
Source/HBIOS/cfg_rcz180.asm
View File

@ -46,6 +46,9 @@ KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT
KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS
;
CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT
CTCBASE .EQU $88 ; CTC BASE I/O ADDRESS
CTCTIMER .EQU FALSE ; ENABLE CTC PERIODIC TIMER
CTCMODE .EQU CTCMODE_RC ; CTC MODE: CTCMODE_[ZP|Z2|EZ|RC]
;
DIAGENABLE .EQU TRUE ; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS
@ -95,18 +98,18 @@ SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR
SIO0ACLK .EQU 7372800 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO0ACFG .EQU SER_115200_8N1 ; SER_115200_8N1 0A: SERIAL LINE CONFIG
SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE
SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
SIO0BCLK .EQU 7372800 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO0BCFG .EQU SER_115200_8N1 ; SIO 0B: SERIAL LINE CONFIG
SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE
SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR
SIO1ACLK .EQU 7372800 ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO1ACFG .EQU SER_115200_8N1 ; SER_115200_8N1 1A: SERIAL LINE CONFIG
SIO1ACTCC .EQU -1 ; SIO 1A: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE
SIO1ACTCC .EQU -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
SIO1BCLK .EQU 7372800 ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO1BCFG .EQU SER_115200_8N1 ; SIO 1B: SERIAL LINE CONFIG
SIO1BCTCC .EQU -1 ; SIO 1B: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE
SIO1BCTCC .EQU -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
;
XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG
;

11
Source/HBIOS/cfg_rcz80.asm
View File

@ -40,8 +40,9 @@ KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT
KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS
;
CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT
CTCMODE .EQU CTCMODE_RC ; CTC MODE: CTCMODE_[ZP|Z2|EZ|RC]
CTCBASE .EQU $88 ; CTC BASE I/O ADDRESS
CTCTIMER .EQU TRUE ; ENABLE CTC PERIODIC TIMER
CTCMODE .EQU CTCMODE_RC ; CTC MODE: CTCMODE_[ZP|Z2|EZ|RC]
;
DIAGENABLE .EQU TRUE ; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS
@ -99,18 +100,18 @@ SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR
SIO0ACLK .EQU CPUOSC ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO0ACFG .EQU DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG
SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE
SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
SIO0BCLK .EQU CPUOSC ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO0BCFG .EQU DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG
SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE
SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR
SIO1ACLK .EQU CPUOSC ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO1ACFG .EQU DEFSERCFG ; SIO 1A: SERIAL LINE CONFIG
SIO1ACTCC .EQU -1 ; SIO 1A: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE
SIO1ACTCC .EQU -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
SIO1BCLK .EQU CPUOSC ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO1BCFG .EQU DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG
SIO1BCTCC .EQU -1 ; SIO 1B: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE
SIO1BCTCC .EQU -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
;
XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG
;

10
Source/HBIOS/cfg_sbc.asm
View File

@ -38,8 +38,9 @@ KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT
KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS
;
CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT
CTCMODE .EQU CTCMODE_ZP ; CTC MODE: CTCMODE_[ZP|Z2|EZ|RC]
CTCBASE .EQU $80 ; CTC BASE I/O ADDRESS
CTCBASE .EQU $B0 ; CTC BASE I/O ADDRESS
CTCTIMER .EQU TRUE ; ENABLE CTC PERIODIC TIMER
CTCMODE .EQU CTCMODE_ZP ; CTC TIMER MODE: CTCMODE_[ZP|Z2|EZ|RC]
;
DIAGENABLE .EQU FALSE ; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS
@ -89,14 +90,13 @@ SIOENABLE .EQU TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT
SIOCNT .EQU 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
SIO0MODE .EQU SIOMODE_ZP ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
SIO0CTCC .EQU -1 ; SIO 0: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE
SIO0BASE .EQU $B0 ; SIO 0: REGISTERS BASE ADR
SIO0ACLK .EQU (4915200/8) ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO0ACFG .EQU DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG
SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE
SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
SIO0BCLK .EQU (4915200/8) ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO0BCFG .EQU DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG
SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE
SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
;
XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG
;

11
Source/HBIOS/cfg_scz180.asm
View File

@ -41,6 +41,9 @@ KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT
KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS
;
CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT
CTCBASE .EQU $88 ; CTC BASE I/O ADDRESS
CTCTIMER .EQU FALSE ; ENABLE CTC PERIODIC TIMER
CTCMODE .EQU CTCMODE_RC ; CTC MODE: CTCMODE_[ZP|Z2|EZ|RC]
;
DIAGENABLE .EQU TRUE ; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
DIAGPORT .EQU $0D ; DIAGNOSTIC PORT ADDRESS
@ -90,18 +93,18 @@ SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR
SIO0ACLK .EQU 7372800 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO0ACFG .EQU SER_115200_8N1 ; SIO 0A: SERIAL LINE CONFIG
SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE
SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
SIO0BCLK .EQU 7372800 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO0BCFG .EQU SER_115200_8N1 ; SIO 0B: SERIAL LINE CONFIG
SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE
SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR
SIO1ACLK .EQU 7372800 ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO1ACFG .EQU SER_115200_8N1 ; SIO 1A: SERIAL LINE CONFIG
SIO1ACTCC .EQU -1 ; SIO 1A: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE
SIO1ACTCC .EQU -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
SIO1BCLK .EQU 7372800 ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO1BCFG .EQU SER_115200_8N1 ; SIO 1B: SERIAL LINE CONFIG
SIO1BCTCC .EQU -1 ; SIO 1B: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE
SIO1BCTCC .EQU -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
;
XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG
;

3
Source/HBIOS/cfg_zeta2.asm
View File

@ -41,8 +41,9 @@ KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT
KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS
;
CTCENABLE .EQU TRUE ; ENABLE ZILOG CTC SUPPORT
CTCMODE .EQU CTCMODE_Z2 ; CTC MODE: CTCMODE_[ZP|Z2|EZ|RC]
CTCBASE .EQU $20 ; CTC BASE I/O ADDRESS
CTCTIMER .EQU TRUE ; ENABLE CTC PERIODIC TIMER
CTCMODE .EQU CTCMODE_Z2 ; CTC MODE: CTCMODE_[ZP|Z2|EZ|RC]
;
DIAGENABLE .EQU FALSE ; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS

66
Source/HBIOS/ctc.asm
View File

@ -5,53 +5,76 @@
; DISPLAY CONFIGURATION DETAILS
;______________________________________________________________________________________________________________________
;
#IF (CTCTIMER)
;
; ONLY IM2 IMPLEMENTED BELOW. I DON'T SEE ANY REASONABLE WAY TO
; IMPLEMENT AN IM1 TIMER BECAUSE THE CTC PROVIDES NO WAY TO
; DETERMINE IF IT WAS THE CAUSE OF AN INTERRUPT OR A WAY TO
; DETERMINE WHICH CHANNEL CAUSED AN INTERRUPT.
;
#IF (INTMODE != 2)
#IF (INTMODE != 2)
.ECHO "*** ERROR: CTC REQUIRES INTMODE 2!!!\n"
!!! ; FORCE AN ASSEMBLY ERROR
#ENDIF
#ENDIF
;
; CONFIGURATION
;
#IF (CTCMODE == CTCMODE_ZP)
#IF (CTCMODE == CTCMODE_ZP)
CTCPC .EQU CTCC ; PRESCALE CHANNEL
CTCPCC .EQU 0 ; PRESCALE CHANNEL CONSTANT
CTCTC .EQU CTCD ; TIMER CHANNEL
CTCTCC .EQU 48 ; TIMER CHANNEL CONSTANT
CTCTIVT .EQU INT_CTC0D ; TIMER CHANNEL IVT ENTRY
#ENDIF
#ENDIF
;
#IF (CTCMODE == CTCMODE_Z2)
#IF (CTCMODE == CTCMODE_Z2)
CTCPC .EQU CTCA ; PRESCALE CHANNEL
CTCPCC .EQU 0 ; PRESCALE CHANNEL CONSTANT
CTCTC .EQU CTCB ; TIMER CHANNEL
CTCTCC .EQU 72 ; TIMER CHANNEL CONSTANT
CTCTIVT .EQU INT_CTC0B ; TIMER CHANNEL IVT ENTRY
#ENDIF
#ENDIF
;
#IF (CTCMODE == CTCMODE_EZ)
#IF (CTCMODE == CTCMODE_EZ)
CTCPC .EQU CTCC ; PRESCALE CHANNEL
CTCPCC .EQU 0 ; PRESCALE CHANNEL CONSTANT
CTCTC .EQU CTCD ; TIMER CHANNEL
CTCTCC .EQU 72 ; TIMER CHANNEL CONSTANT
CTCTIVT .EQU INT_CTC0D ; TIMER CHANNEL IVT ENTRY
#ENDIF
#ENDIF
;
#IF (CTCMODE == CTCMODE_RC)
#IF (CTCMODE == CTCMODE_RC)
CTCPC .EQU CTCC ; PRESCALE CHANNEL
CTCPCC .EQU 0 ; PRESCALE CHANNEL CONSTANT
CTCTC .EQU CTCD ; TIMER CHANNEL
CTCTCC .EQU 144 ; TIMER CHANNEL CONSTANT
CTCTIVT .EQU INT_CTC0D ; TIMER CHANNEL IVT ENTRY
#ENDIF
;
#ENDIF
;
;
;
CTC_PREINIT:
;
; RESET ALL CTC CHANNELS
LD B,4 ; 4 CHANNELS
LD C,CTCBASE ; FIRST CHANNEL PORT
CTC_PREINIT1:
LD A,%01010011 ; CTCC CONTROL WORD VALUE
; |||||||+-- 1=CONTROL WORD FLAG
; ||||||+--- 1=SOFTWARE RESET
; |||||+---- 0=TIME CONSTANT DOES NOT FOLLOW
; ||||+----- 0=AUTO TRIGGER WHEN TIME CONST LOADED
; |||+------ 1=RISING EDGE TRIGGER
; ||+------- 0=PRESCALER OF 16
; |+-------- 1=COUNTER MODE
; +--------- 0=NO INTERRUPTS
OUT (C),A ; CTC COMMAND
INC C ; NEXT CHANNEL PORT
DJNZ CTC_PREINIT1
;
#IF (CTCTIMER)
; SETUP TIMER INTERRUPT IVT SLOT
LD HL,HB_TIMINT ; TIMER INT HANDLER ADR
LD (IVT(CTCTIVT)),HL ; IVT ENTRY FOR TIMER CHANNEL
@ -93,6 +116,8 @@ CTC_PREINIT:
OUT (CTCTC),A ; SETUP TIMER CHANNEL
LD A,CTCTCC ; TIMER CHANNEL CONSTANT
OUT (CTCTC),A ; SET TIMER CONSTANT
;
#ENDIF
;
XOR A
RET
@ -103,19 +128,26 @@ CTC_INIT: ; MINIMAL INIT
CTC_PRTCFG:
; ANNOUNCE PORT
CALL NEWLINE ; FORMATTING
PRTS("CTC: MODE=$") ; FORMATTING
#IF (CTCMODE == CTCMODE_ZP)
PRTS("CTC:$") ; FORMATTING
;
#IF (CTCTIMER)
;
PRTS(" TIMER MODE=$") ; FORMATTING
#IF (CTCMODE == CTCMODE_ZP)
PRTS("ZP$")
#ENDIF
#IF (CTCMODE == CTCMODE_Z2)
#ENDIF
#IF (CTCMODE == CTCMODE_Z2)
PRTS("Z2$")
#ENDIF
#IF (CTCMODE == CTCMODE_EZ)
#ENDIF
#IF (CTCMODE == CTCMODE_EZ)
PRTS("EZ$")
#ENDIF
#IF (CTCMODE == CTCMODE_RC)
#ENDIF
#IF (CTCMODE == CTCMODE_RC)
PRTS("RC$")
#ENDIF
;
#ENDIF
;
PRTS(" IO=0x$") ; FORMATTING
LD A,CTCBASE ; GET BASE PORT
CALL PRTHEXBYTE ; PRINT BASE PORT

2
Source/ver.inc
View File

@ -2,4 +2,4 @@
#DEFINE RMN 1
#DEFINE RUP 0
#DEFINE RTP 0
#DEFINE BIOSVER "3.1-pre.3"
#DEFINE BIOSVER "3.1-pre.4"

2
Source/ver.lib
View File

@ -3,5 +3,5 @@ rmn equ 1
rup equ 0
rtp equ 0
biosver macro
db "3.1-pre.3"
db "3.1-pre.4"
endm

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