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Finalize RC2014 floppy updates 

RC2014 floppy controller support completed and tested for Scott Baker
SMC and WDC controller modules.  FDU application updated as well.
patch
Wayne Warthen 8 years ago
parent
768e41c933
commit
5fc01b4100
13 changed files with 245 additions and 97 deletions
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  1. 4
      Binary/RomList.txt
  2. 3
      Doc/ChangeLog.txt
  3. 7
      Doc/FDU.txt
  4. 2
      ReadMe.txt
  5. 213
      Source/Apps/FDU/FDU.asm
  6. 7
      Source/Apps/FDU/FDU.txt
  7. 6
      Source/CBIOS/ver.inc
  8. 2
      Source/HBIOS/Config/RC_std.asm
  9. 2
      Source/HBIOS/cfg_rc.asm
  10. 70
      Source/HBIOS/fd.asm
  11. 6
      Source/HBIOS/hbios.asm
  12. 14
      Source/HBIOS/std.asm
  13. 6
      Source/HBIOS/ver.inc

4
Binary/RomList.txt
View File

@ -117,4 +117,6 @@ RC2014:
Module (SIO/2). Either one may be used. Module (SIO/2). Either one may be used.
- Includes support for Compact Flash Module - Includes support for Compact Flash Module
- Support for PPIDE Module may be enabled in config - Support for PPIDE Module may be enabled in config
- Support for Scott Baker SIO board may be enabled in config
- Support for Scott Baker SIO board may be enabled in config
- Support for Scott Baker floppy controllers (SMC & WDC) may
be enabled in config

3
Doc/ChangeLog.txt
View File

@ -1,8 +1,9 @@
Version 2.8.7
Version 2.9.0
------------- -------------
- WBW: Implemented multi-sector I/O in all disk drivers - WBW: Implemented multi-sector I/O in all disk drivers
- WBW: Added support for RC2014 SMB Floppy controller modules (SMC and WDC) - WBW: Added support for RC2014 SMB Floppy controller modules (SMC and WDC)
- WBW: New function dispatching for disk drivers - WBW: New function dispatching for disk drivers
- WBW: Updated FDU app to support RC2014 floppy controllers
Version 2.8.6 Version 2.8.6
------------- -------------

7
Doc/FDU.txt
View File

@ -473,4 +473,11 @@ Added runtime selection of FDC hardware.
Added runtime timing adjustment. Added runtime timing adjustment.
WW 12/16/2017: v5.1 WW 12/16/2017: v5.1
Improved polling version of read/write to fix occasional overrun errors. Improved polling version of read/write to fix occasional overrun errors.
WW 1/8/2018: v5.2
Added support for RC2014 hardware:
- Scott Baker SMC 9266 FDC module
- Scott Baker WDC 37C65 FDC module

2
ReadMe.txt
View File

@ -7,7 +7,7 @@
*********************************************************************** ***********************************************************************
Wayne Warthen (wwarthen@gmail.com) Wayne Warthen (wwarthen@gmail.com)
Version 2.8.6, 2017-12-10
Version 2.9.0, 2018-01-08
https://www.retrobrewcomputers.org/ https://www.retrobrewcomputers.org/
RomWBW is a ROM-based implementation of CP/M-80 2.2 and Z-System for RomWBW is a ROM-based implementation of CP/M-80 2.2 and Z-System for

213
Source/Apps/FDU/FDU.asm
View File

@ -38,6 +38,9 @@
; DYNAMIC FDC SELECTION AT STARTUP ; DYNAMIC FDC SELECTION AT STARTUP
; DYNAMIC CPU SPEED ADJUSTMENT ; DYNAMIC CPU SPEED ADJUSTMENT
; 2017-12-16: V5.1 IMPROVED POLLING READ/WRITE PERFORMANCE ; 2017-12-16: V5.1 IMPROVED POLLING READ/WRITE PERFORMANCE
; 2018-01-08: V5.2 ADDED RC2014 SUPPORT FOR:
; - SCOTT BAKER (SMB) SMC 9266 FDC
; - SCOTT BAKER (SMB) WDC 37C65 FDC
; ;
;_______________________________________________________________________________ ;_______________________________________________________________________________
; ;
@ -63,6 +66,8 @@ FDC_ZETA .EQU 2
FDC_ZETA2 .EQU 3 FDC_ZETA2 .EQU 3
FDC_DIDE .EQU 4 FDC_DIDE .EQU 4
FDC_N8 .EQU 5 FDC_N8 .EQU 5
FDC_RCSMC .EQU 6
FDC_RCWDC .EQU 7
; ;
_DIO .EQU 1 << FDC_DIO _DIO .EQU 1 << FDC_DIO
_DIO3 .EQU 1 << FDC_DIO3 _DIO3 .EQU 1 << FDC_DIO3
@ -70,6 +75,8 @@ _ZETA .EQU 1 << FDC_ZETA
_ZETA2 .EQU 1 << FDC_ZETA2 _ZETA2 .EQU 1 << FDC_ZETA2
_DIDE .EQU 1 << FDC_DIDE _DIDE .EQU 1 << FDC_DIDE
_N8 .EQU 1 << FDC_N8 _N8 .EQU 1 << FDC_N8
_RCSMC .EQU 1 << FDC_RCSMC
_RCWDC .EQU 1 << FDC_RCWDC
; ;
FALSE .EQU 0 FALSE .EQU 0
TRUE .EQU ~FALSE TRUE .EQU ~FALSE
@ -197,7 +204,7 @@ INIT5:
XOR A XOR A
RET RET
STR_BANNER .DB "Floppy Disk Utility (FDU) v5.1, 16-Dec-2017$"
STR_BANNER .DB "Floppy Disk Utility (FDU) v5.2, 08-Jan-2018$"
STR_BANNER2 .DB "Copyright (C) 2017, Wayne Warthen, GNU GPL v3","$" STR_BANNER2 .DB "Copyright (C) 2017, Wayne Warthen, GNU GPL v3","$"
STR_HBIOS .DB " [HBIOS]$" STR_HBIOS .DB " [HBIOS]$"
STR_UBIOS .DB " [UBIOS]$" STR_UBIOS .DB " [UBIOS]$"
@ -276,6 +283,8 @@ FDCTBL: ; LABEL CONFIG DATA
.DW STR_ZETA2, CFG_ZETA2 .DW STR_ZETA2, CFG_ZETA2
.DW STR_DIDE, CFG_DIDE .DW STR_DIDE, CFG_DIDE
.DW STR_N8, CFG_N8 .DW STR_N8, CFG_N8
.DW STR_RCSMC, CFG_RCSMC
.DW STR_RCWDC, CFG_RCWDC
FDCCNT .EQU ($-FDCTBL)/4 ; FD CONTROLLER COUNT FDCCNT .EQU ($-FDCTBL)/4 ; FD CONTROLLER COUNT
; ;
; FDC LABEL STRINGS ; FDC LABEL STRINGS
@ -284,8 +293,10 @@ STR_DIO .TEXT "DISKIO$"
STR_DIO3 .TEXT "DISKIO3$" STR_DIO3 .TEXT "DISKIO3$"
STR_ZETA .TEXT "ZETA$" STR_ZETA .TEXT "ZETA$"
STR_ZETA2 .TEXT "ZETA2$" STR_ZETA2 .TEXT "ZETA2$"
STR_DIDE .TEXT "DUAL-IDE$"
STR_DIDE .TEXT "D-IDE$"
STR_N8 .TEXT "N8$" STR_N8 .TEXT "N8$"
STR_RCSMC .TEXT "RC-SMC$"
STR_RCWDC .TEXT "RC-WDC$"
; ;
; FDC CONFIGURATION BLOCKS ; FDC CONFIGURATION BLOCKS
; ;
@ -340,6 +351,26 @@ CFG_N8:
.DB 093H ; TERMINAL COUNT (W/ DACK) .DB 093H ; TERMINAL COUNT (W/ DACK)
.DB 0FFH ; NOT USED BY N8 .DB 0FFH ; NOT USED BY N8
; ;
CFG_RCSMC:
.DB 050H ; FDC MAIN STATUS REGISTER
.DB 051H ; FDC DATA PORT
.DB 0FFH ; DATA INPUT REGISTER
.DB 058H ; DIGITAL OUTPUT REGISTER (LATCH)
.DB 0FFH ; DCR
.DB 0FFH ; DACK
.DB 0FFH ; TERMINAL COUNT (W/ DACK)
.DB 0FFH ; PSEUDO DMA DATA PORT
;
CFG_RCWDC:
.DB 050H ; FDC MAIN STATUS REGISTER
.DB 051H ; FDC DATA PORT
.DB 0FFH ; DATA INPUT REGISTER
.DB 058H ; DIGITAL OUTPUT REGISTER (LATCH)
.DB 048H ; DCR
.DB 0FFH ; DACK
.DB 058H ; TERMINAL COUNT (W/ DACK)
.DB 0FFH ; PSEUDO DMA DATA PORT
;
FDCID .DB 0 ; FDC IDENTIFIER (0 INDEXED) FDCID .DB 0 ; FDC IDENTIFIER (0 INDEXED)
FDCBM .DB 0 ; FDC ID BITMAP FDCBM .DB 0 ; FDC ID BITMAP
FDCLBL .DW 0 ; POINTER TO ACTIVE FDC LABEL STRING FDCLBL .DW 0 ; POINTER TO ACTIVE FDC LABEL STRING
@ -355,6 +386,8 @@ FSS_MENU:
.TEXT " (4) Zeta 2 SBC Onboard FDC\r\n" .TEXT " (4) Zeta 2 SBC Onboard FDC\r\n"
.TEXT " (5) Dual IDE ECB Board\r\n" .TEXT " (5) Dual IDE ECB Board\r\n"
.TEXT " (6) N8 Onboard FDC\r\n" .TEXT " (6) N8 Onboard FDC\r\n"
.TEXT " (7) RC2014 SMC (SMB)\r\n"
.TEXT " (8) RC2014 WDC (SMB)\r\n"
.TEXT "=== OPTION ===> $\r\n" .TEXT "=== OPTION ===> $\r\n"
; ;
;=============================================================================== ;===============================================================================
@ -1424,12 +1457,14 @@ MD_DRQWAIT .EQU 4
; BIT IS SET FOR ALLOWED MODES PER FDC ; BIT IS SET FOR ALLOWED MODES PER FDC
; ;
MD_MAP: MD_MAP:
.DB %00011111 ; DIO: POLL,INT,INTFAST,INTWAIT,DRQWAIT
.DB %00000111 ; DIO3: POLL,INT,INTFAST
.DB %00000111 ; ZETA: POLL,INT,INTFAST
.DB %00000001 ; ZETA2:POLL
.DB %00000001 ; DIDE: POLL
.DB %00000001 ; N8: POLL
.DB %00011111 ; DIO POLL,INT,INTFAST,INTWAIT,DRQWAIT
.DB %00000111 ; DIO3 POLL,INT,INTFAST
.DB %00000111 ; ZETA POLL,INT,INTFAST
.DB %00000001 ; ZETA2 POLL
.DB %00000001 ; DIDE POLL
.DB %00000001 ; N8 POLL
.DB %00000001 ; RCSMC POLL
.DB %00000001 ; RCWDC POLL
; ;
; MEDIA DESCRIPTION BLOCK ; MEDIA DESCRIPTION BLOCK
; ;
@ -1451,6 +1486,7 @@ MDB_HLT .DB 000H ; HEAD LOAD TIME, IBM PS/2 CALLS FOR 15ms 08H = 16ms HUT
MDB_DORA .DB 000H ; OPERATIONS REGISTER VALUE FOR MEDIA MDB_DORA .DB 000H ; OPERATIONS REGISTER VALUE FOR MEDIA
MDB_DORB .DB 000H ; OPERATIONS REGISTER VALUE FOR MEDIA MDB_DORB .DB 000H ; OPERATIONS REGISTER VALUE FOR MEDIA
MDB_DORC .DB 000H ; OPERATIONS REGISTER VALUE FOR MEDIA MDB_DORC .DB 000H ; OPERATIONS REGISTER VALUE FOR MEDIA
MDB_DORD .DB 000H ; OPERATIONS REGISTER VALUE FOR MEDIA
MDB_DCR .DB 000H ; CONTROL REGISTER VALUE FOR MEDIA MDB_DCR .DB 000H ; CONTROL REGISTER VALUE FOR MEDIA
MDB_LEN .EQU $ - MDB MDB_LEN .EQU $ - MDB
; ;
@ -1549,6 +1585,7 @@ FCB_PC720 .DB 009H ; SECTOR COUNT
.DB DORA_BR250 ; OPERATIONS REGISTER VALUE .DB DORA_BR250 ; OPERATIONS REGISTER VALUE
.DB DORB_BR250 ; OPERATIONS REGISTER VALUE .DB DORB_BR250 ; OPERATIONS REGISTER VALUE
.DB DORC_BR250 ; OPERATIONS REGISTER VALUE .DB DORC_BR250 ; OPERATIONS REGISTER VALUE
.DB DORD_BR250 ; OPERATIONS REGISTER VALUE
.DB DCR_BR250 ; CONTROL REGISTER VALUE .DB DCR_BR250 ; CONTROL REGISTER VALUE
.IF (($ - MDB_PC720) != MDB_LEN) .IF (($ - MDB_PC720) != MDB_LEN)
.ECHO "*** FCB SIZE ERROR!!! ***\n" .ECHO "*** FCB SIZE ERROR!!! ***\n"
@ -1571,6 +1608,7 @@ FCB_PC144 .DB 012H ; SECTOR COUNT
.DB DORA_BR500 ; OPERATIONS REGISTER VALUE .DB DORA_BR500 ; OPERATIONS REGISTER VALUE
.DB DORB_BR500 ; OPERATIONS REGISTER VALUE .DB DORB_BR500 ; OPERATIONS REGISTER VALUE
.DB DORC_BR500 ; OPERATIONS REGISTER VALUE .DB DORC_BR500 ; OPERATIONS REGISTER VALUE
.DB DORD_BR500 ; OPERATIONS REGISTER VALUE
.DB DCR_BR500 ; CONTROL REGISTER VALUE .DB DCR_BR500 ; CONTROL REGISTER VALUE
.IF (($ - MDB_PC144) != MDB_LEN) .IF (($ - MDB_PC144) != MDB_LEN)
.ECHO "*** FCB SIZE ERROR!!! ***\n" .ECHO "*** FCB SIZE ERROR!!! ***\n"
@ -1593,6 +1631,7 @@ FCB_PC320 .DB 008H ; SECTOR COUNT
.DB DORA_BR250 ; OPERATIONS REGISTER VALUE .DB DORA_BR250 ; OPERATIONS REGISTER VALUE
.DB DORB_BR250 ; OPERATIONS REGISTER VALUE .DB DORB_BR250 ; OPERATIONS REGISTER VALUE
.DB DORC_BR250 ; OPERATIONS REGISTER VALUE .DB DORC_BR250 ; OPERATIONS REGISTER VALUE
.DB DORD_BR250 ; OPERATIONS REGISTER VALUE
.DB DCR_BR250 ; CONTROL REGISTER VALUE .DB DCR_BR250 ; CONTROL REGISTER VALUE
.IF (($ - MDB_PC320) != MDB_LEN) .IF (($ - MDB_PC320) != MDB_LEN)
.ECHO "*** FCB SIZE ERROR!!! ***\n" .ECHO "*** FCB SIZE ERROR!!! ***\n"
@ -1615,6 +1654,7 @@ FCB_PC360 .DB 009H ; SECTOR COUNT
.DB DORA_BR250 ; OPERATIONS REGISTER VALUE .DB DORA_BR250 ; OPERATIONS REGISTER VALUE
.DB DORB_BR250 ; OPERATIONS REGISTER VALUE .DB DORB_BR250 ; OPERATIONS REGISTER VALUE
.DB DORC_BR250 ; OPERATIONS REGISTER VALUE .DB DORC_BR250 ; OPERATIONS REGISTER VALUE
.DB DORD_BR250 ; OPERATIONS REGISTER VALUE
.DB DCR_BR250 ; CONTROL REGISTER VALUE .DB DCR_BR250 ; CONTROL REGISTER VALUE
.IF (($ - MDB_PC360) != MDB_LEN) .IF (($ - MDB_PC360) != MDB_LEN)
.ECHO "*** FCB SIZE ERROR!!! ***\n" .ECHO "*** FCB SIZE ERROR!!! ***\n"
@ -1637,6 +1677,7 @@ FCB_PC120 .DB 00FH ; SECTOR COUNT
.DB DORA_BR500 ; OPERATIONS REGISTER VALUE .DB DORA_BR500 ; OPERATIONS REGISTER VALUE
.DB DORB_BR500 ; OPERATIONS REGISTER VALUE .DB DORB_BR500 ; OPERATIONS REGISTER VALUE
.DB DORC_BR500 ; OPERATIONS REGISTER VALUE .DB DORC_BR500 ; OPERATIONS REGISTER VALUE
.DB DORD_BR500 ; OPERATIONS REGISTER VALUE
.DB DCR_BR500 ; CONTROL REGISTER VALUE .DB DCR_BR500 ; CONTROL REGISTER VALUE
.IF (($ - MDB_PC120) != MDB_LEN) .IF (($ - MDB_PC120) != MDB_LEN)
.ECHO "*** FCB SIZE ERROR!!! ***\n" .ECHO "*** FCB SIZE ERROR!!! ***\n"
@ -1659,6 +1700,7 @@ FCB_PC111 .DB 00FH ; SECTOR COUNT
.DB DORA_BR500 ; OPERATIONS REGISTER VALUE .DB DORA_BR500 ; OPERATIONS REGISTER VALUE
.DB DORB_BR500 ; OPERATIONS REGISTER VALUE .DB DORB_BR500 ; OPERATIONS REGISTER VALUE
.DB DORC_BR500 ; OPERATIONS REGISTER VALUE .DB DORC_BR500 ; OPERATIONS REGISTER VALUE
.DB DORD_BR500 ; OPERATIONS REGISTER VALUE
.DB DCR_BR500 ; CONTROL REGISTER VALUE .DB DCR_BR500 ; CONTROL REGISTER VALUE
.IF (($ - MDB_PC111) != MDB_LEN) .IF (($ - MDB_PC111) != MDB_LEN)
.ECHO "*** FCB SIZE ERROR!!! ***\n" .ECHO "*** FCB SIZE ERROR!!! ***\n"
@ -1768,29 +1810,37 @@ FM_DRAW:
AND _ZETA | _DIO3 AND _ZETA | _DIO3
JR NZ,FM_DRAW0B JR NZ,FM_DRAW0B
LD A,(HL) LD A,(HL)
AND _DIDE | _N8 | _ZETA2
AND _DIDE | _N8 | _ZETA2 | _RCWDC
JR NZ,FM_DRAW0C JR NZ,FM_DRAW0C
JR FM_DRAW0D
LD A,(HL)
AND _RCSMC
JR NZ,FM_DRAW0D
JR FM_DRAW3
FM_DRAW0A: ; DIO FM_DRAW0A: ; DIO
LD A,(FST_DOR) LD A,(FST_DOR)
AND 00000010B AND 00000010B
XOR 00000010B XOR 00000010B
JR FM_DRAW0D
JR FM_DRAW1
FM_DRAW0B: ; ZETA, DIO3 FM_DRAW0B: ; ZETA, DIO3
LD A,(FST_DOR) LD A,(FST_DOR)
AND 00000010B AND 00000010B
JR FM_DRAW0D
FM_DRAW0C: ; DIDE, N8, ZETA2
JR FM_DRAW1
FM_DRAW0C: ; DIDE, N8, ZETA2, RCWDC
LD A,(FST_DOR) LD A,(FST_DOR)
AND 11110000B AND 11110000B
JR FM_DRAW0D
FM_DRAW0D:
JR FM_DRAW1
FM_DRAW0D: ; RCSMC
LD A,(FST_DOR)
AND 00000110B
JR FM_DRAW1
FM_DRAW1:
LD DE,STR_ON LD DE,STR_ON
JP NZ,FM_DRAW1
JP NZ,FM_DRAW2
LD DE,STR_OFF LD DE,STR_OFF
FM_DRAW1:
FM_DRAW2:
LD HL,MV_MOT LD HL,MV_MOT
CALL STRCPY CALL STRCPY
FM_DRAW3:
; UPDATE MSR VALUE ; UPDATE MSR VALUE
LD DE,MV_MSR LD DE,MV_MSR
@ -1913,23 +1963,30 @@ FM_MOTOR:
AND _ZETA | _DIO3 AND _ZETA | _DIO3
JR NZ,FM_MOTOR0B JR NZ,FM_MOTOR0B
LD A,(HL) LD A,(HL)
AND _DIDE | _N8 | _ZETA2
AND _DIDE | _N8 | _ZETA2 | _RCWDC
JR NZ,FM_MOTOR0C JR NZ,FM_MOTOR0C
JR FM_MOTOR0D
LD A,(HL)
AND _RCSMC
JR NZ,FM_MOTOR0D
RET
FM_MOTOR0A: ; DIO FM_MOTOR0A: ; DIO
LD A,(FST_DOR) LD A,(FST_DOR)
AND 00000010B AND 00000010B
XOR 00000010B XOR 00000010B
JR FM_MOTOR0D
JR FM_MOTOR1
FM_MOTOR0B: ; ZETA, DIO3 FM_MOTOR0B: ; ZETA, DIO3
LD A,(FST_DOR) LD A,(FST_DOR)
AND 00000010B AND 00000010B
JR FM_MOTOR0D
FM_MOTOR0C: ; DIDE, N8, ZETA2
JR FM_MOTOR1
FM_MOTOR0C: ; DIDE, N8, ZETA2, RCWDC
LD A,(FST_DOR) LD A,(FST_DOR)
AND 11110000B AND 11110000B
JR FM_MOTOR0D
FM_MOTOR0D:
JR FM_MOTOR1
FM_MOTOR0D: ; RCSMC
LD A,(FST_DOR)
AND 00000110B
JR FM_MOTOR1
FM_MOTOR1:
JP Z,FC_MOTORON JP Z,FC_MOTORON
JP FC_MOTOROFF JP FC_MOTOROFF
@ -2130,6 +2187,7 @@ FCD_HLT .DB 000H ; HEAD LOAD TIME, IBM PS/2 CALLS FOR 15ms 08H = 16ms HUT
FCD_DORA .DB 000H ; DEFAULT DOR VALUE FOR MEDIA FCD_DORA .DB 000H ; DEFAULT DOR VALUE FOR MEDIA
FCD_DORB .DB 000H ; DEFAULT DOR VALUE FOR MEDIA FCD_DORB .DB 000H ; DEFAULT DOR VALUE FOR MEDIA
FCD_DORC .DB 000H ; DEFAULT DOR VALUE FOR MEDIA FCD_DORC .DB 000H ; DEFAULT DOR VALUE FOR MEDIA
FCD_DORD .DB 000H ; DEFAULT DOR VALUE FOR MEDIA
FCD_DCR .DB 000H ; DOR VALUE FOR MEDIA FCD_DCR .DB 000H ; DOR VALUE FOR MEDIA
FCD_LEN .EQU $ - FCD FCD_LEN .EQU $ - FCD
; DYNAMICALLY MANAGED (PUBLIC) ; DYNAMICALLY MANAGED (PUBLIC)
@ -2645,27 +2703,33 @@ FC_INIT:
AND _ZETA | _DIO3 AND _ZETA | _DIO3
JR NZ,FC_INIT2 JR NZ,FC_INIT2
LD A,(HL) LD A,(HL)
AND _DIDE | _N8 | _ZETA2
AND _DIDE | _N8 | _ZETA2 | _RCWDC
JR NZ,FC_INIT3 JR NZ,FC_INIT3
JR FC_INIT4
LD A,(HL)
AND _RCSMC
JR NZ,FC_INIT4
RET
FC_INIT1: ; DIO FC_INIT1: ; DIO
LD A,(FCD_DORA) LD A,(FCD_DORA)
JR FC_INIT4
JR FC_INIT5
FC_INIT2: ; ZETA, DIO3 FC_INIT2: ; ZETA, DIO3
LD A,(FCD_DORB) LD A,(FCD_DORB)
JR FC_INIT4
FC_INIT3: ; DIDE, N8, ZETA2
JR FC_INIT5
FC_INIT3: ; DIDE, N8, ZETA2, RCWDC
LD A,(FCD_DORC) LD A,(FCD_DORC)
JR FC_INIT4
JR FC_INIT5
FC_INIT4: ; WDSMC
LD A,(FCD_DORD)
JR FC_INIT5
FC_INIT4:
FC_INIT5:
LD (FST_DOR),A LD (FST_DOR),A
CALL FC_SETDOR CALL FC_SETDOR
RET RET
; ;
; SET FST_DOR ; SET FST_DOR
; ;
FC_SETDOR
FC_SETDOR:
PUSH AF PUSH AF
LD A,(FST_DOR) LD A,(FST_DOR)
LD C,(IY+CFG_DOR) LD C,(IY+CFG_DOR)
@ -2674,28 +2738,28 @@ FC_SETDOR
RET RET
; ;
; RESET FDC BY PULSING BIT 7 OF DOR LOW ; RESET FDC BY PULSING BIT 7 OF DOR LOW
; NOTE: DIO HARDWARE HAS NO MECHANISM TO PULSE RESET VIA SOFTWARE
; ;
FC_RESETFDC: FC_RESETFDC:
LD C,(IY+CFG_DOR) LD C,(IY+CFG_DOR)
LD HL,FDCBM LD HL,FDCBM
LD A,(HL) LD A,(HL)
AND _ZETA | _DIO3
AND _ZETA | _DIO3 | _RCSMC
JR NZ,FC_RESETFDC1 JR NZ,FC_RESETFDC1
LD A,(HL) LD A,(HL)
AND _DIDE | _N8 | _ZETA2
AND _DIDE | _N8 | _ZETA2 | _RCWDC
JR NZ,FC_RESETFDC2 JR NZ,FC_RESETFDC2
JR FC_RESETFDC3
FC_RESETFDC1: ; ZETA, DIO3
RET
FC_RESETFDC1: ; ZETA, DIO3, RCSMC
LD A,(FST_DOR) LD A,(FST_DOR)
PUSH AF
RES 7,A RES 7,A
OUT (C),A OUT (C),A
PUSH AF ; SAVE AF BECAUSE DELAY TRASHES IT
CALL DELAY CALL DELAY
POP AF ; RESTORE AF
SET 7,A
POP AF
OUT (C),A OUT (C),A
JR FC_RESETFDC3 JR FC_RESETFDC3
FC_RESETFDC2: ; DIDE, N8, ZETA2
FC_RESETFDC2: ; DIDE, N8, ZETA2, RCWDC
LD A,0 LD A,0
OUT (C),A OUT (C),A
LD A,(FST_DOR) LD A,(FST_DOR)
@ -2711,7 +2775,7 @@ FC_RESETFDC3:
; ;
FC_PULSETC: FC_PULSETC:
LD A,(FDCBM) LD A,(FDCBM)
AND _DIDE | _N8 | _ZETA2
AND _DIDE | _N8 | _ZETA2 | _RCWDC
JR NZ,FC_PULSETC1 JR NZ,FC_PULSETC1
; NOT DIDE, N8, ZETA2 ; NOT DIDE, N8, ZETA2
LD C,(IY+CFG_DOR) LD C,(IY+CFG_DOR)
@ -2721,7 +2785,7 @@ FC_PULSETC:
RES 0,A RES 0,A
OUT (C),A OUT (C),A
JR FC_PULSETC2 JR FC_PULSETC2
FC_PULSETC1: ; DIDE, N8, ZETA2
FC_PULSETC1: ; DIDE, N8, ZETA2, RCWDC
LD C,(IY+CFG_TC) LD C,(IY+CFG_TC)
IN A,(C) IN A,(C)
JR FC_PULSETC2 JR FC_PULSETC2
@ -2739,18 +2803,21 @@ FC_MOTORON:
AND _ZETA | _DIO3 AND _ZETA | _DIO3
JR NZ,FC_MOTORON2 JR NZ,FC_MOTORON2
LD A,(HL) LD A,(HL)
AND _DIDE | _N8 | _ZETA2
AND _DIDE | _N8 | _ZETA2 | _RCWDC
JR NZ,FC_MOTORON3 JR NZ,FC_MOTORON3
JR FC_MOTORON4
LD A,(HL)
AND _RCSMC
JR NZ,FC_MOTORON4
RET
FC_MOTORON1: ; DIO FC_MOTORON1: ; DIO
LD HL,FST_DOR ; POINT TO FDC_DOR LD HL,FST_DOR ; POINT TO FDC_DOR
RES 1,(HL) ; SET MOTOR ON RES 1,(HL) ; SET MOTOR ON
JR FC_MOTORON4
JR FC_MOTORON5
FC_MOTORON2: ; ZETA, DIO3 FC_MOTORON2: ; ZETA, DIO3
LD HL,FST_DOR ; POINT TO FDC_DOR LD HL,FST_DOR ; POINT TO FDC_DOR
SET 1,(HL) SET 1,(HL)
JR FC_MOTORON4
FC_MOTORON3: ; DIDE, N8, ZETA2
JR FC_MOTORON5
FC_MOTORON3: ; DIDE, N8, ZETA2, RCWDC
LD HL,FST_DOR ; POINT TO FDC_DOR LD HL,FST_DOR ; POINT TO FDC_DOR
LD A,(HL) ; START WITH CURRENT DOR LD A,(HL) ; START WITH CURRENT DOR
AND 11111100B ; GET RID OF ANY ACTIVE DS BITS AND 11111100B ; GET RID OF ANY ACTIVE DS BITS
@ -2766,18 +2833,27 @@ FC_MOTORON3A:
DJNZ FC_MOTORON3A ; DS TIMES DJNZ FC_MOTORON3A ; DS TIMES
OR C ; COMBINE WITH SAVED OR C ; COMBINE WITH SAVED
LD (HL),A ; COMMIT THE NEW VALUE TO FST_DOR LD (HL),A ; COMMIT THE NEW VALUE TO FST_DOR
JR FC_MOTORON4
FC_MOTORON4:
JR FC_MOTORON5
FC_MOTORON4: ; RCSMC
LD A,(FCD_DS) ; GET CURRENT DS
LD C,00000010B ; ASSUME MOTORA (BIT 1)
OR A ; TEST FOR DS 0
JR Z,FC_MOTORON4A ; IF SO, CONTINUE W/ MOTORA
LD C,00000100B ; OTHERWISE, MOTORB (BIT 2)
FC_MOTORON4A:
LD A,(FST_DOR) ; GET CURRENT DOR VALUE
OR C ; APPLY NEW MOTOR BIT
LD (FST_DOR),A ; COMMIT NEW VALUE
JR FC_MOTORON5
FC_MOTORON5:
CALL FC_SETDOR ; OUTPUT TO CONTROLLER CALL FC_SETDOR ; OUTPUT TO CONTROLLER
CALL LDELAY ; WAIT 1/2 SEC ON MOTOR START FOR SPIN-UP CALL LDELAY ; WAIT 1/2 SEC ON MOTOR START FOR SPIN-UP
LD A,(FDCBM) LD A,(FDCBM)
AND _DIDE | _N8 | _ZETA2
JR Z,FC_MOTORON5
AND _DIDE | _N8 | _ZETA2 | _RCWDC
RET Z
LD A,(FCD_DCR) LD A,(FCD_DCR)
LD C,(IY+CFG_DCR) LD C,(IY+CFG_DCR)
OUT (C),A OUT (C),A
FC_MOTORON5:
RET RET
; ;
; SET FST_DOR FOR MOTOR CONTROL OFF ; SET FST_DOR FOR MOTOR CONTROL OFF
@ -2791,24 +2867,32 @@ FC_MOTOROFF:
AND _ZETA | _DIO3 AND _ZETA | _DIO3
JR NZ,FC_MOTOROFF2 JR NZ,FC_MOTOROFF2
LD A,(HL) LD A,(HL)
AND _DIDE | _N8 | _ZETA2
AND _DIDE | _N8 | _ZETA2 | _RCWDC
JR NZ,FC_MOTOROFF3 JR NZ,FC_MOTOROFF3
JR FC_MOTOROFF4
LD A,(HL)
AND _RCSMC
JR NZ,FC_MOTOROFF4
RET
FC_MOTOROFF1: ; DIO FC_MOTOROFF1: ; DIO
LD HL,FST_DOR ; POINT TO FDC_DOR LD HL,FST_DOR ; POINT TO FDC_DOR
SET 1,(HL) ; SET MOTOR OFF SET 1,(HL) ; SET MOTOR OFF
JR FC_MOTOROFF4
JR FC_MOTOROFF5
FC_MOTOROFF2: ; ZETA, DIO3 FC_MOTOROFF2: ; ZETA, DIO3
LD HL,FST_DOR ; POINT TO FDC_DOR LD HL,FST_DOR ; POINT TO FDC_DOR
RES 1,(HL) RES 1,(HL)
JR FC_MOTOROFF4
FC_MOTOROFF3: ; DIDE, N8, ZETA2
JR FC_MOTOROFF5
FC_MOTOROFF3: ; DIDE, N8, ZETA2, RCWDC
LD HL,FST_DOR ; POINT TO FDC_DOR LD HL,FST_DOR ; POINT TO FDC_DOR
LD A,DORC_INIT LD A,DORC_INIT
LD (HL),A LD (HL),A
JR FC_MOTOROFF4
JR FC_MOTOROFF5
FC_MOTOROFF4: ; RCSMC
LD HL,FST_DOR ; POINT TO FDC_DOR
RES 1,(HL) ; CLEAR MOTORA
RES 2,(HL) ; CLEAR MOTORB
JR FC_MOTOROFF5
FC_MOTOROFF4:
FC_MOTOROFF5:
CALL FC_SETDOR ; OUTPUT TO CONTROLLER CALL FC_SETDOR ; OUTPUT TO CONTROLLER
RET RET
; ;
@ -3661,13 +3745,20 @@ DORB_BR500 .EQU 10100000B ; 500KBPS
; ;
DORB_INIT .EQU DORB_BR250 DORB_INIT .EQU DORB_BR250
; ;
; *** DIDE/N8/ZETA2 ***
; *** DIDE/N8/ZETA2/RCWDC ***
; ;
DORC_INIT .EQU 00001100B ; SOFT RESET INACTIVE, DMA ENABLED DORC_INIT .EQU 00001100B ; SOFT RESET INACTIVE, DMA ENABLED
; ;
DORC_BR250 .EQU DORC_INIT DORC_BR250 .EQU DORC_INIT
DORC_BR500 .EQU DORC_INIT DORC_BR500 .EQU DORC_INIT
; ;
; *** RCSMC ***
;
DORD_BR250 .EQU 10100000B ; 250KBPS
DORD_BR500 .EQU 11100000B ; 500KBPS
;
DORD_INIT .EQU DORB_BR250
;
; DCR (ONLY APPLIES TO DIDE, N8, AND ZETA2) ; DCR (ONLY APPLIES TO DIDE, N8, AND ZETA2)
; ;
DCR_BR250 .EQU 01H ; 250KBPS DCR_BR250 .EQU 01H ; 250KBPS

7
Source/Apps/FDU/FDU.txt
View File

@ -473,4 +473,11 @@ Added runtime selection of FDC hardware.
Added runtime timing adjustment. Added runtime timing adjustment.
WW 12/16/2017: v5.1 WW 12/16/2017: v5.1
Improved polling version of read/write to fix occasional overrun errors. Improved polling version of read/write to fix occasional overrun errors.
WW 1/8/2018: v5.2
Added support for RC2014 hardware:
- Scott Baker SMC 9266 FDC module
- Scott Baker WDC 37C65 FDC module

6
Source/CBIOS/ver.inc
View File

@ -1,5 +1,5 @@
#DEFINE RMJ 2 #DEFINE RMJ 2
#DEFINE RMN 8
#DEFINE RUP 6
#DEFINE RMN 9
#DEFINE RUP 0
#DEFINE RTP 0 #DEFINE RTP 0
#DEFINE BIOSVER "2.8.6"
#DEFINE BIOSVER "2.9.0-pre.0"

2
Source/HBIOS/Config/RC_std.asm
View File

@ -13,7 +13,7 @@ SIOMODE .SET SIOMODE_RC ; TYPE OF SIO/2 TO DETECT: SIOMODE_RC, SIOMODE_SMB
ACIAENABLE .SET TRUE ; TRUE TO AUTO-DETECT MOTOROLA 6850 ACIA ACIAENABLE .SET TRUE ; TRUE TO AUTO-DETECT MOTOROLA 6850 ACIA
; ;
FDENABLE .SET FALSE ; TRUE FOR FLOPPY SUPPORT FDENABLE .SET FALSE ; TRUE FOR FLOPPY SUPPORT
FDMODE .SET FDMODE_SMBWDC ; FDMODE_SMBSMC, FDMODE_SMBWDC
FDMODE .SET FDMODE_RCWDC ; FDMODE_RCSMC, FDMODE_RCWDC
; ;
IDEENABLE .SET TRUE ; TRUE FOR IDE DEVICE SUPPORT (CF MODULE) IDEENABLE .SET TRUE ; TRUE FOR IDE DEVICE SUPPORT (CF MODULE)
IDEMODE .SET IDEMODE_RC ; TYPE OF CF MODULE: IDEMODE_RC, IDEMODE_SMB IDEMODE .SET IDEMODE_RC ; TYPE OF CF MODULE: IDEMODE_RC, IDEMODE_SMB

2
Source/HBIOS/cfg_rc.asm
View File

@ -36,7 +36,7 @@ MDENABLE .EQU TRUE ; TRUE FOR ROM/RAM DISK SUPPORT (ALMOST ALWAYS WANT THIS ENA
MDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF MDENABLE = TRUE) MDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF MDENABLE = TRUE)
; ;
FDENABLE .EQU FALSE ; TRUE FOR FLOPPY SUPPORT FDENABLE .EQU FALSE ; TRUE FOR FLOPPY SUPPORT
FDMODE .EQU FDMODE_SMBWDC ; FDMODE_DIO, FDMODE_ZETA, FDMODE_DIDE, FDMODE_N8, FDMODE_DIO3
FDMODE .EQU FDMODE_RCWDC ; FDMODE_DIO, FDMODE_ZETA, FDMODE_DIDE, FDMODE_N8, FDMODE_DIO3
FDTRACE .EQU 1 ; 0=SILENT, 1=FATAL ERRORS, 2=ALL ERRORS, 3=EVERYTHING (ONLY RELEVANT IF FDENABLE = TRUE) FDTRACE .EQU 1 ; 0=SILENT, 1=FATAL ERRORS, 2=ALL ERRORS, 3=EVERYTHING (ONLY RELEVANT IF FDENABLE = TRUE)
FDMEDIA .EQU FDM144 ; FDM720, FDM144, FDM360, FDM120 (ONLY RELEVANT IF FDENABLE = TRUE) FDMEDIA .EQU FDM144 ; FDM720, FDM144, FDM360, FDM120 (ONLY RELEVANT IF FDENABLE = TRUE)
FDMEDIAALT .EQU FDM720 ; ALTERNATE MEDIA TO TRY, SAME CHOICES AS ABOVE (ONLY RELEVANT IF FDMAUTO = TRUE) FDMEDIAALT .EQU FDM720 ; ALTERNATE MEDIA TO TRY, SAME CHOICES AS ABOVE (ONLY RELEVANT IF FDMAUTO = TRUE)

70
Source/HBIOS/fd.asm
View File

@ -8,7 +8,7 @@
; ;
; PORTS ; PORTS
; ;
#IF ((FDMODE == FDMODE_DIO) | (FDMODE == FDMODE_ZETA) | (FDMODE == FDMODE_DIO3) | (FDMODE == FDMODE_SMBSMC))
#IF ((FDMODE == FDMODE_DIO) | (FDMODE == FDMODE_ZETA) | (FDMODE == FDMODE_DIO3))
FDC_MSR .EQU $36 ; 8272 MAIN STATUS REGISTER FDC_MSR .EQU $36 ; 8272 MAIN STATUS REGISTER
FDC_DATA .EQU $37 ; 8272 DATA PORT FDC_DATA .EQU $37 ; 8272 DATA PORT
FDC_DIR .EQU $38 ; DATA INPUT REGISTER FDC_DIR .EQU $38 ; DATA INPUT REGISTER
@ -41,14 +41,18 @@ FDC_DACK .EQU $90 ; DACK
FDC_TC .EQU $93 ; TERMINAL COUNT (W/ DACK) FDC_TC .EQU $93 ; TERMINAL COUNT (W/ DACK)
FDC_DMA .EQU $3C ; NOT USED BY N8 FDC_DMA .EQU $3C ; NOT USED BY N8
#ENDIF #ENDIF
#IF (FDMODE = FDMODE_SMBWDC)
#IF (FDMODE == FDMODE_RCSMC)
FDC_MSR .EQU $50 ; 8272 MAIN STATUS REGISTER
FDC_DATA .EQU $51 ; 8272 DATA PORT
FDC_DOR .EQU $58 ; DIGITAL OUTPUT REGISTER (LATCH)
#ENDIF
#IF (FDMODE = FDMODE_RCWDC)
FDC_MSR .EQU $50 ; 8272 MAIN STATUS REGISTER FDC_MSR .EQU $50 ; 8272 MAIN STATUS REGISTER
FDC_DATA .EQU $51 ; 8272 DATA PORT FDC_DATA .EQU $51 ; 8272 DATA PORT
FDC_DOR .EQU $58 ; DIGITAL OUTPUT REGISTER FDC_DOR .EQU $58 ; DIGITAL OUTPUT REGISTER
FDC_DCR .EQU $48 ; CONFIGURATION CONTROL REGISTER FDC_DCR .EQU $48 ; CONFIGURATION CONTROL REGISTER
FDC_TC .EQU $58 ; TERMINAL COUNT (W/ DACK) FDC_TC .EQU $58 ; TERMINAL COUNT (W/ DACK)
#ENDIF #ENDIF
; ;
; DISK OPERATIONS ; DISK OPERATIONS
; ;
@ -352,7 +356,7 @@ DOR_INIT .EQU 11010010B ; INITIAL DEFAULT LATCH VALUE
;D1 MOTOR 0 (OFF) 0 (OFF) ;D1 MOTOR 0 (OFF) 0 (OFF)
;D0 TC 0 (OFF) 0 (OFF) ;D0 TC 0 (OFF) 0 (OFF)
; ;
; MOTOR AND DENSITY SELECT ARE INVERTED ON ZETA/DISKIO3
; MOTOR AND DENSITY SELECT ARE INVERTED ON ZETA/DISKIO3 VS. DIO
; ;
#IF ((FDMODE == FDMODE_ZETA) | (FDMODE == FDMODE_DIO3)) #IF ((FDMODE == FDMODE_ZETA) | (FDMODE == FDMODE_DIO3))
DOR_BR250 .EQU 11100110B ; 250KBPS W/ MOTOR ON DOR_BR250 .EQU 11100110B ; 250KBPS W/ MOTOR ON
@ -360,17 +364,34 @@ DOR_BR500 .EQU 10100010B ; 500KBPS W/ MOTOR ON
DOR_INIT .EQU 10100000B ; INITIAL DEFAULT LATCH VALUE DOR_INIT .EQU 10100000B ; INITIAL DEFAULT LATCH VALUE
#ENDIF #ENDIF
; ;
; MOTOR INVERTED, DENSITY SELECT NORMAL FOR SMB SMC
; RCSMC 250KBPS 500KBPS
; ------------ ------- -------
;D7 /FDC_RST 1 (RUN) 1 (RUN)
;D6 DENSEL 0 (DD) 1 (HD)
;D5 P0 (PRECOMP BIT 0) 1 \ 1 \
;D4 P1 (PRECOMP BIT 1) 0 (125NS) 0 (125NS)
;D3 P2 (PRECOMP BIT 2) 0 / 0 /
;D2 MOTORB 0 (OFF) 0 (OFF)
;D1 MOTORA 0 (OFF) 0 (OFF)
;D0 TC 0 (OFF) 0 (OFF)
; ;
#IF (FDMODE == FDMODE_SMBSMC)
DOR_BR250 .EQU 10100110B ; 250KBPS W/ MOTOR ON
DOR_BR500 .EQU 11100010B ; 500KBPS W/ MOTOR ON
; MOTOR INVERTED VS. DIO, DENSITY SELECT LIKE DIO
;
#IF (FDMODE == FDMODE_RCSMC)
; RCSMC HAS NO MINI (BITRATE) LATCH AT D2. INSTEAD, D1 AND
; D2 PROVIDE INDEPENDENT MOTOR CONTROL FOR EACH DRIVE.
; MINI (BITRATE) IS A HARDWARE JUMPER (JP3)
; JP3: 1-2 IS DD (MINI HIGH) AND 2-3 IS HD (MINI LOW)
; JP3 *MUST* BE SET CORRECTLY FOR MEDIA USED
; THE CORRECT MOTOR BIT IS SET IN MOTOR ON, NEITHER SET HERE
DOR_BR250 .EQU 10100000B ; 250KBPS W/ MOTOR OFF!
DOR_BR500 .EQU 11100000B ; 500KBPS W/ MOTOR OFF!
DOR_INIT .EQU 11100000B ; INITIAL DEFAULT LATCH VALUE DOR_INIT .EQU 11100000B ; INITIAL DEFAULT LATCH VALUE
#ENDIF #ENDIF
; ;
; *** DIDE/N8/ZETA V2 *** ; *** DIDE/N8/ZETA V2 ***
; ;
#IF ((FDMODE == FDMODE_DIDE) | (FDMODE == FDMODE_N8) | (FDMODE == FDMODE_ZETA2) | (FDMODE == FDMODE_SMBWDC))
#IF ((FDMODE == FDMODE_DIDE) | (FDMODE == FDMODE_N8) | (FDMODE == FDMODE_ZETA2) | (FDMODE == FDMODE_RCWDC))
DOR_INIT .EQU 00001100B ; SOFT RESET INACTIVE, DMA ENABLED DOR_INIT .EQU 00001100B ; SOFT RESET INACTIVE, DMA ENABLED
DOR_BR250 .EQU DOR_INIT DOR_BR250 .EQU DOR_INIT
DOR_BR500 .EQU DOR_INIT DOR_BR500 .EQU DOR_INIT
@ -1174,7 +1195,7 @@ FC_SETDOR
; ;
; SET FST_DCR ; SET FST_DCR
; ;
#IF ((FDMODE == FDMODE_DIDE) | (FDMODE == FDMODE_N8) | (FDMODE == FDMODE_ZETA2) | (FDMODE == FDMODE_SMBWDC))
#IF ((FDMODE == FDMODE_DIDE) | (FDMODE == FDMODE_N8) | (FDMODE == FDMODE_ZETA2) | (FDMODE == FDMODE_RCWDC))
; ;
FC_SETDCR FC_SETDCR
LD (FST_DCR),A LD (FST_DCR),A
@ -1203,10 +1224,10 @@ FC_RESETFDC:
LD A,(FST_DOR) LD A,(FST_DOR)
PUSH AF PUSH AF
#IF ((FDMODE == FDMODE_ZETA) | (FDMODE == FDMODE_DIO3) | (FDMODE == FDMODE_SMBSMC))
#IF ((FDMODE == FDMODE_ZETA) | (FDMODE == FDMODE_DIO3) | (FDMODE == FDMODE_RCSMC))
RES 7,A RES 7,A
#ENDIF #ENDIF
#IF ((FDMODE == FDMODE_DIDE) | (FDMODE == FDMODE_N8) | (FDMODE == FDMODE_ZETA2) | (FDMODE == FDMODE_SMBWDC))
#IF ((FDMODE == FDMODE_DIDE) | (FDMODE == FDMODE_N8) | (FDMODE == FDMODE_ZETA2) | (FDMODE == FDMODE_RCWDC))
LD A,0 LD A,0
#ENDIF #ENDIF
CALL FC_SETDOR CALL FC_SETDOR
@ -1221,7 +1242,7 @@ FC_RESETFDC:
; PULSE TERMCT TO TERMINATE ANY ACTIVE EXECUTION PHASE ; PULSE TERMCT TO TERMINATE ANY ACTIVE EXECUTION PHASE
; ;
FC_PULSETC: FC_PULSETC:
#IF ((FDMODE == FDMODE_DIDE) | (FDMODE == FDMODE_N8) | (FDMODE == FDMODE_ZETA2) | (FDMODE == FDMODE_SMBWDC))
#IF ((FDMODE == FDMODE_DIDE) | (FDMODE == FDMODE_N8) | (FDMODE == FDMODE_ZETA2) | (FDMODE == FDMODE_RCWDC))
IN A,(FDC_TC) IN A,(FDC_TC)
#ELSE #ELSE
LD A,(FST_DOR) LD A,(FST_DOR)
@ -1243,7 +1264,7 @@ FC_MOTORON:
LD DE,FDSTR_MOTON LD DE,FDSTR_MOTON
CALL WRITESTR CALL WRITESTR
#ENDIF #ENDIF
#IF ((FDMODE == FDMODE_DIO) | (FDMODE == FDMODE_ZETA) | (FDMODE == FDMODE_DIO3) | (FDMODE == FDMODE_SMBSMC))
#IF ((FDMODE == FDMODE_DIO) | (FDMODE == FDMODE_ZETA) | (FDMODE == FDMODE_DIO3))
LD A,(FST_DOR) LD A,(FST_DOR)
PUSH AF PUSH AF
@ -1251,13 +1272,30 @@ FC_MOTORON:
CALL FC_SETDOR ; AND IMPLEMENT IT CALL FC_SETDOR ; AND IMPLEMENT IT
POP AF POP AF
#IF ((FDMODE == FDMODE_ZETA) | (FDMODE == FDMODE_DIO3) | (FDMODE == FDMODE_SMBSMC))
#IF ((FDMODE == FDMODE_ZETA) | (FDMODE == FDMODE_DIO3))
XOR 00000010B ; MOTOR BIT INVERTED ON ZETA XOR 00000010B ; MOTOR BIT INVERTED ON ZETA
#ENDIF #ENDIF
BIT 1,A ; SET FLAGS SET BASED ON CURRENT MOTOR BIT BIT 1,A ; SET FLAGS SET BASED ON CURRENT MOTOR BIT
RET Z ; MOTOR WAS PREVIOUSLY ON, WE ARE DONE RET Z ; MOTOR WAS PREVIOUSLY ON, WE ARE DONE
#ENDIF #ENDIF
#IF ((FDMODE == FDMODE_DIDE) | (FDMODE == FDMODE_N8) | (FDMODE == FDMODE_ZETA2) | (FDMODE == FDMODE_SMBWDC))
#IF (FDMODE == FDMODE_RCSMC)
LD A,(FCD_DS) ; GET DRIVE SELECTED (0 OR 1)
LD C,%00000010 ; MASK FOR MOTORA ON (BIT 1 IS MOTORA)
OR A ; SET FLAGS BASED ON FCD_DS
JR Z,FC_MOTORON1 ; IF FCD_DS == 0, MOTORA IS CORRECT
LD C,%00000100 ; ELSE MASK FOR MOTORB ON (BIT 2 IS MOTORB)
FC_MOTORON1:
LD A,(FST_DOR) ; GET CURRENT DOR VALUE
PUSH AF ; SAVE IT
LD A,(FCD_DOR) ; GET NEW DOR VALUE (W/O MOTOR BITS SET)
OR C ; ADD THE MOTOR BITS
CALL FC_SETDOR ; AND IMPLEMENT NEW VALUE
POP AF ; RECOVER PREVIOUS DOR VALUE
AND %00000110 ; ISOLATE PREVIOUS MOTOR BITS
CP C ; COMPARE TO NEW MOTOR BITS
RET Z ; SKIP DELAY, MOTOR WAS ALREADY ON
#ENDIF
#IF ((FDMODE == FDMODE_DIDE) | (FDMODE == FDMODE_N8) | (FDMODE == FDMODE_ZETA2) | (FDMODE == FDMODE_RCWDC))
; SETUP DCR FOR DIDE HARDWARE ; SETUP DCR FOR DIDE HARDWARE
LD A,(FCD_DCR) ; GET NEW DCR VALUE LD A,(FCD_DCR) ; GET NEW DCR VALUE
CALL FC_SETDCR ; AND IMPLEMENT IT CALL FC_SETDCR ; AND IMPLEMENT IT

6
Source/HBIOS/hbios.asm
View File

@ -496,10 +496,11 @@ HBX_INT: ; COMMON INTERRUPT ROUTING CODE
LD (HBX_INT_SP),SP ; SAVE ORIGINAL STACK FRAME LD (HBX_INT_SP),SP ; SAVE ORIGINAL STACK FRAME
LD SP,HBX_STACK ; USE STACK FRAME IN HI MEM LD SP,HBX_STACK ; USE STACK FRAME IN HI MEM
; SAVE STATE (HL SAVED PREVIOUSLY)
; SAVE STATE (HL SAVED PREVIOUSLY ON ORIGINAL STACK FRAME)
PUSH AF ; SAVE AF PUSH AF ; SAVE AF
PUSH BC ; SAVE BC PUSH BC ; SAVE BC
PUSH DE ; SAVE DE PUSH DE ; SAVE DE
PUSH IY ; SAVE IY
LD A,BID_BIOS ; HBIOS BANK LD A,BID_BIOS ; HBIOS BANK
CALL HBX_BNKSEL_INT ; SELECT IT CALL HBX_BNKSEL_INT ; SELECT IT
@ -510,6 +511,7 @@ HBX_INT: ; COMMON INTERRUPT ROUTING CODE
CALL HBX_BNKSEL ; SELECT IT CALL HBX_BNKSEL ; SELECT IT
; RESTORE STATE ; RESTORE STATE
POP IY ; RESTORE IY
POP DE ; RESTORE DE POP DE ; RESTORE DE
POP BC ; RESTORE BC POP BC ; RESTORE BC
POP AF ; RESTORE AF POP AF ; RESTORE AF
@ -2556,7 +2558,7 @@ PS_SERIAL:
PRTS("Serial $") PRTS("Serial $")
LD A,C ; MOVE UNIT NUM TO A LD A,C ; MOVE UNIT NUM TO A
CALL PRTDECB ; PRINT IT, ASSUME SINGLE DIGIT CALL PRTDECB ; PRINT IT, ASSUME SINGLE DIGIT
PRTS(" $") ; PAD TO NEXT COLUMN
PRTS(" $") ; PAD TO NEXT COLUMN
; ;
; DEVICE COLUMN ; DEVICE COLUMN
LD B,BF_CIODEVICE ; FUNC=GET DEVICE INFO, UNIT NUM STILL IN C LD B,BF_CIODEVICE ; FUNC=GET DEVICE INFO, UNIT NUM STILL IN C

14
Source/HBIOS/std.asm
View File

@ -79,8 +79,8 @@ DSRTCMODE_MFPIC .EQU 2 ; MF/PIC VARIANT
; SIO MODE SELECTIONS ; SIO MODE SELECTIONS
; ;
SIOMODE_NONE .EQU 0 SIOMODE_NONE .EQU 0
SIOMODE_RC .EQU 1 ; RC2014 SIO MODULE FROM SPENCER
SIOMODE_SMB .EQU 2 ; RC2014 SIO MODULE BY SCOTT BAKER
SIOMODE_RC .EQU 1 ; RC2014 SIO MODULE (SPENCER OWEN)
SIOMODE_SMB .EQU 2 ; RC2014 SIO MODULE (SCOTT BAKER)
; ;
; FD MODE SELECTIONS ; FD MODE SELECTIONS
; ;
@ -91,8 +91,8 @@ FDMODE_ZETA2 .EQU 3 ; ZETA V2
FDMODE_DIDE .EQU 4 ; DUAL IDE FDMODE_DIDE .EQU 4 ; DUAL IDE
FDMODE_N8 .EQU 5 ; N8 FDMODE_N8 .EQU 5 ; N8
FDMODE_DIO3 .EQU 6 ; DISKIO V3 FDMODE_DIO3 .EQU 6 ; DISKIO V3
FDMODE_SMBSMC .EQU 7 ; RC2014 SMB SMC9266
FDMODE_SMBWDC .EQU 8 ; RC2014 SMB WD37C65
FDMODE_RCSMC .EQU 7 ; RC2014 SMC 9266 @ $40 (SCOTT BAKER)
FDMODE_RCWDC .EQU 8 ; RC2014 WDC 37C65 @ $40 (SCOTT BAKER)
; ;
; IDE MODE SELECTIONS ; IDE MODE SELECTIONS
@ -101,8 +101,8 @@ IDEMODE_NONE .EQU 0
IDEMODE_DIO .EQU 1 ; DISKIO V1 IDEMODE_DIO .EQU 1 ; DISKIO V1
IDEMODE_DIDE .EQU 2 ; DUAL IDE IDEMODE_DIDE .EQU 2 ; DUAL IDE
IDEMODE_MK4 .EQU 3 ; MARK IV ONBOARD IDE (8 BIT) IDEMODE_MK4 .EQU 3 ; MARK IV ONBOARD IDE (8 BIT)
IDEMODE_RC .EQU 4 ; RC2014 CF BOARD (8 BIT)
IDEMODE_SMB .EQU 5 ; RC2014 IDE SMB $E0 IO BASE (8 BIT)
IDEMODE_RC .EQU 4 ; RC2014 CF MODULE (8 BIT) @ $10 (SPENCER OWEN)
IDEMODE_SMB .EQU 5 ; RC2014 IDE MODULE (8 BIT) @ $E0 (SCOTT BAKER)
; ;
; PPIDE MODE SELECTIONS ; PPIDE MODE SELECTIONS
; ;
@ -111,7 +111,7 @@ PPIDEMODE_SBC .EQU 1 ; STANDARD SBC PARALLEL PORT
PPIDEMODE_DIO3 .EQU 2 ; DISKIO V3 PARALLEL PORT PPIDEMODE_DIO3 .EQU 2 ; DISKIO V3 PARALLEL PORT
PPIDEMODE_MFP .EQU 3 ; MULTIFUNCTION / PIC PPIDEMODE_MFP .EQU 3 ; MULTIFUNCTION / PIC
PPIDEMODE_N8 .EQU 4 ; MULTIFUNCTION / PIC PPIDEMODE_N8 .EQU 4 ; MULTIFUNCTION / PIC
PPIDEMODE_RC .EQU 5 ; RC2014 PPIDE STANDARD $20 IO BASE
PPIDEMODE_RC .EQU 5 ; RC2014 PPIDE MODULE @ $20 (ED BRINDLEY)
; ;
; SD MODE SELECTIONS ; SD MODE SELECTIONS
; ;

6
Source/HBIOS/ver.inc
View File

@ -1,5 +1,5 @@
#DEFINE RMJ 2 #DEFINE RMJ 2
#DEFINE RMN 8
#DEFINE RUP 6
#DEFINE RMN 9
#DEFINE RUP 0
#DEFINE RTP 0 #DEFINE RTP 0
#DEFINE BIOSVER "2.8.6"
#DEFINE BIOSVER "2.9.0-pre.0"

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