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@ -243,7 +243,7 @@ EXTRA3: |
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; |
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BIOID DB 0 ; BIOS ID, 1=HBIOS, 2=UBIOS |
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CPUSPD DB 10 ; CPU speed in MHz |
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RCVSCL DW 2800 ; RECV loop timeout scalar |
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RCVSCL DW 6600 ; RECV loop timeout scalar |
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; |
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RBC DB "RBC, 28-Aug-2019$" |
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; |
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@ -302,6 +302,9 @@ U_JPTBL: |
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; UART initialization |
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; |
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U_INIT: |
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LD HL,13000 ; Receive loop timeout scalar |
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LD (RCVSCL),HL ; ... for UART RCVRDY timing |
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; |
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LD HL,U_JPTBL |
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LD DE,U_LBL |
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JP MINIT_RET |
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@ -429,6 +432,9 @@ A_JPTBL: |
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; ASCI initialization |
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; |
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A_INIT: |
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LD HL,7500 ; Receive loop timeout scalar |
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LD (RCVSCL),HL ; ... for ASCI RCVRDY timing |
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; |
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; Test for location of Z180 internal registers |
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; and use appropriate I/O address. |
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LD B,0 ; set MSB for 16 bit I/O |
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@ -601,6 +607,9 @@ S_JPTBL: |
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; SIO initialization |
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; |
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S_INIT: |
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LD HL,12000 ; Receive loop timeout scalar |
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LD (RCVSCL),HL ; ... for UART RCVRDY timing |
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; |
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; Suppress interrupts |
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LD A,01H ; WR1 |
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OUT (S_CTLP),A ; Select WR1 |
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@ -841,6 +850,9 @@ UF_JPTBL: |
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; USB-FIFO initialization |
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; |
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UF_INIT: |
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LD HL,12000 ; Receive loop timeout scalar |
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LD (RCVSCL),HL ; ... for UART RCVRDY timing |
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; |
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LD HL,UF_JPTBL |
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LD DE,UF_LBL |
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JP MINIT_RET |
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