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Pegasys-RomWBW
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Reintegrate wbw -> trunk

patch
wayne 13 years ago
parent
f5c27ce732
commit
82351f2c5f
52 changed files with 657 additions and 496 deletions
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  1. 24
      Apps/Source/Build.cmd
  2. 6
      Apps/Source/applvers.h
  3. 8
      Apps/Source/applvers.lib
  4. 2
      Apps/Source/cnfgdata.h
  5. 1
      Apps/Source/cpmbdos.h
  6. 13
      Apps/Source/cpmname.c
  7. 2
      Apps/Source/infolist.h
  8. 3
      Apps/Source/map.c
  9. 2
      Apps/Source/memory.asm
  10. 13
      Apps/Source/meta.c
  11. 13
      Apps/Source/multifmt.c
  12. 1
      Apps/Source/setlabel.asm
  13. 287
      Apps/Source/termtype.c
  14. 74
      Apps/Source/view.c
  15. 2
      Doc/ChangeLog.txt
  16. 4
      ReadMe.txt
  17. BIN
      RomDsk/cfg_n8vem_mfp/1200.COM
  18. BIN
      RomDsk/cfg_n8vem_mfp/38400.COM
  19. BIN
      RomDsk/cfg_n8vem_mfp/9600.COM
  20. BIN
      RomDsk/cfg_n8vem_mfp/FLASHZ.COM
  21. BIN
      RomDsk/cfg_n8vem_mfp/LDTIM.COM
  22. BIN
      RomDsk/cfg_n8vem_mfp/RTC.COM
  23. BIN
      RomDsk/cfg_n8vem_mfp/T5.COM
  24. BIN
      RomDsk/cfg_n8vem_mfp/VT3.COM
  25. BIN
      RomDsk/cfg_n8vem_mfp/XM.COM
  26. BIN
      RomDsk/cfg_n8vem_mfp/XM5.COM
  27. 32
      RomList.txt
  28. 2
      Source/bootapp.asm
  29. 2
      Source/bootrom.asm
  30. 18
      Source/cbios.asm
  31. 2
      Source/config_n8_2312.asm
  32. 2
      Source/config_n8_2511.asm
  33. 4
      Source/config_n8vem_ci.asm
  34. 2
      Source/config_n8vem_cvdu.asm
  35. 2
      Source/config_n8vem_dide.asm
  36. 2
      Source/config_n8vem_diskio.asm
  37. 2
      Source/config_n8vem_diskio3.asm
  38. 2
      Source/config_n8vem_dsd.asm
  39. 102
      Source/config_n8vem_mfp.asm
  40. 2
      Source/config_n8vem_ppide.asm
  41. 2
      Source/config_n8vem_ppisd.asm
  42. 2
      Source/config_n8vem_propio.asm
  43. 2
      Source/config_n8vem_simh.asm
  44. 2
      Source/config_n8vem_std.asm
  45. 2
      Source/config_n8vem_vdu.asm
  46. 2
      Source/config_zeta_ppp.asm
  47. 2
      Source/config_zeta_std.asm
  48. 15
      Source/ppide.asm
  49. 1
      Source/std.asm
  50. 2
      Source/syscfg.asm
  51. 486
      Source/uart.asm
  52. 4
      Source/ver.inc

24
Apps/Source/Build.cmd
View File

@ -15,13 +15,15 @@ echo Building DWG.REL...
echo.
set TGT=dwg.rel
if exist %TGT% del %TGT%
zx rmac printers
zx rmac memory
zx rmac banner
zx rmac terminal
zx rmac identity
zx rmac hbios
zx lib %TGT%=printers,memory,banner,terminal,identity,hbios
zx rmac printers.asm -$PN
zx rmac memory.asm -$PN
zx rmac banner.asm -$PN
zx rmac terminal.asm -$PN
zx rmac identity.asm -$PN
zx rmac hbios.asm -$PN
ZX rmac labelib.asm -$PN
zx rmac metadata.asm -$PN
zx lib %TGT%=printers,memory,banner,terminal,identity,hbios,labelib,metadata
if not exist %TGT% echo *** Failed to build %TGT% *** && pause
echo.
@ -52,7 +54,7 @@ echo Building ACCESS.COM...
echo.
set TGT=access.com
if exist %TGT% del %TGT%
zx rmac access
zx rmac access.asm -$PN
zx link access,dwg
if not exist %TGT% echo *** Failed to build %TGT% *** && pause
@ -71,7 +73,7 @@ echo Building FINDFILE.COM...
echo.
set TGT=findfile.com
if exist %TGT% del %TGT%
zx rmac findfile
zx rmac findfile.asm -$PN
zx link findfile,dwg
if not exist %TGT% echo *** Failed to build %TGT% *** && pause
@ -110,7 +112,7 @@ echo Building REM.COM...
echo.
set TGT=rem.com
if exist %TGT% del %TGT%
zx rmac rem
zx rmac rem.asm -$PN
zx link rem
if not exist %TGT% echo *** Failed to build %TGT% *** && pause
@ -119,7 +121,7 @@ echo Building SETLABEL.COM...
echo.
set TGT=setlabel.com
if exist %TGT% del %TGT%
zx rmac setlabel
zx rmac setlabel.asm -$PN
zx link setlabel,dwg
if not exist %TGT% echo *** Failed to build %TGT% *** && pause

6
Apps/Source/applvers.h
View File

@ -5,10 +5,10 @@
#define A_RMJ 2
#define A_RMN 5
#define A_RUP 0
#define A_RTP 12
#define A_RTP 13
#define A_MONTH 5
#define A_DAY 24
#define A_MONTH 6
#define A_DAY 7
#define A_YEAR 2013
#define A_YR 13

8
Apps/Source/applvers.lib
View File

@ -3,14 +3,14 @@
A$RMJ equ 2
A$RMN equ 5
A$RUP equ 0
A$RTP equ 12
A$RTP equ 13
A$MONTH equ 5
A$DAY equ 24
A$MONTH equ 6
A$DAY equ 7
A$YEAR equ 2013
date macro
dat db ' 5/24/2013$'
dat db ' 6/7/2013$'
endm
serial macro

2
Apps/Source/cnfgdata.h
View File

@ -94,7 +94,7 @@ struct CNFGDATA {
unsigned int idecapacity;
unsigned char ppideenable;
unsigned char ppidemode;
unsigned char ppideiob;
unsigned char ppidetrace;
unsigned char ppide8bit;
unsigned int ppidecapacity;

1
Apps/Source/cpmbdos.h
View File

@ -34,6 +34,7 @@
#define RESETDRIVE 37
#define WRRANDFILL 38
#define BDOSDEFDR 0 /* BDOS Default (current) Drive Number */
#define BDOSDRA 1
#define BDOSDRB 2
#define BDOSDRC 3

13
Apps/Source/cpmname.c
View File

@ -12,9 +12,11 @@
#define GETSYSCFG 0xF000 /* HBIOS function for Get System Configuration */
char None[] = "*None*";
char Unk[] = "*Unknown*";
char * PltName[] = {None, "N8VEM Z80", "ZETA Z80", "N8 Z180"};
char * CIOName[] = {"UART", "ASCI", "VDU", "CVDU", "UPD7220",
"N8V", "PRPCON", "PPPCON", "CRT", "BAT", "NUL"};
"N8V", "PRPCON", "PPPCON", Unk, Unk, Unk, Unk, Unk,
"CRT", "BAT", "NUL"};
char * DIOName[] = {"MD", "FD", "IDE", "ATAPI", "PPIDE",
"SD", "PRPSD", "PPPSD", "HDSK"};
char * VDAName[] = {None, "VDU", "CVDU", "UPD7220", "N8V"};
@ -123,8 +125,9 @@ prtcfg1(pSysCfg)
pager();
pager();
printf("Console: Default=%s, Alternate=%s, Init Baudrate=%d0",
CIOName[pCfg->defcon], CIOName[pCfg->altcon],
printf("Console: Default=%s:%d, Alternate=%s:%d, Init Baudrate=%d0",
CIOName[(pCfg->defcon) >> 4], pCfg->defcon & 0xF,
CIOName[(pCfg->altcon) >> 4], pCfg->altcon & 0xF,
pCfg->conbaud);
pager();
printf ("Default Video Display: %s, Default Emulation: %s",
@ -208,8 +211,8 @@ prtcfg2(pSysCfg)
fmtenable(pCfg->ideenable), IDEModeName[pCfg->idemode],
pCfg->idetrace, fmtbool(pCfg->ide8bit), pCfg->idecapacity);
pager();
printf("PPIDE %s, Mode=%s, TraceLevel=%d, 8bit=%s, Slow=%s, Size=%dMB",
fmtenable(pCfg->ppideenable), IDEModeName[pCfg->ppidemode],
printf("PPIDE %s, IOBase=0x%s, TraceLevel=%d, 8bit=%s, Slow=%s, Size=%dMB",
fmtenable(pCfg->ppideenable), fmthexbyte(pCfg->ppideiob, buf),
pCfg->ppidetrace, fmtbool(pCfg->ppide8bit),
fmtbool(pCfg->ppideslow), pCfg->ppidecapacity);
pager();

2
Apps/Source/infolist.h
View File

@ -8,7 +8,7 @@ struct INFOLIST {
void * dpbmap;
void * dphmap;
void * ciomap;
} * pINFOLIST;
};
/********************/
/* eof - infolist.h */

3
Apps/Source/map.c
View File

@ -238,8 +238,7 @@ int main(argc,argv)
char szDrive[32];
char szLuNum[32];
char szWP[2];
struct INFOLIST * pINFOLIST;
if(argc == 3) {

2
Apps/Source/memory.asm
View File

@ -1,5 +1,5 @@
; memory.asm 2/1/2012 dwg - memory library implementation
; maclib z80
maclib z80
;memcpy macro h=src,d==dst,bc=size
public x$memcpy

13
Apps/Source/meta.c
View File

@ -1,6 +1,5 @@
/* meta.c 6/7/2012 dwg - view and edit the metadata */
#include "stdio.h"
#include "portab.h"
#include "globals.h"
@ -47,10 +46,10 @@ display()
rdsector(drive,0,11,&metadata);
crtlc(METALINE+0,METACOL);
printf("metadata.signature = 0x%04x",metadata.signature);
printf("metadata.signature = 0x%x",metadata.signature);
crtlc(METALINE+1,METACOL);
printf("metadata.platform = 0x%02x",metadata.platform);
printf("metadata.platform = 0x%x",metadata.platform);
crtlc(METALINE+2,METACOL);
printf("metadata.formatter = \"");
@ -93,16 +92,16 @@ display()
}
printf("\"");
crtlc(METALINE+9,METACOL);
printf("metadata.infloc = 0x%04x",metadata.infloc);
printf("metadata.infloc = 0x%x",metadata.infloc);
crtlc(METALINE+10,METACOL);
printf("metadata.cpmloc = 0x%04x",metadata.cpmloc);
printf("metadata.cpmloc = 0x%x",metadata.cpmloc);
crtlc(METALINE+11,METACOL);
printf("metadata.cpmend = 0x%04x",metadata.cpmend);
printf("metadata.cpmend = 0x%x",metadata.cpmend);
crtlc(METALINE+12,METACOL);
printf("metadata.cpment = 0x%04x",metadata.cpment);
printf("metadata.cpment = 0x%x",metadata.cpment);
}

13
Apps/Source/multifmt.c
View File

@ -219,7 +219,7 @@ clrdir(line,col)
if(-1 != line) {
crtlc(line,col-1);
printf("%3d",sectors-sector);
printf("%d",sectors-sector);
}
wrsector(gDrvNum,pDPB->off,sector,e5buffer,1);
@ -283,7 +283,7 @@ physfmt(lu)
/* LU is not protected or override is enabled */
if(0==gTT) {
printf("Formatting LU# %3d%c",lu,0x0d);
printf("Formatting LU# %d%c",lu,0x0d);
clrmeta(lu,-1,-1);
clrdir(-1,-1);
} else {
@ -291,14 +291,14 @@ physfmt(lu)
line = lu / 16;
crtlc(26-16-4+line,0);
printf("%3d...",lu & 0xf0);
printf("%d...",lu & 0xf0);
col = lu & 15;
clrmeta(lu,24-16-2+line,((80-64)/2)+(col*4)+1);
clrdir( 24-16-2+line,((80-64)/2)+(col*4)+1);
crtlc(24-16-2+line,((80-64)/2)+(col*4)+1);
printf("OK");
crtlc(24-16-2+line,((80-64)/2)+(col*4));
printf(" OK");
}
return TRUE;
@ -317,7 +317,7 @@ lformat()
if(0 != gTT) {
for(index=0;index<16;index++) {
crtlc(24-16-2-2,((80-64)/2)+(index*4));
printf("+%2d",index);
printf("+%d",index);
}
for(index=0;index<16;index++) {
crtlc(24-16-2-1,((80-64)/2)+(index*4));
@ -438,6 +438,7 @@ main(argc,argv)
char *argv[];
{
int retcode;
struct INFOLIST * pINFOLIST;
hregbc = GETSYSCFG; /* function = Get System Config */
hregde = HIGHSEG; /* addr of dest (must be high) */

1
Apps/Source/setlabel.asm
View File

@ -64,7 +64,6 @@ around$bandata:
printf 'Sorry, you can only label drives with reserved tracks'
jmp main$exit
off$ok:
lda drive$num ; using the default drive number
mov c,a ; (presented in the C register)
call x$label ; call the actual code in labelib.asm

287
Apps/Source/termtype.c
View File

@ -2,292 +2,21 @@
#include "stdio.h"
#include "applvers.h"
/* declarations for HBIOS access */
extern char hrega;
extern unsigned int hregbc;
extern unsigned int hregde;
extern unsigned int hreghl;
extern diagnose();
/* declaration dir BIOS and BDOS and low level calls */
extern char xrega;
extern unsigned int xregbc;
extern unsigned int xregde;
extern unsigned int xreghl;
extern asmif(); /* asmif(0x0E6**,bc,de,hl); */
#include "infolist.h"
#include "cnfgdata.h"
#include "syscfg.h"
#include "diagnose.h"
#include "asmiface.h"
#include "cpmbdos.h"
#include "cpmbios.h"
#define BDOS 5 /* memory address of BDOS invocation */
#define PRIFCB 0x5C /* memory address of primary FCB */
#define SECFCB 0x6C /* memory address of secondary FCB */
#define DEFBUF 0x80 /* memory address of default buffer */
#define HIGHSEG 0x0C000 /* memory address of system config */
#define GETSYSCFG 0x0F000 /* HBIOS function for Get System Configuration */
#define PUTSYSCFG 0x0F100 /* HBIOS function for Put System Configuration */
#define TERMCPM 0 /* BDOS function for System Reset */
#define CONIN 1 /* BDOS function for Console Input */
#define CWRITE 2 /* BDOS function for Console Output */
#define DIRCONIO 6 /* BDOS function for Direct Console I/O */
#define PRINTSTR 9 /* BDOS function for Print String */
#define RDCONBUF 10 /* BDOS function for Buffered Console Read */
#define GETCONST 11 /* BDOS function for Get Console Status */
#define RETVERNUM 12 /* BDOS function for Return Version Number */
#define RESDISKSYS 13 /* BDOS function for Reset Disk System */
#define SELECTDISK 14 /* BDOS function for Select Disk */
#define FOPEN 15 /* BDOS function for File Open */
#define FCLOSE 16 /* BDOS function for File Close */
#define SEARCHFIRST 17 /* BDOS function for Search First */
#define SEARCHNEXT 18 /* BDOS function for Search Next */
#define FDELETE 19 /* BDOS function for File Delete */
#define FREADSEQ 20 /* BDOS function for File Read Sequential */
#define FWRITESEQ 21 /* BDOS function for File Write Sequential */
#define FMAKEFILE 22 /* BDOS function for File Make */
#define FRENAME 23 /* BDOS function for File Rename */
#define RETLOGINVEC 24 /* BDOS function for Return Login Vector */
#define RETCURRDISK 25 /* BDOS function for Return Current Disk */
#define SETDMAADDR 26 /* BDOS function for Set DMA Address */
#define GETALLOCVEC 27 /* BDOS function for Get Allocation Vector */
#define WRPROTDISK 28 /* BDOS function for Write Protect Disk */
#define GETROVECTOR 29 /* BDOS function for Get Read Only Vector */
#define FSETATTRIB 30 /* BDOS function for File Set Attribute */
#define GETDPBADDR 31 /* BDOS function for Get DPB Address */
#define SETGETUSER 32 /* BDOS function for Set & Get User Number */
#define FREADRANDOM 33 /* BDOS function for File Read Random */
#define FWRITERAND 34 /* BDOS function for File Write Random */
#define FCOMPSIZE 35 /* BDOS function for File Compare Size */
#define SETRANDREC 36 /* BDOS function for Set Random Record # */
#define RESETDRIVE 37 /* BDOS function for Reset Drive */
#define WRRANDFILL 38 /* BDOS function for Write Random w/ Fill */
#define BDOSDEFDR 0 /* BDOS Default (current) Drive Number */
#define BDOSDRA 1 /* BDOS Drive A: number */
#define BDOSDRB 2 /* BDOS Drive B: number */
#define BDOSDRC 3 /* BDOS Drive C: number */
#define BDOSDRD 4 /* BDOS Drive D: number */
#define BDOSDRE 5 /* BDOS Drive E: number */
#define BDOSDRF 6 /* BDOS Drive F: number */
#define BDOSDRG 7 /* BDOS Drive G: number */
#define BDOSDRH 8 /* BDOS Drive H: number */
#define BIOSDRA 0 /* BIOS Drive A: number */
#define BIOSDRB 1 /* BIOS Drive B: number */
#define BIOSDRC 2 /* BIOS Drive C: number */
#define BIOSDRD 3 /* BIOS Drive D: number */
#define BIOSDRE 4 /* BIOS Drive E: number */
#define BIOSDRF 5 /* BIOS Drive F: number */
#define BIOSDRG 6 /* BIOS Drive G: number */
#define BIOSDRH 7 /* BIOS Drive H: number */
struct FCB {
char drive; /* BDOS Drive Code */
char filename[8]; /* space padded file name */
char filetype[3]; /* space padded file extension */
char filler[24]; /* remainder of FCB */
};
struct FCB * pPriFcb = PRIFCB; /* pointer to Primary FCB structure */
struct FCB * pSecFcb = SECFCB; /* pointer to secondary FCB structure */
struct {
char length; /* length of commad tail */
char tail[127]; /* command tail */
} * pDefBuf = DEFBUF;
#define CURDRV 0x00004
#define BIOSAD 0x0e600 /* base address of BIOS jumps */
/* addresses of BIOS jumps */
#define pBOOT 0x0E600
#define pWBOOT 0x0E603
#define pCONST 0x0E606
#define pCONIN 0x0E609
#define pCONOUT 0x0E60C
#define pLIST 0x0E60F
#define pPUNCH 0x0E612
#define pREADER 0x0E615
#define pHOME 0x0E618
#define pSELDSK 0x0E61B
#define pSETTRK 0x0E61E
#define pSETSEC 0x0E621
#define pSETDMA 0x0E624
#define pREAD 0x0E627
#define pWRITE 0x0E62A
#define pLISTST 0x0E62D
#define pSECTRN 0x0E630
#define pBNKSEL 0x0E633
#define pGETLU 0x0E636
#define pSETLU 0x0E639
#define pGETINFO 0x0E63C
struct JMP {
unsigned char opcode; /* JMP opcode */
unsigned int address; /* JMP address */
};
struct BIOS {
struct JMP boot;
struct JMP wboot;
struct JMP const;
struct JMP conin;
struct JMP conout;
struct JMP list;
struct JMP punch;
struct JMP reader;
struct JMP home;
struct JMP seldsk;
struct JMP settrk;
struct JMP setsec;
struct JMP setdma;
struct JMP read;
struct JMP write;
struct JMP listst;
struct JMP sectrn;
struct JMP bnksel;
struct JMP getlu;
struct JMP setlu;
struct JMP getinfo;
struct JMP rsvd1;
struct JMP rsvd2;
struct JMP rsvd3;
struct JMP rsvd4;
char rmj;
char rmn;
char rup;
char rtp;
} * pBIOS = 0xe600;
/* pointer based Disk Parameter Block structure */
struct DPB {
unsigned int spt;
unsigned char bsh;
unsigned char blm;
unsigned char exm;
unsigned int dsm;
unsigned int drm;
unsigned char al0;
unsigned int cks;
unsigned int off;
} * pDPB;
/* pointer based Disk Parameter Header structure */
struct DPH {
unsigned int xlt;
unsigned int rv1;
unsigned int rv2;
unsigned int rv3;
unsigned int dbf;
struct DPB * pDpb;
unsigned int csv;
unsigned int alv;
unsigned char sigl;
unsigned char sigu;
unsigned int current;
unsigned int number;
} * pDPH;
/* pointer based Information List structure */
struct INFOLIST {
int version;
void * banptr;
void * varloc;
void * tstloc;
void * dpbmap;
void * dphmap;
void * ciomap;
} * pINFOLIST;
/* pointer based Configuration Data structure */
struct CNFGDATA {
unsigned char rmj;
unsigned char rmn;
unsigned char rup;
unsigned char rtp;
unsigned char diskboot;
unsigned char devunit;
unsigned int bootlu;
unsigned char hour;
unsigned char minute;
unsigned char second;
unsigned char month;
unsigned char day;
unsigned char year;
unsigned char freq;
unsigned char platform;
unsigned char dioplat;
unsigned char vdumode;
unsigned int romsize;
unsigned int ramsize;
unsigned char clrramdk;
unsigned char dskyenable;
unsigned char uartenable;
unsigned char vduenable;
unsigned char fdenable;
unsigned char fdtrace;
unsigned char fdmedia;
unsigned char fdmediaalt;
unsigned char fdmauto;
unsigned char ideenable;
unsigned char idetrace;
unsigned char ide8bit;
unsigned int idecapacity;
unsigned char ppideenable;
unsigned char ppidetrace;
unsigned char ppide8bit;
unsigned int ppidecapacity;
unsigned char ppideslow;
unsigned char boottype;
unsigned char boottimeout;
unsigned char bootdefault;
unsigned int baudrate;
unsigned char ckdiv;
unsigned char memwait;
unsigned char iowait;
unsigned char cntlb0;
unsigned char cntlb1;
unsigned char sdenable;
unsigned char sdtrace;
unsigned int sdcapacity;
unsigned char sdcsio;
unsigned char sdcsiofast;
unsigned char defiobyte;
unsigned char termtype;
unsigned int revision;
unsigned char prpsdenable;
unsigned char prpsdtrace;
unsigned int prpsdcapacity;
unsigned char prpconenable;
unsigned int biossize;
unsigned char pppenable;
unsigned char pppsdenable;
unsigned char pppsdtrace;
unsigned int pppsdcapacity;
unsigned char pppconenable;
unsigned char prpenable;
} * pCNFGDATA;
struct JMP_TAG {
unsigned char opcode;
unsigned int address;
};
/* pointer based System Configuration structure */
struct SYSCFG {
struct JMP_TAG jmp;
void * cnfloc;
void * tstloc;
void * varloc;
struct CNFGDATA cnfgdata;
char filler[256-3-2-2-2-sizeof(struct CNFGDATA)];
} * pSYSCFG = HIGHSEG;
struct SYSCFG * pSYSCFG = HIGHSEG;
#define TTY 0
#define ANSI 1

74
Apps/Source/view.c
View File

@ -23,28 +23,6 @@
#define GETSYSCFG 0x0F000 /* HBIOS function for Get System Configuration */
/*
#include "cpmbind.h"
#include "cbioshdr.h"
#include "std.h"
#include "infolist.h"
#include "dphdpb.h"
#include "dphmap.h"
#include "metadata.h"
#include "setlunum.h"
#include "applvers.h"
#include "cpmbdos.h"
#include "ctermcap.h"
#include "diagnose.h"
*/
#define BDOS 5 /* memory address of BDOS invocation */
#define HIGHSEG 0x0C000 /* memory address of system config */
#define GETSYSCFG 0x0F000 /* HBIOS function for Get System Configuration */
/* Drive List Geometry */
#define COL1 0
#define COL2 (80/4)
@ -67,39 +45,31 @@
struct SYSCFG * pSYSCFG = HIGHSEG;
/*
struct DPH * pDPH;
struct DPB * pDPB;
*/
/* int drive; */
dispdpb(line,column,pDPB)
int line;
int column;
struct DPB * pDPB;
{
crtlc(line+0,column);
printf("[%04x] spt =%04x",&pDPB->spt,pDPB->spt);
printf("[%x] spt =%x",&pDPB->spt,pDPB->spt);
crtlc(line+1,column);
printf("[%04x] bsh =%02x",&pDPB->bsh,pDPB->bsh);
printf("[%x] bsh =%x",&pDPB->bsh,pDPB->bsh);
crtlc(line+2,column);
printf("[%04x] blm =%02x",&pDPB->blm,pDPB->blm);
printf("[%x] blm =%x",&pDPB->blm,pDPB->blm);
crtlc(line+3,column);
printf("[%04x] exm =%02x",&pDPB->exm,pDPB->exm);
printf("[%x] exm =%x",&pDPB->exm,pDPB->exm);
crtlc(line+4,column);
printf("[%04x] dsm =%04x",&pDPB->dsm,pDPB->dsm);
printf("[%x] dsm =%x",&pDPB->dsm,pDPB->dsm);
crtlc(line+5,column);
printf("[%04x] drm =%04x",&pDPB->drm,pDPB->drm);
printf("[%x] drm =%x",&pDPB->drm,pDPB->drm);
crtlc(line+6,column);
printf("[%04x] al0 =%02x",&pDPB->al0,pDPB->al0);
printf("[%x] al0 =%x",&pDPB->al0,pDPB->al0);
crtlc(line+7,column);
printf("[%04x] al1 =%02x",&pDPB->al1,pDPB->al1);
printf("[%x] al1 =%x",&pDPB->al1,pDPB->al1);
crtlc(line+8,column);
printf("[%04x] cks =%04x",&pDPB->cks,pDPB->cks);
printf("[%x] cks =%x",&pDPB->cks,pDPB->cks);
crtlc(line+9,column);
printf("[%04x] off =%04x",&pDPB->off,pDPB->off);
printf("[%x] off =%x",&pDPB->off,pDPB->off);
}
struct DPB * dispdph(drive,line,column)
@ -149,31 +119,31 @@ struct DPB * dispdph(drive,line,column)
}
crtlc(line+0,column); printf("[%04x] xlt =%04x",
crtlc(line+0,column); printf("[%x] xlt =%x",
&pDPH->xlt,pDPH->xlt);
crtlc(line+1,column); printf("[%04x] rv1 =%04x",
crtlc(line+1,column); printf("[%x] rv1 =%x",
&pDPH->rv1,pDPH->rv1);
crtlc(line+2,column); printf("[%04x] rv2 =%04x",
crtlc(line+2,column); printf("[%x] rv2 =%x",
&pDPH->rv2,pDPH->rv2);
crtlc(line+3,column); printf("[%04x] rv3 =%04x",
crtlc(line+3,column); printf("[%x] rv3 =%x",
&pDPH->rv3,pDPH->rv3);
crtlc(line+4,column); printf("[%04x] dbf =%04x",
crtlc(line+4,column); printf("[%x] dbf =%x",
&pDPH->dbf,pDPH->dbf);
crtlc(line+5,column); printf("[%04x] dpb =%04x",
crtlc(line+5,column); printf("[%x] dpb =%x",
&pDPH->dpb,pDPH->dpb);
crtlc(line+6,column); printf("[%04x] csv =%04x",
crtlc(line+6,column); printf("[%x] csv =%x",
&pDPH->csv,pDPH->csv);
crtlc(line+7,column); printf("[%04x] alv =%04x",
crtlc(line+7,column); printf("[%x] alv =%x",
&pDPH->alv,pDPH->alv);
if( ('L' == pDPH->sigl) && ('U' == pDPH->sigu) ) {
crtlc(line+8,column);
printf("[%04x] sigl=%02x",&pDPH->sigl,pDPH->sigl);
printf("[%x] sigl=%x",&pDPH->sigl,pDPH->sigl);
crtlc(line+9,column);
printf("[%04x] sigu=%02x",&pDPH->sigu,pDPH->sigu);
printf("[%x] sigu=%x",&pDPH->sigu,pDPH->sigu);
crtlc(line+10,column);
printf("[%04x] curr=%04x",&pDPH->current,pDPH->current);
printf("[%x] curr=%x",&pDPH->current,pDPH->current);
crtlc(line+11,column);
printf("[%04x] numb=%04x",&pDPH->number,pDPH->number);
printf("[%x] numb=%x",&pDPH->number,pDPH->number);
}
if(DSM720 == pDPB->dsm) {

2
Doc/ChangeLog.txt
View File

@ -18,6 +18,8 @@ Version 2.5
- WBW: Updated Apps built with Aztec C to use the TINY library
- WBW: Updated CPMNAME application to reflect latest config data block
- WBW: Support up to 4 UART devices
- WBW: Partial support for Multifunction / PIC (UART & PPIDE)
- WBW: Add chip detection to UART driver
Version 2.1.1
-------------

4
ReadMe.txt
View File

@ -8,8 +8,8 @@ Builders: Wayne Warthen (wwarthen@gmail.com)
Douglas Goodall (douglas_goodall@mac.com)
David Giles (vk5dg@internode.on.net)
Updated: 2013-05-24
Version: 2.5 Beta 12
Updated: 2013-06-07
Version: 2.5 Beta 13
This is an adaptation of CP/M-80 2.2 and ZSDOS/ZCPR
targeting ROMs for all N8VEM Z80 hardware variations

BIN
RomDsk/cfg_n8vem_mfp/1200.COM
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BIN
RomDsk/cfg_n8vem_mfp/38400.COM
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BIN
RomDsk/cfg_n8vem_mfp/9600.COM
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BIN
RomDsk/cfg_n8vem_mfp/FLASHZ.COM
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BIN
RomDsk/cfg_n8vem_mfp/LDTIM.COM
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BIN
RomDsk/cfg_n8vem_mfp/RTC.COM
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BIN
RomDsk/cfg_n8vem_mfp/T5.COM
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BIN
RomDsk/cfg_n8vem_mfp/VT3.COM
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BIN
RomDsk/cfg_n8vem_mfp/XM.COM
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BIN
RomDsk/cfg_n8vem_mfp/XM5.COM
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32
RomList.txt
View File

@ -86,7 +86,22 @@ DRI CP/M (BDOS & CCP)
for the Propeller found in the Support directory!
- NOTE: Console defaults to VGA & PS/2 Keyboard. Short JP2
(one bit input port) to use the serial port as the console.
N8VEM_mfp.rom for N8VEM Z80 SBC V1/V2:
- 512KB ROM, 512KB RAM
- 38.4KB serial console baud rate
- Basic ROM/RAM disk (no floppy)
- Drives A:=ROM, B:=RAM, C:=PPIDE0-00, D:=PPIDE0-01, E:=PPIDE0-02, F:=PPIDE0-03
- IDE support via Multifunction / PIC
- Second UART via Multifunction / PIC
N8VEM_ci.rom for N8VEM Z80 SBC V1/V2:
- 512KB ROM, 512KB RAM
- 38.4KB serial console baud rate
- Basic ROM/RAM disk (no floppy/IDE)
- Drives A:=ROM, B:=RAM
- Cassette Interface mapped to RDR/PUN
N8VEM_simh.rom for N8VEM SIMH Simulator:
- 512KB ROM, 512KB RAM
- 38.4KB serial console baud rate
@ -217,6 +232,21 @@ ZSYSTEM (ZSDOS & ZCPR)
- VDU board support
- Drives A:=ROM, B:=RAM
N8VEM_mfp_z.rom for N8VEM Z80 SBC V1/V2:
- 512KB ROM, 512KB RAM
- 38.4KB serial console baud rate
- Basic ROM/RAM disk (no floppy)
- Drives A:=ROM, B:=RAM, C:=PPIDE0-00, D:=PPIDE0-01, E:=PPIDE0-02, F:=PPIDE0-03
- IDE support via Multifunction / PIC
- Second UART via Multifunction / PIC
N8VEM_ci_z.rom for N8VEM Z80 SBC V1/V2:
- 512KB ROM, 512KB RAM
- 38.4KB serial console baud rate
- Basic ROM/RAM disk (no floppy/IDE)
- Drives A:=ROM, B:=RAM
- Cassette Interface mapped to RDR/PUN
N8VEM_simh_Z.rom for N8VEM SIMH Simulator:
- 512KB ROM, 512KB RAM
- 38.4KB serial console baud rate

2
Source/bootapp.asm
View File

@ -79,7 +79,7 @@
;
JP PHASE2 ; JUMP TO PHASE 2 BOOT IN UPPER MEMORY
;
STR_BOOT .DB "Boot$"
STR_BOOT .DB "RomWBW$"
;
; IMBED DIRECT SERIAL I/O ROUTINES
;

2
Source/bootrom.asm
View File

@ -62,7 +62,7 @@
;
JP PHASE2 ; JUMP TO PHASE 2 BOOT IN UPPER MEMORY
;
STR_BOOT .DB "Boot$"
STR_BOOT .DB "RomWBW$"
;
; IMBED DIRECT SERIAL I/O ROUTINES
;

18
Source/cbios.asm
View File

@ -512,9 +512,21 @@ READWRITE:
#ENDIF
LD A,(SEKDU) ; GET DEVICE/UNIT
AND 0F0H ; ISOLATE DEVICE NIBBLE
JR Z,DIRRW ; DEVICE = 0 = MD, SO DIRECT R/W
JP BLKRW ; OTHERWISE, (DE)BLOCKING R/W
; JR Z,DIRRW ; DEVICE = 0 = MD, SO DIRECT R/W
; JP BLKRW ; OTHERWISE, (DE)BLOCKING R/W
JR NZ,BLKRW ; DEVICE != 0, (DE)BLOCKING R/W
;
LD (STKSAV),SP ; SAVE STACK
LD SP,TMPSTK ; TEMP STACK
CALL DIRRW ; DEVICE = 0 = MD, SO DIRECT R/W
LD SP,(STKSAV) ; RESTORE STACK
RET ; DONE
;
; NEED TO FORCE STACK INTO UPPER MEMORY DUE TO PAGING OF LOWER MEMORY
;
STKSAV .DW 0
.FILL 16
TMPSTK .EQU $
;
;==================================================================================================
; DIRECT READ/WRITE (NO (DE)BLOCKING, NO BUFFERING, 128 BYTE SECTOR)

2
Source/config_n8_2312.asm
View File

@ -52,7 +52,7 @@ IDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!
IDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)
;
PPIDEENABLE .EQU FALSE ; TRUE FOR PPIDE SUPPORT (DO NOT COMBINE WITH DSKYENABLE)
PPIDEMODE .EQU PPIDEMODE_STD ; PPIDEMODE_STD, PPIDEMODE_DIO3
PPIDEIOB .EQU $60 ; PPIDE IOBASE
PPIDETRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPIDEENABLE = TRUE)
PPIDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!)
PPIDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)

2
Source/config_n8_2511.asm
View File

@ -52,7 +52,7 @@ IDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!
IDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)
;
PPIDEENABLE .EQU FALSE ; TRUE FOR PPIDE SUPPORT (DO NOT COMBINE WITH DSKYENABLE)
PPIDEMODE .EQU PPIDEMODE_STD ; PPIDEMODE_STD, PPIDEMODE_DIO3
PPIDEIOB .EQU $60 ; PPIDE IOBASE
PPIDETRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPIDEENABLE = TRUE)
PPIDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!)
PPIDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)

4
Source/config_n8vem_ci.asm
View File

@ -1,6 +1,6 @@
;
;==================================================================================================
; ROMWBW 2.X CONFIGURATION FOR N8VEM SBC
; ROMWBW 2.X CONFIGURATION FOR N8VEM SBC W/ CASSETTE INTERFACE
;==================================================================================================
;
; BUILD CONFIGURATION OPTIONS
@ -60,7 +60,7 @@ IDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!
IDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)
;
PPIDEENABLE .EQU FALSE ; TRUE FOR PPIDE SUPPORT (DO NOT COMBINE WITH DSKYENABLE)
PPIDEMODE .EQU PPIDEMODE_STD ; PPIDEMODE_STD, PPIDEMODE_DIO3
PPIDEIOB .EQU $60 ; PPIDE IOBASE
PPIDETRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPIDEENABLE = TRUE)
PPIDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!)
PPIDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)

2
Source/config_n8vem_cvdu.asm
View File

@ -56,7 +56,7 @@ IDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!
IDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)
;
PPIDEENABLE .EQU TRUE ; TRUE FOR PPIDE SUPPORT (DO NOT COMBINE WITH DSKYENABLE)
PPIDEMODE .EQU PPIDEMODE_STD ; PPIDEMODE_STD, PPIDEMODE_DIO3
PPIDEIOB .EQU $60 ; PPIDE IOBASE
PPIDETRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPIDEENABLE = TRUE)
PPIDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!)
PPIDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)

2
Source/config_n8vem_dide.asm
View File

@ -56,7 +56,7 @@ IDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!
IDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)
;
PPIDEENABLE .EQU FALSE ; TRUE FOR PPIDE SUPPORT (DO NOT COMBINE WITH DSKYENABLE)
PPIDEMODE .EQU PPIDEMODE_STD ; PPIDEMODE_STD, PPIDEMODE_DIO3
PPIDEIOB .EQU $60 ; PPIDE IOBASE
PPIDETRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPIDEENABLE = TRUE)
PPIDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!)
PPIDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)

2
Source/config_n8vem_diskio.asm
View File

@ -56,7 +56,7 @@ IDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!
IDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)
;
PPIDEENABLE .EQU FALSE ; TRUE FOR PPIDE SUPPORT (DO NOT COMBINE WITH DSKYENABLE)
PPIDEMODE .EQU PPIDEMODE_STD ; PPIDEMODE_STD, PPIDEMODE_DIO3
PPIDEIOB .EQU $60 ; PPIDE IOBASE
PPIDETRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPIDEENABLE = TRUE)
PPIDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!)
PPIDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)

2
Source/config_n8vem_diskio3.asm
View File

@ -56,7 +56,7 @@ IDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!
IDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)
;
PPIDEENABLE .EQU TRUE ; TRUE FOR PPIDE SUPPORT (DO NOT COMBINE WITH DSKYENABLE)
PPIDEMODE .EQU PPIDEMODE_DIO3 ; PPIDEMODE_STD, PPIDEMODE_DIO3
PPIDEIOB .EQU $20 ; PPIDE IOBASE IS $20 FOR DISKIO V3
PPIDETRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPIDEENABLE = TRUE)
PPIDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!)
PPIDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)

2
Source/config_n8vem_dsd.asm
View File

@ -56,7 +56,7 @@ IDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!
IDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)
;
PPIDEENABLE .EQU FALSE ; TRUE FOR PPIDE SUPPORT (DO NOT COMBINE WITH DSKYENABLE)
PPIDEMODE .EQU PPIDEMODE_STD ; PPIDEMODE_STD, PPIDEMODE_DIO3
PPIDEIOB .EQU $60 ; PPIDE IOBASE
PPIDETRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPIDEENABLE = TRUE)
PPIDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!)
PPIDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)

102
Source/config_n8vem_mfp.asm
View File

@ -0,0 +1,102 @@
;
;==================================================================================================
; ROMWBW 2.X CONFIGURATION FOR N8VEM SBC W/ MULTIFUNCTION PIC
;==================================================================================================
;
; BUILD CONFIGURATION OPTIONS
;
CPUFREQ .EQU 8 ; IN MHZ, USED TO COMPUTE DELAY FACTORS
;
DEFCON .EQU CIODEV_UART ; DEFAULT CONSOLE DEVICE (LOADER AND MONITOR): CIODEV_UART, DIODEV_CRT, CIODEV_PRPCON, CIODEV_PPPCON
ALTCON .EQU DEFCON ; ALT CONSOLE DEVICE (USED WHEN CONFIG JUMPER SHORTED)
CONBAUD .EQU 38400 ; BAUDRATE FOR CONSOLE DURING HARDWARE INIT
DEFVDA .EQU VDADEV_NONE ; DEFAULT VDA DEVICE (VDADEV_NONE, VDADEV_VDU, VDADEV_CVDU, VDADEV_N8V, VDADEV_UPD7220)
DEFEMU .EQU EMUTYP_TTY ; DEFAULT VDA EMULATION (EMUTYP_TTY, EMUTYP_ANSI, ...)
TERMTYPE .EQU TERM_ANSI ; TERM_TTY=0, TERM_ANSI=1, TERM_WYSE=2
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB, MUST MATCH YOUR HARDWARE!!!
CLRRAMDISK .EQU CLR_AUTO ; CLR_ALWAYS, CLR_NEVER, CLR_AUTO (CLEAR IF INVALID DIR AREA)
;
DSKMAP .EQU DM_RAM ; DM_ROM, DM_RAM, DM_FD, DM_IDE, DM_PPIDE, DM_SD, DM_PRPSD, DM_PPPSD
;
DSKYENABLE .EQU FALSE ; TRUE FOR DSKY SUPPORT (DO NOT COMBINE WITH PPIDE)
;
UARTENABLE .EQU TRUE ; TRUE FOR UART SUPPORT (ALMOST ALWAYS WANT THIS TO BE TRUE)
UARTCNT .EQU 2 ; NUMBER OF UARTS
UART0IOB .EQU $68 ; UART0 IOBASE
UART0BAUD .EQU CONBAUD ; UART0 BAUDRATE
UART0FIFO .EQU TRUE ; UART0 TRUE ENABLES UART FIFO (16550 ASSUMED, N8VEM AND ZETA ONLY)
UART0AFC .EQU FALSE ; UART0 TRUE ENABLES AUTO FLOW CONTROL (YOUR TERMINAL/UART MUST SUPPORT RTS/CTS FLOW CONTROL!!!)
UART1IOB .EQU $88 ; UART1 IOBASE AT $88 FOR MFPIC
UART1BAUD .EQU 38400 ; UART1 BAUDRATE IS 38400 FOR MFPIC
UART1FIFO .EQU TRUE ; UART1 FIFO ENABLED FOR MFPIC
UART1AFC .EQU FALSE ; UART1 AUTO FLOW CONTROL DISABLED FOR MFPIC (ENABLE IF DESIRED)
;
ASCIENABLE .EQU FALSE ; TRUE FOR Z180 ASCI SUPPORT
ASCI0BAUD .EQU 38400 ; ASCI0 BAUDRATE (IMPLEMENTED BY Z180_CNTLB0)
ASCI1BAUD .EQU 38400 ; ASCI1 BAUDRATE (IMPLEMENTED BY Z180_CNTLB1)
;
VDUENABLE .EQU FALSE ; TRUE FOR VDU BOARD SUPPORT
CVDUENABLE .EQU FALSE ; TRUE FOR CVDU BOARD SUPPORT
UPD7220ENABLE .EQU FALSE ; TRUE FOR uPD7220 BOARD SUPPORT
N8VENABLE .EQU FALSE ; TRUE FOR N8 (TMS9918) VIDEO/KBD SUPPORT
;
DEFIOBYTE .EQU $00 ; DEFAULT INITIAL VALUE FOR CP/M IOBYTE, $00=TTY, $01=CRT (MUST HAVE CRT HARDWARE)
ALTIOBYTE .EQU DEFIOBYTE ; ALT INITIAL VALUE (USED WHEN CONFIG JUMPER SHORTED)
WRTCACHE .EQU TRUE ; ENABLE WRITE CACHING IN CBIOS (DE)BLOCKING ALGORITHM
DSKTRACE .EQU FALSE ; ENABLE TRACING OF CBIOS DISK FUNCTION CALLS
;
FDENABLE .EQU FALSE ; TRUE FOR FLOPPY SUPPORT
FDMODE .EQU FDMODE_DIO ; FDMODE_DIO, FDMODE_ZETA, FDMODE_DIDE, FDMODE_N8, FDMODE_DIO3
FDTRACE .EQU 1 ; 0=SILENT, 1=FATAL ERRORS, 2=ALL ERRORS, 3=EVERYTHING (ONLY RELEVANT IF FDENABLE = TRUE)
FDMEDIA .EQU FDM144 ; FDM720, FDM144, FDM360, FDM120 (ONLY RELEVANT IF FDENABLE = TRUE)
FDMEDIAALT .EQU FDM720 ; ALTERNATE MEDIA TO TRY, SAME CHOICES AS ABOVE (ONLY RELEVANT IF FDMAUTO = TRUE)
FDMAUTO .EQU TRUE ; SELECT BETWEEN MEDIA OPTS ABOVE AUTOMATICALLY
;
IDEENABLE .EQU FALSE ; TRUE FOR IDE SUPPORT
IDEMODE .EQU IDEMODE_DIO ; IDEMODE_DIO, IDEMODE_DIDE
IDETRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF IDEENABLE = TRUE)
IDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!)
IDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)
;
PPIDEENABLE .EQU TRUE ; TRUE FOR PPIDE SUPPORT (DO NOT COMBINE WITH DSKYENABLE)
PPIDEIOB .EQU $84 ; PPIDE IOBASE IS $84 FOR MFPIC (PRELIMINARY ADDRESS)
PPIDETRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPIDEENABLE = TRUE)
PPIDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!)
PPIDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)
PPIDESLOW .EQU FALSE ; ADD DELAYS TO HELP PROBLEMATIC HARDWARE (TRY THIS IF PPIDE IS UNRELIABLE)
;
SDENABLE .EQU FALSE ; TRUE FOR SD SUPPORT
SDMODE .EQU SDMODE_JUHA ; SDMODE_JUHA, SDMODE_CSIO, SDMODE_UART, SDMODE_PPI, SDMODE_DSD
SDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF IDEENABLE = TRUE)
SDCAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)
SDCSIOFAST .EQU FALSE ; TABLE-DRIVEN BIT INVERTER
;
PRPENABLE .EQU FALSE ; TRUE FOR PROPIO SD SUPPORT (FOR N8VEM PROPIO ONLY!)
PRPSDENABLE .EQU TRUE ; TRUE FOR PROPIO SD SUPPORT (FOR N8VEM PROPIO ONLY!)
PRPSDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PRPSDENABLE = TRUE)
PRPSDCAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)
PRPCONENABLE .EQU TRUE ; TRUE FOR PROPIO CONSOLE SUPPORT (PS/2 KBD & VGA VIDEO)
;
PPPENABLE .EQU FALSE ; TRUE FOR PARPORTPROP SUPPORT
PPPSDENABLE .EQU TRUE ; TRUE FOR PROPIO SD SUPPORT (FOR N8VEM PROPIO ONLY!)
PPPSDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPPENABLE = TRUE)
PPPSDCAPACITY .EQU 64 ; CAPACITY OF PPP SD DEVICE (IN MB)
PPPCONENABLE .EQU TRUE ; TRUE FOR PROPIO CONSOLE SUPPORT (PS/2 KBD & VGA VIDEO)
;
HDSKENABLE .EQU FALSE ; TRUE FOR SIMH HDSK SUPPORT
HDSKTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF IDEENABLE = TRUE)
HDSKCAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)
;
PPKENABLE .EQU FALSE ; TRUE FOR PARALLEL PORT KEYBOARD
PPKTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPKENABLE = TRUE)
KBDENABLE .EQU FALSE ; TRUE FOR PS/2 KEYBOARD ON I8242
KBDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF KBDENABLE = TRUE)
;
TTYENABLE .EQU FALSE ; INCLUDE TTY EMULATION SUPPORT
ANSIENABLE .EQU FALSE ; INCLUDE ANSI EMULATION SUPPORT
ANSITRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF ANSIENABLE = TRUE)
;
BOOTTYPE .EQU BT_MENU ; BT_MENU (WAIT FOR KEYPRESS), BT_AUTO (BOOT_DEFAULT AFTER BOOT_TIMEOUT SECS)
BOOT_TIMEOUT .EQU 20 ; APPROX TIMEOUT IN SECONDS FOR AUTOBOOT, 0 FOR IMMEDIATE
BOOT_DEFAULT .EQU 'R' ; SELECTION TO INVOKE AT TIMEOUT

2
Source/config_n8vem_ppide.asm
View File

@ -56,7 +56,7 @@ IDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!
IDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)
;
PPIDEENABLE .EQU TRUE ; TRUE FOR PPIDE SUPPORT (DO NOT COMBINE WITH DSKYENABLE)
PPIDEMODE .EQU PPIDEMODE_STD ; PPIDEMODE_STD, PPIDEMODE_DIO3
PPIDEIOB .EQU $60 ; PPIDE IOBASE
PPIDETRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPIDEENABLE = TRUE)
PPIDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!)
PPIDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)

2
Source/config_n8vem_ppisd.asm
View File

@ -56,7 +56,7 @@ IDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!
IDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)
;
PPIDEENABLE .EQU FALSE ; TRUE FOR PPIDE SUPPORT (DO NOT COMBINE WITH DSKYENABLE)
PPIDEMODE .EQU PPIDEMODE_STD ; PPIDEMODE_STD, PPIDEMODE_DIO3
PPIDEIOB .EQU $60 ; PPIDE IOBASE
PPIDETRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPIDEENABLE = TRUE)
PPIDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!)
PPIDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)

2
Source/config_n8vem_propio.asm
View File

@ -56,7 +56,7 @@ IDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!
IDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)
;
PPIDEENABLE .EQU FALSE ; TRUE FOR PPIDE SUPPORT (DO NOT COMBINE WITH DSKYENABLE)
PPIDEMODE .EQU PPIDEMODE_STD ; PPIDEMODE_STD, PPIDEMODE_DIO3
PPIDEIOB .EQU $60 ; PPIDE IOBASE
PPIDETRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPIDEENABLE = TRUE)
PPIDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!)
PPIDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)

2
Source/config_n8vem_simh.asm
View File

@ -56,7 +56,7 @@ IDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!
IDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)
;
PPIDEENABLE .EQU FALSE ; TRUE FOR PPIDE SUPPORT (DO NOT COMBINE WITH DSKYENABLE)
PPIDEMODE .EQU PPIDEMODE_STD ; PPIDEMODE_STD, PPIDEMODE_DIO3
PPIDEIOB .EQU $60 ; PPIDE IOBASE
PPIDETRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPIDEENABLE = TRUE)
PPIDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!)
PPIDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)

2
Source/config_n8vem_std.asm
View File

@ -56,7 +56,7 @@ IDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!
IDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)
;
PPIDEENABLE .EQU FALSE ; TRUE FOR PPIDE SUPPORT (DO NOT COMBINE WITH DSKYENABLE)
PPIDEMODE .EQU PPIDEMODE_STD ; PPIDEMODE_STD, PPIDEMODE_DIO3
PPIDEIOB .EQU $60 ; PPIDE IOBASE
PPIDETRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPIDEENABLE = TRUE)
PPIDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!)
PPIDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)

2
Source/config_n8vem_vdu.asm
View File

@ -56,7 +56,7 @@ IDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!
IDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)
;
PPIDEENABLE .EQU TRUE ; TRUE FOR PPIDE SUPPORT (DO NOT COMBINE WITH DSKYENABLE)
PPIDEMODE .EQU PPIDEMODE_DIO3 ; PPIDEMODE_STD, PPIDEMODE_DIO3
PPIDEIOB .EQU $60 ; PPIDE IOBASE
PPIDETRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPIDEENABLE = TRUE)
PPIDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!)
PPIDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)

2
Source/config_zeta_ppp.asm
View File

@ -56,7 +56,7 @@ IDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!
IDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)
;
PPIDEENABLE .EQU FALSE ; TRUE FOR PPIDE SUPPORT (DO NOT COMBINE WITH DSKYENABLE)
PPIDEMODE .EQU PPIDEMODE_STD ; PPIDEMODE_STD, PPIDEMODE_DIO3
PPIDEIOB .EQU $60 ; PPIDE IOBASE
PPIDETRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPIDEENABLE = TRUE)
PPIDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!)
PPIDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)

2
Source/config_zeta_std.asm
View File

@ -56,7 +56,7 @@ IDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!
IDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)
;
PPIDEENABLE .EQU TRUE ; TRUE FOR PPIDE SUPPORT (DO NOT COMBINE WITH DSKYENABLE)
PPIDEMODE .EQU PPIDEMODE_STD ; PPIDEMODE_STD, PPIDEMODE_DIO3
PPIDEIOB .EQU $60 ; PPIDE IOBASE
PPIDETRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPIDEENABLE = TRUE)
PPIDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!)
PPIDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)

15
Source/ppide.asm
View File

@ -18,17 +18,10 @@
;
; MAP PPI PORTS TO PPIDE PORTS
;
#IF (PPIDEMODE == PPIDEMODE_DIO3)
IDELSB .EQU 20H ; LSB
IDEMSB .EQU 21H ; MSB
IDECTL .EQU 22H ; CONTROL SIGNALS
PPI1CONT .EQU 23H ; CONTROL BYTE PPI 82C55
#ELSE
IDELSB .EQU PPIA ; LSB
IDEMSB .EQU PPIB ; MSB
IDECTL .EQU PPIC ; CONTROL SIGNALS
PPI1CONT .EQU PPIX ; CONTROL BYTE PPI 82C55
#ENDIF
IDELSB .EQU PPIDEIOB + 0 ; LSB
IDEMSB .EQU PPIDEIOB + 1 ; MSB
IDECTL .EQU PPIDEIOB + 2 ; CONTROL SIGNALS
PPI1CONT .EQU PPIDEIOB + 3 ; CONTROL BYTE PPI 82C55
;
; PPI control bytes for read and write to IDE drive
;

1
Source/std.asm
View File

@ -98,6 +98,7 @@ IDEMODE_DIDE .EQU 2 ; DUAL IDE
PPIDEMODE_NONE .EQU 0
PPIDEMODE_STD .EQU 1 ; STANDARD N8VEM PARALLEL PORT
PPIDEMODE_DIO3 .EQU 2 ; DISKIO V3 PARALLEL PORT
PPIDEMODE_MFP .EQU 3 ; MULTIFUNCTION / PIC
;
; SD MODE SELECTIONS
;

2
Source/syscfg.asm
View File

@ -134,7 +134,7 @@ BOOTTIME .DB 0,0,0,0,0,0 ; SYSTEM STARTUP TIME (YY,MM,DD,HH,MM,SS)
.DW IDECAPACITY
.DB PPIDEENABLE
.DB PPIDEMODE
.DB PPIDEIOB
.DB PPIDETRACE
.DB PPIDE8BIT
.DW PPIDECAPACITY

486
Source/uart.asm
View File

@ -3,6 +3,35 @@
; UART DRIVER (SERIAL PORT)
;==================================================================================================
;
UART_DEBUG .EQU FALSE
;
UART_NONE .EQU 0 ; UNKNOWN OR NOT PRESENT
UART_8250 .EQU 1
UART_16450 .EQU 2
UART_16550 .EQU 3
UART_16550A .EQU 4
UART_16550C .EQU 5
UART_16650 .EQU 6
UART_16750 .EQU 7
UART_16850 .EQU 8
;
UART_RBR .EQU 0 ; DLAB=0: RCVR BUFFER REG (READ)
UART_THR .EQU 0 ; DLAB=0: XMIT HOLDING REG (WRITE)
UART_IER .EQU 1 ; DLAB=0: INT ENABLE REG (READ)
UART_IIR .EQU 2 ; INT IDENT REGISTER (READ)
UART_FCR .EQU 2 ; FIFO CONTROL REG (WRITE)
UART_LCR .EQU 3 ; LINE CONTROL REG (READ/WRITE)
UART_MCR .EQU 4 ; MODEM CONTROL REG (READ/WRITE)
UART_LSR .EQU 5 ; LINE STATUS REG (READ)
UART_MSR .EQU 6 ; MODEM STATUS REG (READ)
UART_SCR .EQU 7 ; SCRATCH REGISTER (READ/WRITE)
UART_DLL .EQU 0 ; DLAB=1: DIVISOR LATCH (LS) (READ/WRITE)
UART_DLM .EQU 1 ; DLAB=1: DIVISOR LATCH (MS) (READ/WRITE)
UART_EFR .EQU 2 ; LCR=$BF: ENHANCED FEATURE REG (READ/WRITE)
;
#DEFINE UART_IN(RID) CALL UART_INP \ .DB RID
#DEFINE UART_OUT(RID) CALL UART_OUTP \ .DB RID
;
#IF (UARTCNT >= 1)
UART0_RBR .EQU UART0IOB + 0 ; DLAB=0: RCVR BUFFER REG (READ ONLY)
UART0_THR .EQU UART0IOB + 0 ; DLAB=0: XMIT HOLDING REG (WRITE ONLY)
@ -16,8 +45,10 @@ UART0_MSR .EQU UART0IOB + 6 ; MODEM STATUS REG
UART0_SCR .EQU UART0IOB + 7 ; SCRATCH REGISTER
UART0_DLL .EQU UART0IOB + 0 ; DLAB=1: DIVISOR LATCH (LS)
UART0_DLM .EQU UART0IOB + 1 ; DLAB=1: DIVISOR LATCH (MS)
UART0_EFR .EQU UART0IOB + 2 ; ENHANCED FEATURE (WHEN LCR = $BF)
;
UART0_DIV .EQU (1843200 / (16 * UART0BAUD))
;
#ENDIF
;
#IF (UARTCNT >= 2)
@ -33,6 +64,7 @@ UART1_MSR .EQU UART1IOB + 6 ; MODEM STATUS REG
UART1_SCR .EQU UART1IOB + 7 ; SCRATCH REGISTER
UART1_DLL .EQU UART1IOB + 0 ; DLAB=1: DIVISOR LATCH (LS)
UART1_DLM .EQU UART1IOB + 1 ; DLAB=1: DIVISOR LATCH (MS)
UART1_EFR .EQU UART1IOB + 2 ; ENHANCED FEATURE (WHEN LCR = $BF)
;
UART1_DIV .EQU (1843200 / (16 * UART1BAUD))
#ENDIF
@ -50,6 +82,7 @@ UART2_MSR .EQU UART2IOB + 6 ; MODEM STATUS REG
UART2_SCR .EQU UART2IOB + 7 ; SCRATCH REGISTER
UART2_DLL .EQU UART2IOB + 0 ; DLAB=1: DIVISOR LATCH (LS)
UART2_DLM .EQU UART2IOB + 1 ; DLAB=1: DIVISOR LATCH (MS)
UART2_EFR .EQU UART2IOB + 2 ; ENHANCED FEATURE (WHEN LCR = $BF)
;
UART2_DIV .EQU (1843200 / (16 * UART2BAUD))
#ENDIF
@ -67,6 +100,7 @@ UART3_MSR .EQU UART3IOB + 6 ; MODEM STATUS REG
UART3_SCR .EQU UART3IOB + 7 ; SCRATCH REGISTER
UART3_DLL .EQU UART3IOB + 0 ; DLAB=1: DIVISOR LATCH (LS)
UART3_DLM .EQU UART3IOB + 1 ; DLAB=1: DIVISOR LATCH (MS)
UART3_EFR .EQU UART3IOB + 2 ; ENHANCED FEATURE (WHEN LCR = $BF)
;
UART3_DIV .EQU (1843200 / (16 * UART3BAUD))
#ENDIF
@ -124,50 +158,25 @@ UART0_INIT:
PRTS("UART0: IO=0x$")
LD A,UART0IOB
CALL PRTHEXBYTE
PRTS(" BAUD=$")
LD HL,UART0BAUD / 10
CALL PRTDEC
PRTC('0')
LD A,80H
OUT (UART0_LCR),A ; DLAB ON
LD A,UART0_DIV % $100
OUT (UART0_DLL),A ; SET DIVISOR (LS)
LD A,UART0_DIV / $100
OUT (UART0_DLM),A ; SET DIVISOR (MS)
LD B,03H ; B = DEFAULT SETTING FOR MCR (DTR + RTS)
#IF (UART0AFC)
PRTS(" AFC$")
LD A,$55 ; TEST VALUE
OUT (UART0_SCR),A ; SET SCRATCH REG TO TEST VALUE
LD A,0BFH
OUT (UART0_LCR),A ; SET LCR=$BF TO ATTEMPT TO ACCESS EFR
IN A,(UART0_SCR) ; READ SCRATCH REGISTER
CP $55 ; IF $55, NO EFR
JR NZ,UART0_AFC1 ; NZ, HAVE EFR, DO IT
SET 5,B ; ENABLE AUTO FLOW CONTROL
JR UART0_AFC2
UART0_AFC1:
LD A,0C0H ; ENABLE CTS/RTS FLOW CONTROL
OUT (UART0_EFR),A ; SAVE IT
UART0_AFC2:
#ENDIF
LD A,03H
OUT (UART0_LCR),A ; DLAB OFF, 8 DATA, 1 STOP, NO PARITY
LD A,B ; LOAD MCR VALUE TO SET
OUT (UART0_MCR),A ; SAVE IT
;
; SETUP FOR GENERIC INIT ROUTINE
LD (UART_BASE),A ; IO BASE ADDRESS
LD DE,UART0BAUD / 10 ; BAUD RATE / 10
LD (UART_BAUD),DE ; SAVE IT
LD DE,UART0_DIV ; DIVISOR
LD (UART_DIV),DE ; SAVE IT
;
; MAP REQUESTED FEATURES TO FLAGS IN UART_FUNC
XOR A ; START WITH NO FEATURES
#IF (UART0FIFO)
; LD A,07H ; ENABLE AND RESET FIFOS
LD A,01H ; ENABLE AND RESET FIFOS
OUT (UART0_FCR),A ; ENABLE FIFOS
PRTS(" FIFO$")
SET UART_FIFO,A ; TURN ON FIFO BIT IF REQUESTED
#ENDIF
RET
#IF (UART0AFC)
SET UART_AFC,A ; TURN ON AFC BIT IF REQUESTED
#ENDIF
LD (UART_FUNC),A ; SAVE IT
;
JP UART_INITP ; HAND OFF TO GENERIC INIT CODE
;
;
;
@ -232,50 +241,25 @@ UART1_INIT:
PRTS("UART1: IO=0x$")
LD A,UART1IOB
CALL PRTHEXBYTE
PRTS(" BAUD=$")
LD HL,UART1BAUD / 10
CALL PRTDEC
PRTC('0')
LD A,80H
OUT (UART1_LCR),A ; DLAB ON
LD A,UART1_DIV % $100
OUT (UART1_DLL),A ; SET DIVISOR (LS)
LD A,UART1_DIV / $100
OUT (UART1_DLM),A ; SET DIVISOR (MS)
LD B,03H ; B = DEFAULT SETTING FOR MCR (DTR + RTS)
#IF (UART1AFC)
PRTS(" AFC$")
LD A,$55 ; TEST VALUE
OUT (UART1_SCR),A ; SET SCRATCH REG TO TEST VALUE
LD A,0BFH
OUT (UART1_LCR),A ; SET LCR=$BF TO ATTEMPT TO ACCESS EFR
IN A,(UART1_SCR) ; READ SCRATCH REGISTER
CP $55 ; IF $55, NO EFR
JR NZ,UART1_AFC1 ; NZ, HAVE EFR, DO IT
SET 5,B ; ENABLE AUTO FLOW CONTROL
JR UART1_AFC2
UART1_AFC1:
LD A,0C0H ; ENABLE CTS/RTS FLOW CONTROL
OUT (UART1_EFR),A ; SAVE IT
UART1_AFC2:
#ENDIF
LD A,03H
OUT (UART1_LCR),A ; DLAB OFF, 8 DATA, 1 STOP, NO PARITY
LD A,B ; LOAD MCR VALUE TO SET
OUT (UART1_MCR),A ; SAVE IT
;
; SETUP FOR GENERIC INIT ROUTINE
LD (UART_BASE),A ; IO BASE ADDRESS
LD DE,UART1BAUD / 10 ; BAUD RATE / 10
LD (UART_BAUD),DE ; SAVE IT
LD DE,UART1_DIV ; DIVISOR
LD (UART_DIV),DE ; SAVE IT
;
; MAP REQUESTED FEATURES TO FLAGS IN UART_FUNC
XOR A ; START WITH NO FEATURES
#IF (UART1FIFO)
; LD A,07H ; ENABLE AND RESET FIFOS
LD A,01H ; ENABLE AND RESET FIFOS
OUT (UART1_FCR),A ; ENABLE FIFOS
PRTS(" FIFO$")
SET UART_FIFO,A ; TURN ON FIFO BIT IF REQUESTED
#ENDIF
RET
#IF (UART1AFC)
SET UART_AFC,A ; TURN ON AFC BIT IF REQUESTED
#ENDIF
LD (UART_FUNC),A ; SAVE IT
;
JP UART_INITP ; HAND OFF TO GENERIC INIT CODE
;
;
;
@ -330,3 +314,337 @@ UART1_OST:
RET
;
#ENDIF
;
; UART INITIALIZATION ROUTINE
;
UART_INITP:
LD DE,400 ; WAIT 1/10 SEC FOR UART TO SEND PENDING
CALL VDELAY
; DETECT THE UART TYPE
CALL UART_DETECT ; DETERMINE UART TYPE
LD (UART_TYPE),A ; SAVE TYPE
; HL IS USED BELOW TO REFER TO FEATURE BITS ENABLED
LD HL,UART_FEAT ; HL POINTS TO FEATURE FLAGS BYTE
XOR A ; RESET ALL FEATRUES
LD (HL),A ; SAVE IT
; START OF UART INITIALIZATION, SET BAUD RATE
LD A,80H
UART_OUT(UART_LCR) ; DLAB ON
LD DE,(UART_DIV)
LD A,E
UART_OUT(UART_DLL) ; SET DIVISOR (LS)
LD A,D
UART_OUT(UART_DLM) ; SET DIVISOR (MS)
; SET LCR TO DEFAULT
LD A,$03 ; DLAB OFF, 8 DATA, 1 STOP, NO PARITY
UART_OUT(UART_LCR) ; SAVE IT
; SET MCR TO DEFAULT
LD A,$03 ; DTR + RTS
UART_OUT(UART_MCR) ; SAVE IT
LD A,(UART_TYPE) ; GET UART TYPE
CP UART_16550A ; 16550A OR BETTER?
JR C,UART_INITP1 ; NOPE, SKIP FIFO & AFC FEATURES
LD B,0 ; START BY ASSUMING NO FIFOS, FCR=0
LD A,(UART_FUNC) ; LOAD FIFO ENABLE REQUEST VALUE
BIT UART_FIFO,A ; TEST FOR FIFO REQUESTED
JR Z,UART_FIFO1 ; NOPE
LD B,$07 ; VALUE TO ENABLE AND RESET FIFOS
SET UART_FIFO,(HL) ; RECORD FEATURE ENABLED
UART_FIFO1:
LD A,B ; MOVE VALUE TO A
UART_OUT(UART_FCR) ; DO IT
LD A,(UART_TYPE) ; GET UART TYPE
CP UART_16550C ; 16550C OR BETTER?
JR C,UART_INITP1 ; NOPE, SKIP AFC FEATURES
; BRANCH BASED ON TYPE AFC CONFIGURATION (EFR OR MCR)
LD A,(UART_TYPE) ; GET UART TYPE
CP UART_16650 ; 16650?
JR Z,UART_AFC2 ; USE EFR REGISTER
CP UART_16850 ; 16750?
JR Z,UART_AFC2 ; USE EFR REGISTER
; SET AFC VIA MCR
LD B,$03 ; START WITH DEFAULT MCR
LD A,(UART_FUNC) ; LOAD AFC ENABLE REQUEST VALUE
BIT UART_AFC,A ; TEST FOR AFC REQUESTED
JR Z,UART_AFC1 ; NOPE
SET 5,B ; SET MCR BIT TO ENABLE AFC
SET UART_AFC,(HL) ; RECORD FEATURE ENABLED
UART_AFC1:
LD A,B ; MOVE VALUE TO Ar
UART_OUT(UART_MCR) ; SET AFC VALUE VIA MCR
JR UART_INITP1 ; AND CONTINUE
UART_AFC2: ; SET AFC VIA EFR
LD A,$BF ; VALUE TO ACCESS EFR
UART_OUT(UART_LCR) ; SET VALUE IN LCR
LD B,0 ; ASSUME AFC OFF, EFR=0
LD A,(UART_FUNC) ; LOAD AFC ENABLE REQUEST VALUE
BIT UART_AFC,A ; TEST FOR AFC REQUESTED
JR Z,UART_AFC3 ; NOPE
LD B,$C0 ; ENABLE CTS/RTS FLOW CONTROL
SET UART_AFC,(HL) ; RECORD FEATURE ENABLED
UART_AFC3:
LD A,B ; MOVE VALUE TO A
UART_OUT(UART_EFR) ; SAVE IT
LD A,$03 ; NORMAL LCR VALUE
UART_OUT(UART_LCR) ; SAVE IT
UART_INITP1:
#IF (UART_DEBUG)
PRTS(" [$")
; DEBUG: DUMP UART TYPE
LD A,(UART_TYPE)
CALL PRTHEXBYTE
; DEBUG: DUMP IIR
UART_IN(UART_IIR)
CALL PC_SPACE
CALL PRTHEXBYTE
; DEBUG: DUMP LCR
UART_IN(UART_LCR)
CALL PC_SPACE
CALL PRTHEXBYTE
; DEBUG: DUMP MCR
UART_IN(UART_MCR)
CALL PC_SPACE
CALL PRTHEXBYTE
; DEBUG: DUMP EFR
LD A,$BF
UART_OUT(UART_LCR)
UART_IN(UART_EFR)
PUSH AF
LD A,$03
UART_OUT(UART_LCR)
POP AF
CALL PC_SPACE
CALL PRTHEXBYTE
PRTC(']')
#ENDIF
; PRINT THE UART TYPE
LD A,(UART_TYPE)
RLCA
LD HL,UART_TYPE_MAP
LD D,0
LD E,A
ADD HL,DE ; HL NOW POINTS TO MAP ENTRY
LD A,(HL)
INC HL
LD D,(HL)
LD E,A ; HL NOW POINTS TO STRING
CALL PC_SPACE
CALL WRITESTR ; PRINT THE STRING
;
; ALL DONE IF NO UART WAS DETECTED
LD A,(UART_TYPE)
OR A
JR Z,UART_INITP3
;
; PRINT BAUD RATE
PRTS(" BAUD=$")
LD HL,(UART_BAUD)
CALL PRTDEC
PRTC('0')
;
; PRINT FEATURES ENABLED
LD A,(UART_FEAT)
BIT UART_FIFO,A
JR Z,UART_INITP2
PRTS(" FIFO$")
UART_INITP2:
BIT UART_AFC,A
JR Z,UART_INITP3
PRTS(" AFC$")
UART_INITP3:
;
RET
;
; UART DETECTION ROUTINE
;
UART_DETECT:
;
; SEE IF UART IS THERE BY CHECKING DLAB FUNCTIONALITY
XOR A ; ZERO ACCUM
UART_OUT(UART_IER) ; IER := 0
LD A,$80 ; DLAB BIT ON
UART_OUT(UART_LCR) ; OUTPUT TO LCR (DLAB REGS NOW ACTIVE)
LD A,$5A ; LOAD TEST VALUE
UART_OUT(UART_DLM) ; OUTPUT TO DLM
UART_IN(UART_DLM) ; READ IT BACK
CP $5A ; CHECK FOR TEST VALUE
JR NZ,UART_DETECT_NONE ; NOPE, UNKNOWN UART OR NOT PRESENT
XOR A ; DLAB BIT OFF
UART_OUT(UART_LCR) ; OUTPUT TO LCR (DLAB REGS NOW INACTIVE)
UART_IN(UART_IER) ; READ IER
CP $5A ; CHECK FOR TEST VALUE
JR Z,UART_DETECT_NONE ; IF STILL $5A, UNKNOWN OR NOT PRESENT
;
; TEST FOR FUNCTIONAL SCRATCH REG, IF NOT, WE HAVE AN 8250
LD A,$5A ; LOAD TEST VALUE
UART_OUT(UART_SCR) ; PUT IT IN SCRATCH REGISTER
UART_IN(UART_SCR) ; READ IT BACK
CP $5A ; CHECK IT
JR NZ,UART_DETECT_8250 ; STUPID 8250
;
; TEST FOR EFR REGISTER WHICH IMPLIES 16650/850
LD A,$BF ; VALUE TO ENABLE EFR
UART_OUT(UART_LCR) ; WRITE IT TO LCR
UART_IN(UART_SCR) ; READ SCRATCH REGISTER
CP $5A ; SPR STILL THERE?
JR NZ,UART_DETECT1 ; NOPE, HIDDEN, MUST BE 16650/850
;
; RESET LCR TO DEFAULT
XOR A ; ZERO ACCUM
UART_OUT(UART_LCR) ; RESET LCR
;
; TEST FCR TO ISOLATE 16450/550/550A
LD A,$E7 ; TEST VALUE
UART_OUT(UART_FCR) ; PUT IT IN FCR
UART_IN(UART_IIR) ; READ BACK FROM IIR
BIT 6,A ; BIT 6 IS FIFO ENABLE, LO BIT
JR Z,UART_DETECT_16450 ; IF NOT SET, MUST BE 16450
BIT 7,A ; BIT 7 IS FIFO ENABLE, HI BIT
JR Z,UART_DETECT_16550 ; IF NOT SET, MUST BE 16550
BIT 5,A ; BIT 5 IS 64 BYTE FIFO
JR Z,UART_DETECT2 ; IF NOT SET, MUST BE 16550A/C
JR UART_DETECT_16750 ; ONLY THING LEFT IS 16750
;
UART_DETECT1: ; PICK BETWEEN 16650/850
; NEED TO RESET LCR
XOR A ; DLAB BIT OFF
UART_OUT(UART_LCR) ; OUTPUT TO LCR (DLAB REGS NOW INACTIVE)
; NOT SURE HOW TO DIFFERENTIATE 16650 FROM 16850 YET
JR UART_DETECT_16650 ; ASSUME 16650
RET
;
UART_DETECT2: ; PICK BETWEEN 16650A/C
; SET AFC BIT IN FCR
LD A,$20 ; SET AFC BIT, FCR:5
UART_OUT(UART_FCR) ; WRITE NEW FCR VALUE
;
; READ IT BACK, IF SET, WE HAVE 16550C
UART_IN(UART_FCR) ; READ BACK FCR
BIT 5,A ; CHECK AFC BIT
JR Z,UART_DETECT_16550A ; NOT SET, SO 16550A
JR UART_DETECT_16550C ; IS SET, SO 16550C
;
UART_DETECT_NONE:
LD A,UART_NONE
RET
;
UART_DETECT_8250:
LD A,UART_8250
RET
;
UART_DETECT_16450:
LD A,UART_16450
RET
;
UART_DETECT_16550:
LD A,UART_16550
RET
;
UART_DETECT_16550A:
LD A,UART_16550A
RET
;
UART_DETECT_16550C:
LD A,UART_16550C
RET
;
UART_DETECT_16650:
LD A,UART_16650
RET
;
UART_DETECT_16750:
LD A,UART_16750
RET
;
UART_DETECT_16850:
LD A,UART_16850
RET
;
; ROUTINES TO READ/WRITE PORTS INDIRECTLY
;
; READ VALUE OF UART PORT ON TOS INTO REGISTER A
;
UART_INP:
EX (SP),HL ; SWAP HL AND TOS
PUSH BC ; PRESERVE BC
LD A,(UART_BASE) ; GET UART IO BASE PORT
OR (HL) ; OR IN REGISTER ID BITS
LD C,A ; C := PORT
INC HL ; BUMP HL PAST REG ID PARM
IN A,(C) ; READ PORT INTO A
POP BC ; RESTORE BC
EX (SP),HL ; SWAP BACK HL AND TOS
RET
;
; WRITE VALUE IN REGISTER A TO UART PORT ON TOS
;
UART_OUTP:
EX (SP),HL ; SWAP HL AND TOS
PUSH BC ; PRESERVE BC
PUSH AF ; SAVE AF (VALUE TO WRITE)
LD A,(UART_BASE) ; GET UART IO BASE PORT
OR (HL) ; OR IN REGISTER ID BITS
LD C,A ; C := PORT
INC HL ; BUMP HL PAST REG ID PARM
POP AF ; RESTORE VALUE TO WRITE
OUT (C),A ; WRITE VALUE TO PORT
POP BC ; RESTORE BC
EX (SP),HL ; SWAP BACK HL AND TOS
RET
;
;
;
UART_TYPE_MAP:
.DW UART_STR_NONE
.DW UART_STR_8250
.DW UART_STR_16450
.DW UART_STR_16550
.DW UART_STR_16550A
.DW UART_STR_16550C
.DW UART_STR_16650
.DW UART_STR_16750
.DW UART_STR_16850
UART_STR_NONE .DB "<NOT PRESENT>$"
UART_STR_8250 .DB "8250$"
UART_STR_16450 .DB "16450$"
UART_STR_16550 .DB "16550$"
UART_STR_16550A .DB "16550A$"
UART_STR_16550C .DB "16550C$"
UART_STR_16650 .DB "16650$"
UART_STR_16750 .DB "16750$"
UART_STR_16850 .DB "16850$"
;
; WORKING VARIABLES
;
UART_BASE .DB 0 ; BASE IO ADDRESS FOR ACTIVE UART
UART_TYPE .DB 0 ; UART TYPE DISCOVERED
UART_FEAT .DB 0 ; UART FEATURES DISCOVERED
UART_BAUD .DW 0 ; BAUD RATE
UART_DIV .DW 0 ; BAUD DIVISOR
UART_FUNC .DB 0 ; UART FUNCTIONS REQUESTED
;
;
;
UART_FIFO .EQU 0 ; FIFO ENABLE BIT
UART_AFC .EQU 1 ; AUTO FLOW CONTROL ENABLE BIT

4
Source/ver.inc
View File

@ -1,6 +1,6 @@
#DEFINE RMJ 2
#DEFINE RMN 5
#DEFINE RUP 0
#DEFINE RTP 12
#DEFINE BIOSVER "2.5 - Beta 12"
#DEFINE RTP 13
#DEFINE BIOSVER "2.5 - Beta 13"
#DEFINE REVISION 412

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