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Preliminary Support for MBC 

- Added new memory manager to support Andrew Lynch's MBC system.
patch
Wayne Warthen 5 years ago
parent
e463959fee
commit
86e55f7968
21 changed files with 101 additions and 32 deletions
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  1. 1
      Doc/ChangeLog.txt
  2. 33
      Source/HBIOS/Config/SBC_mbc.asm
  3. 3
      Source/HBIOS/Makefile
  4. 4
      Source/HBIOS/cfg_dyno.asm
  5. 4
      Source/HBIOS/cfg_ezz80.asm
  6. 4
      Source/HBIOS/cfg_master.asm
  7. 4
      Source/HBIOS/cfg_mk4.asm
  8. 4
      Source/HBIOS/cfg_n8.asm
  9. 4
      Source/HBIOS/cfg_rcz180.asm
  10. 4
      Source/HBIOS/cfg_rcz280.asm
  11. 4
      Source/HBIOS/cfg_rcz80.asm
  12. 4
      Source/HBIOS/cfg_sbc.asm
  13. 4
      Source/HBIOS/cfg_scz180.asm
  14. 2
      Source/HBIOS/cfg_una.asm
  15. 4
      Source/HBIOS/cfg_zeta.asm
  16. 4
      Source/HBIOS/cfg_zeta2.asm
  17. 35
      Source/HBIOS/hbios.asm
  18. 1
      Source/HBIOS/std.asm
  19. 6
      Source/HBIOS/tms.asm
  20. 2
      Source/ver.inc
  21. 2
      Source/ver.lib

1
Doc/ChangeLog.txt
View File

@ -35,6 +35,7 @@ Version 3.1.1
- D?N: Added support for RP5C01 RTC
- L?N: Slightly enhanced ZCPRD&J w/ a couple bug fixes
- L?N: UNZIPZ4 which handles most modern ZIP file compression algorithms
- AJL: Preliminary support for MBC systems
Version 3.1
-----------

33
Source/HBIOS/Config/SBC_mbc.asm
View File

@ -0,0 +1,33 @@
;
;==================================================================================================
; MBC CONFIGURATION
;==================================================================================================
;
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
; YOUR FILE IN THE BUILD PROCESS.
;
; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
; SETTINGS.
;
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
;
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
; DIRECTORIES ABOVE THIS ONE).
;
#DEFINE PLATFORM_NAME "SBC"
#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
;
#include "cfg_sbc.asm"
;
INTMODE .SET 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
MEMMGR .SET MM_MBC ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
;
PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)

3
Source/HBIOS/Makefile
View File

@ -22,8 +22,9 @@ else
OBJECTS += RCZ80_std.rom RCZ80_std.com RCZ80_std.upd
OBJECTS += RCZ80_skz.rom RCZ80_skz.com RCZ80_skz.upd
OBJECTS += RCZ80_zrc.rom RCZ80_zrc.com RCZ80_zrc.upd
OBJECTS += SBC_simh.rom SBC_simh.com SBC_simh.upd
OBJECTS += SBC_std.rom SBC_std.com SBC_std.upd
OBJECTS += SBC_simh.rom SBC_simh.com SBC_simh.upd
OBJECTS += SBC_mbc.rom SBC_mbc.com SBC_mbc.upd
OBJECTS += SCZ180_126.rom SCZ180_126.com SCZ180_126.upd
OBJECTS += SCZ180_130.rom SCZ180_130.com SCZ180_130.upd
OBJECTS += SCZ180_131.rom SCZ180_131.com SCZ180_131.upd

4
Source/HBIOS/cfg_dyno.asm
View File

@ -24,13 +24,13 @@ TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
;
CPUOSC .EQU 18432000 ; CPU OSC FREQ IN MHZ
INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
RAM_RESERVE .EQU 0 ; RESERVE FIRST N KB OF RAM (USUALLY 0)
ROM_RESERVE .EQU 0 ; RESERVE FIRST N KB OR ROM (USUALLY 0)
MEMMGR .EQU MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
MEMMGR .EQU MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
RAMLOC .EQU 19 ; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
RAMBIAS .EQU (1 << (RAMLOC - 10)) ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)

4
Source/HBIOS/cfg_ezz80.asm
View File

@ -24,13 +24,13 @@ TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
;
CPUOSC .EQU 10000000 ; CPU OSC FREQ IN MHZ
INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
DEFSERCFG .EQU SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
RAM_RESERVE .EQU 0 ; RESERVE FIRST N KB OF RAM (USUALLY 0)
ROM_RESERVE .EQU 0 ; RESERVE FIRST N KB OR ROM (USUALLY 0)
MEMMGR .EQU MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
MEMMGR .EQU MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
MPGSEL_1 .EQU $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)

4
Source/HBIOS/cfg_master.asm
View File

@ -21,13 +21,13 @@ TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
;
CPUOSC .EQU 8000000 ; CPU OSC FREQ IN MHZ
INTMODE .EQU 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
INTMODE .EQU 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
RAM_RESERVE .EQU 0 ; RESERVE FIRST N KB OF RAM (USUALLY 0)
ROM_RESERVE .EQU 0 ; RESERVE FIRST N KB OR ROM (USUALLY 0)
MEMMGR .EQU MM_NONE ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
MEMMGR .EQU MM_NONE ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
RAMLOC .EQU 19 ; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
RAMBIAS .EQU (1 << (RAMLOC - 10)) ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
MPCL_RAM .EQU $78 ; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)

4
Source/HBIOS/cfg_mk4.asm
View File

@ -24,13 +24,13 @@ TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
;
CPUOSC .EQU 18432000 ; CPU OSC FREQ IN MHZ
INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
RAM_RESERVE .EQU 0 ; RESERVE FIRST N KB OF RAM (USUALLY 0)
ROM_RESERVE .EQU 0 ; RESERVE FIRST N KB OR ROM (USUALLY 0)
MEMMGR .EQU MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
MEMMGR .EQU MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
RAMLOC .EQU 19 ; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
RAMBIAS .EQU (1 << (RAMLOC - 10)) ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
;

4
Source/HBIOS/cfg_n8.asm
View File

@ -24,13 +24,13 @@ TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
;
CPUOSC .EQU 18432000 ; CPU OSC FREQ IN MHZ
INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
RAM_RESERVE .EQU 0 ; RESERVE FIRST N KB OF RAM (USUALLY 0)
ROM_RESERVE .EQU 0 ; RESERVE FIRST N KB OR ROM (USUALLY 0)
MEMMGR .EQU MM_N8 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
MEMMGR .EQU MM_N8 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
RAMBIAS .EQU 0 ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
RAMLOC .EQU 0 ; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
;

4
Source/HBIOS/cfg_rcz180.asm
View File

@ -24,13 +24,13 @@ TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
;
CPUOSC .EQU 18432000 ; CPU OSC FREQ IN MHZ
INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
DEFSERCFG .EQU SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
RAM_RESERVE .EQU 0 ; RESERVE FIRST N KB OF RAM (USUALLY 0)
ROM_RESERVE .EQU 0 ; RESERVE FIRST N KB OR ROM (USUALLY 0)
MEMMGR .EQU MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
MEMMGR .EQU MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
RAMLOC .EQU 19 ; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
RAMBIAS .EQU (1 << (RAMLOC - 10)) ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)

4
Source/HBIOS/cfg_rcz280.asm
View File

@ -24,13 +24,13 @@ TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
;
CPUOSC .EQU 24000000 ; CPU OSC FREQ IN MHZ
INTMODE .EQU 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
INTMODE .EQU 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
DEFSERCFG .EQU SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
RAM_RESERVE .EQU 0 ; RESERVE FIRST N KB OF RAM (USUALLY 0)
ROM_RESERVE .EQU 0 ; RESERVE FIRST N KB OR ROM (USUALLY 0)
MEMMGR .EQU MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
MEMMGR .EQU MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
RAMLOC .EQU 19 ; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
RAMBIAS .EQU (1 << (RAMLOC - 10)) ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)

4
Source/HBIOS/cfg_rcz80.asm
View File

@ -24,13 +24,13 @@ TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
;
CPUOSC .EQU 7372800 ; CPU OSC FREQ IN MHZ
INTMODE .EQU 1 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
INTMODE .EQU 1 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
DEFSERCFG .EQU SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
RAM_RESERVE .EQU 0 ; RESERVE FIRST N KB OF RAM (USUALLY 0)
ROM_RESERVE .EQU 0 ; RESERVE FIRST N KB OR ROM (USUALLY 0)
MEMMGR .EQU MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
MEMMGR .EQU MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
MPGSEL_1 .EQU $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)

4
Source/HBIOS/cfg_sbc.asm
View File

@ -24,13 +24,13 @@ TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
;
CPUOSC .EQU 8000000 ; CPU OSC FREQ IN MHZ
INTMODE .EQU 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
INTMODE .EQU 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
RAM_RESERVE .EQU 0 ; RESERVE FIRST N KB OF RAM (USUALLY 0)
ROM_RESERVE .EQU 0 ; RESERVE FIRST N KB OR ROM (USUALLY 0)
MEMMGR .EQU MM_SBC ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
MEMMGR .EQU MM_SBC ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
MPCL_RAM .EQU $78 ; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
MPCL_ROM .EQU $7C ; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
;

4
Source/HBIOS/cfg_scz180.asm
View File

@ -24,13 +24,13 @@ TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
;
CPUOSC .EQU 18432000 ; CPU OSC FREQ IN MHZ
INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
DEFSERCFG .EQU SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
RAM_RESERVE .EQU 0 ; RESERVE FIRST N KB OF RAM (USUALLY 0)
ROM_RESERVE .EQU 0 ; RESERVE FIRST N KB OR ROM (USUALLY 0)
MEMMGR .EQU MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
MEMMGR .EQU MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
RAMLOC .EQU 19 ; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
RAMBIAS .EQU (1 << (RAMLOC - 10)) ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
;

2
Source/HBIOS/cfg_una.asm
View File

@ -19,7 +19,7 @@ BIOS .EQU BIOS_UNA ; HARDWARE BIOS: BIOS_[WBW|UNA]
BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
;
CPUOSC .EQU 18432000 ; CPU OSC FREQ IN MHZ
INTMODE .EQU 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
INTMODE .EQU 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
RAM_RESERVE .EQU 0 ; RESERVE FIRST N KB OF RAM (USUALLY 0)

4
Source/HBIOS/cfg_zeta.asm
View File

@ -24,13 +24,13 @@ TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
;
CPUOSC .EQU 20000000 ; CPU OSC FREQ IN MHZ
INTMODE .EQU 0 ; INTERRUPT MODE: 0=NONE, 1=MODE 1, 2=MODE 2
INTMODE .EQU 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
RAM_RESERVE .EQU 0 ; RESERVE FIRST N KB OF RAM (USUALLY 0)
ROM_RESERVE .EQU 0 ; RESERVE FIRST N KB OR ROM (USUALLY 0)
MEMMGR .EQU MM_SBC ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
MEMMGR .EQU MM_SBC ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
MPCL_RAM .EQU $78 ; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
MPCL_ROM .EQU $7C ; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
;

4
Source/HBIOS/cfg_zeta2.asm
View File

@ -24,13 +24,13 @@ TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
;
CPUOSC .EQU 20000000 ; CPU OSC FREQ IN MHZ
INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
RAM_RESERVE .EQU 0 ; RESERVE FIRST N KB OF RAM (USUALLY 0)
ROM_RESERVE .EQU 0 ; RESERVE FIRST N KB OR ROM (USUALLY 0)
MEMMGR .EQU MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
MEMMGR .EQU MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
MPGSEL_1 .EQU $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)

35
Source/HBIOS/hbios.asm
View File

@ -116,8 +116,6 @@ MODCNT .SET MODCNT + 1
#IF (INTMODE == 3)
; Z280 MODE 3 INTERRUPT HANDLING (INTA, C/T 0, & UART RCVR ENABLED)
#DEFINE HB_DI DI
;#DEFINE HB_DI .DB $ED,$77,$7F
;#DEFINE HB_EI EI
#DEFINE HB_EI .DB $ED,$7F,$0B
#ELSE
; Z280 MODE 1/2 INTERRUPT HANDLING
@ -486,6 +484,39 @@ HBX_ROM:
RET ; DONE
#ENDIF
;
#IF (MEMMGR == MM_MBC)
;
#IF (INTMODE == 1)
LD (HBX_MMA),A ; SAVE ACCUM
LD A,I ; GET INT CTL REG
HB_DI ; DISABLE INTS
PUSH AF ; SAVE INT CTL REG
LD A,(HBX_MMA) ; RESTORE ACCUM
#ENDIF
;
OR A ; SET FLAGS
JP P,HBX_ROM ; BIT 7 INDICATES RAM
OUT (MPCL_ROM),A ; ENSURE ROM PAGE OUT OF MEMORY BEFORE SWITCH
OUT (MPCL_RAM),A ; SET RAM PAGE SELECTOR
JR HBX_RAMX
HBX_ROM:
OUT (MPCL_RAM),A ; ENSURE RAM PAGE OUT OF MEMORY BEFORE SWITCH
OUT (MPCL_ROM),A ; SET ROM PAGE SELECTOR
HBX_RAMX:
;
#IF (INTMODE == 1)
POP AF ; RESTORE INT CTL REG
JP PO,$+4 ; WERE INTS DISABLED AT ENTRY?
EI ; *** DO NOT USE HB_EI HERE ***
LD A,(HBX_MMA) ; RESTORE INCOMING ACCUM
#ENDIF
;
RET
;
HBX_MMA .DB 0 ; TEMPORARY STORAGE FOR REG A
#ENDIF
;
;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
; Copy Data - Possibly between banks. This resembles CP/M 3, but
; usage of the HL and DE registers is reversed.

1
Source/HBIOS/std.asm
View File

@ -84,6 +84,7 @@ MM_N8 .EQU 3 ; Z180 CUSTOMIZED FOR N8 MEMORY EXTENSIONS
MM_Z180 .EQU 4 ; Z180 NATIVE MEMORY MANAGER
MM_Z280 .EQU 5 ; Z280 NATIVE MEMORY MANAGER
MM_ZRC .EQU 6 ; ZRC BANK SWITCHING
MM_MBC .EQU 7 ; MBC MEMORY MANAGER
;
; BOOT STYLE
;

6
Source/HBIOS/tms.asm
View File

@ -381,8 +381,8 @@ TMS_SET:
;
;----------------------------------------------------------------------
; SET TMS9918 READ/WRITE ADDRESS
; TMS_WR SETS TMS9918 TO BEGIN WRITING TO ADDRESS SPECIFIED IN HL
; TMS_RD SETS TMS9918 TO BEGIN READING TO ADDRESS SPECIFIED IN HL
; TMS_WR SETS TMS9918 TO BEGIN WRITING AT VDU ADDRESS SPECIFIED IN HL
; TMS_RD SETS TMS9918 TO BEGIN READING AT VDU ADDRESS SPECIFIED IN HL
;----------------------------------------------------------------------
;
TMS_WR:
@ -390,8 +390,10 @@ TMS_WR:
; CLEAR R#14 FOR V9958
XOR A
OUT (TMS_CMDREG), A
TMS_IODELAY
LD A, $80 | 14
OUT (TMS_CMDREG), A
TMS_IODELAY
#ENDIF
PUSH HL

2
Source/ver.inc
View File

@ -2,4 +2,4 @@
#DEFINE RMN 1
#DEFINE RUP 1
#DEFINE RTP 0
#DEFINE BIOSVER "3.1.1-pre.82"
#DEFINE BIOSVER "3.1.1-pre.83"

2
Source/ver.lib
View File

@ -3,5 +3,5 @@ rmn equ 1
rup equ 1
rtp equ 0
biosver macro
db "3.1.1-pre.82"
db "3.1.1-pre.83"
endm

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