From 8ad2bdbb29fc76ae7d1efa4d742ee5fc6f57c77e Mon Sep 17 00:00:00 2001 From: Wayne Warthen Date: Fri, 17 Apr 2020 11:25:28 -0700 Subject: [PATCH] SIO driver now CTC aware The SIO driver can now use a CTC (if available) to provide much more flexible baud rate programming. --- Doc/ChangeLog.txt | 1 + Doc/RomWBW Applications.pdf | Bin 140215 -> 140215 bytes Doc/RomWBW Architecture.pdf | Bin 371105 -> 371105 bytes Doc/RomWBW Getting Started.pdf | Bin 166095 -> 166096 bytes ReadMe.md | 4 +- ReadMe.txt | 4 +- Source/Doc/GettingStarted.md | 2 +- Source/HBIOS/Config/RCZ80_kio.asm | 5 +- Source/HBIOS/cfg_ezz80.asm | 14 +- Source/HBIOS/cfg_master.asm | 14 +- Source/HBIOS/cfg_rcz180.asm | 14 +- Source/HBIOS/cfg_rcz80.asm | 14 +- Source/HBIOS/cfg_sbc.asm | 10 +- Source/HBIOS/cfg_scz180.asm | 14 +- Source/HBIOS/sd.asm | 17 +- Source/HBIOS/sio.asm | 352 ++++++++++++++++++++---------- Source/HBIOS/std.asm | 8 +- Source/Images/Common/COMP.COM | Bin 0 -> 1024 bytes Source/Images/Common/COMPARE.COM | Bin 2560 -> 0 bytes Source/ver.inc | 2 +- Source/ver.lib | 2 +- 21 files changed, 291 insertions(+), 186 deletions(-) create mode 100644 Source/Images/Common/COMP.COM delete mode 100644 Source/Images/Common/COMPARE.COM diff --git a/Doc/ChangeLog.txt b/Doc/ChangeLog.txt index 8d28bd22..e177cbc8 100644 --- a/Doc/ChangeLog.txt +++ b/Doc/ChangeLog.txt @@ -6,6 +6,7 @@ Version 3.1 - WBW: Added support dual 16C550 UART on RC2014 platform - WBW: Made .com images smaller (contain only Z-System now) - WBW: Support automatic clock hardware detection and fallback +- WBW: Support use of CTC for SIO baud rate divisors Version 3.0.1 ------------- diff --git a/Doc/RomWBW Applications.pdf b/Doc/RomWBW Applications.pdf index ed1cd38b7583a0bc5acf95f7c116d582d8ea70c9..4fdbaee45f2fef4c43fd928b2e3d648a992e9479 100644 GIT binary patch delta 111 zcmdmfoMZcOj)pCa8o$_04J=Iz3=OC2|6-JZakdBjVr12HHn((ibTxA{G%z-HvM_cs fb}?|ZFm^UKv~aX=HFhyKuv4%hq-6RmWhPkw^PwFL delta 111 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z0g=FI(Y<9d&_GNWxRQJ@q$CnC4CCP`wjrNt?a#SOU5QdLqUH=T6;4&qhatm22_2SI(8@LtPz7Xw5gP_76yaht2mL6CG2p2Ifm%qLB$$V_fSns^0nUXvdjn~zg+Z+f zEEZ7125&G3vdaK1iGYN)xK)58S2HB6D^W5FO+Z5lVKIJK06r`XXqr$ztYy*Lrwnfw z4SfOh5BDH%0*e_mCjma3f}jJy2SX`rcoEf$3z|sD@KnYUB?=A(T#FV1wkK&Y?I!FA zl^dWq;$u+#1=LjwoY|jQT(ua7qUtLPv>_KeAP_o0k$iK2@D4`!pN zN0MO%g#ryCw>s*4 zXr1aYR`W^l(1K_%5<|3xlkNZ3!jlilCo>A_>|j2D0EH||!!+R&-rTUC2 zK1eM@U;s@Z2T4GaP&C7Y9%}{$$K*TqPh(OzS%rmBmpCZIz}=Ad)8N2_fB>BEj2>tRJb};{T&fBjscNWNWTJr= zUMRujsBnZYLy@V-UxvCyQ{`a%u1hiMUR78oow z2OtIs2&jSd84j8{(lI&c$4Q#PL3>K%Wte(lC*%M(U_JqV=9_tLl-7 z)B=1xKu)&divl#70U8*u_Tc|QmRI28BhrxoRv=%1PYB6D5zWJQUZht;RwgIqzz2wm zJQyB^RZch=a&(>g0cs+3u@aUVUeQUfhJ1 @@ -311,7 +311,7 @@ media. You can think of slices as a way to refer to any of the first 256 Of course, the problem is that CP/M-like operating systems have only 16 drive letters (A:-P:) available. Under the covers, RomWBW allows you to use any drive letter to refer to any slice of any media. The `ASSIGN` -command is allows you to view or change the drive letter mappings at any +command allows you to view or change the drive letter mappings at any time. At startup, the operating system will automatically allocate a reasonable number of drive letters to the available storage devices. The allocation will depend on the number of large storage devices available diff --git a/ReadMe.txt b/ReadMe.txt index f47dcf47..e0241d40 100644 --- a/ReadMe.txt +++ b/ReadMe.txt @@ -3,7 +3,7 @@ RomWBW Z80/Z180 System Software Version 3.1 Pre-release -Saturday 11 April 2020 +Wednesday 15 April 2020 Wayne Warthen wwarthen@gmail.com @@ -325,7 +325,7 @@ media. You can think of slices as a way to refer to any of the first 256 Of course, the problem is that CP/M-like operating systems have only 16 drive letters (A:-P:) available. Under the covers, RomWBW allows you to use any drive letter to refer to any slice of any media. The ASSIGN -command is allows you to view or change the drive letter mappings at any +command allows you to view or change the drive letter mappings at any time. At startup, the operating system will automatically allocate a reasonable number of drive letters to the available storage devices. The allocation will depend on the number of large storage devices available diff --git a/Source/Doc/GettingStarted.md b/Source/Doc/GettingStarted.md index 345c768b..a92b189a 100644 --- a/Source/Doc/GettingStarted.md +++ b/Source/Doc/GettingStarted.md @@ -346,7 +346,7 @@ the first 256 8MB chunks of space on a single media. Of course, the problem is that CP/M-like operating systems have only 16 drive letters (A:-P:) available. Under the covers, RomWBW allows you to use any drive letter to refer to any slice of any media. The -`ASSIGN` command is allows you to view or change the drive letter +`ASSIGN` command allows you to view or change the drive letter mappings at any time. At startup, the operating system will automatically allocate a reasonable number of drive letters to the available storage devices. The allocation will depend on the number of diff --git a/Source/HBIOS/Config/RCZ80_kio.asm b/Source/HBIOS/Config/RCZ80_kio.asm index a83052f4..91ef5e73 100644 --- a/Source/HBIOS/Config/RCZ80_kio.asm +++ b/Source/HBIOS/Config/RCZ80_kio.asm @@ -39,8 +39,9 @@ ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) ; SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) SIOCNT .SET 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP -SIO0MODE .SET SIOMODE_EZZ80 ; SIO 0: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80] +SIO0MODE .SET SIOMODE_STD ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP] SIO0BASE .SET KIOBASE+$08 ; SIO 0: REGISTERS BASE ADR -SIO0CTCC .SET 0 ; SIO 0: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE SIO0ACLK .SET 1843200 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO0ACTCC .SET 0 ; SIO 0A: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE SIO0BCLK .SET 1843200 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO0BCTCC .SET 1 ; SIO 0A: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE diff --git a/Source/HBIOS/cfg_ezz80.asm b/Source/HBIOS/cfg_ezz80.asm index 1c64c652..b7a190f8 100644 --- a/Source/HBIOS/cfg_ezz80.asm +++ b/Source/HBIOS/cfg_ezz80.asm @@ -86,24 +86,22 @@ ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) SIOENABLE .EQU TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP -SIO0MODE .EQU SIOMODE_EZZ80 ; SIO 0: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80] -SIO0CTCC .EQU -1 ; SIO 0: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE +SIO0MODE .EQU SIOMODE_STD ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP] SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR SIO0ACLK .EQU 1843200 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO0ADIV .EQU 1 ; SIO 0A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5) SIO0ACFG .EQU DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG +SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE SIO0BCLK .EQU 1843200 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO0BDIV .EQU 1 ; SIO 0B: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5) SIO0BCFG .EQU DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG -SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80] -SIO1CTCC .EQU -1 ; SIO 1: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE +SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE +SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP] SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR SIO1ACLK .EQU 7372800 ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO1ADIV .EQU 1 ; SIO 1A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5) SIO1ACFG .EQU DEFSERCFG ; SIO 1A: SERIAL LINE CONFIG +SIO1ACTCC .EQU -1 ; SIO 1A: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE SIO1BCLK .EQU 7372800 ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO1BDIV .EQU 1 ; SIO 1B: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5) SIO1BCFG .EQU DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG +SIO1BCTCC .EQU -1 ; SIO 1B: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE ; XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG ; diff --git a/Source/HBIOS/cfg_master.asm b/Source/HBIOS/cfg_master.asm index 55806745..b5f4ce33 100644 --- a/Source/HBIOS/cfg_master.asm +++ b/Source/HBIOS/cfg_master.asm @@ -121,24 +121,22 @@ ACIA1CFG .EQU DEFSERCFG ; ACIA 1: SERIAL LINE CONFIG (SEE STD.ASM) SIOENABLE .EQU FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP -SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80] -SIO0CTCC .EQU -1 ; SIO 0: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE +SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP] SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR SIO0ACLK .EQU CPUOSC ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO0ADIV .EQU 1 ; SIO 0A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5) SIO0ACFG .EQU DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG +SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE SIO0BCLK .EQU CPUOSC ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO0BDIV .EQU 1 ; SIO 0B: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5) SIO0BCFG .EQU DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG -SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80] -SIO1CTCC .EQU -1 ; SIO 1: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE +SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE +SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP] SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR SIO1ACLK .EQU CPUOSC ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO1ADIV .EQU 1 ; SIO 1A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5) SIO1ACFG .EQU DEFSERCFG ; SIO 1A: SERIAL LINE CONFIG +SIO1ACTCC .EQU -1 ; SIO 1A: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE SIO1BCLK .EQU CPUOSC ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO1BDIV .EQU 1 ; SIO 1B: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5) SIO1BCFG .EQU DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG +SIO1BCTCC .EQU -1 ; SIO 1B: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE ; XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG ; diff --git a/Source/HBIOS/cfg_rcz180.asm b/Source/HBIOS/cfg_rcz180.asm index ee65373f..746446f2 100644 --- a/Source/HBIOS/cfg_rcz180.asm +++ b/Source/HBIOS/cfg_rcz180.asm @@ -91,24 +91,22 @@ ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) SIOENABLE .EQU TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP -SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80] -SIO0CTCC .EQU -1 ; SIO 0: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE +SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP] SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR SIO0ACLK .EQU 7372800 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO0ADIV .EQU 1 ; SIO 0A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5) SIO0ACFG .EQU SER_115200_8N1 ; SER_115200_8N1 0A: SERIAL LINE CONFIG +SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE SIO0BCLK .EQU 7372800 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO0BDIV .EQU 1 ; SIO 0B: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5) SIO0BCFG .EQU SER_115200_8N1 ; SIO 0B: SERIAL LINE CONFIG -SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80] -SIO1CTCC .EQU -1 ; SIO 1: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE +SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE +SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP] SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR SIO1ACLK .EQU 7372800 ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO1ADIV .EQU 1 ; SIO 1A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5) SIO1ACFG .EQU SER_115200_8N1 ; SER_115200_8N1 1A: SERIAL LINE CONFIG +SIO1ACTCC .EQU -1 ; SIO 1A: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE SIO1BCLK .EQU 7372800 ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO1BDIV .EQU 1 ; SIO 1B: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5) SIO1BCFG .EQU SER_115200_8N1 ; SIO 1B: SERIAL LINE CONFIG +SIO1BCTCC .EQU -1 ; SIO 1B: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE ; XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG ; diff --git a/Source/HBIOS/cfg_rcz80.asm b/Source/HBIOS/cfg_rcz80.asm index 40b3d129..971216b3 100644 --- a/Source/HBIOS/cfg_rcz80.asm +++ b/Source/HBIOS/cfg_rcz80.asm @@ -95,24 +95,22 @@ ACIA1CFG .EQU DEFSERCFG ; ACIA 1: SERIAL LINE CONFIG (SEE STD.ASM) SIOENABLE .EQU TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP -SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80] -SIO0CTCC .EQU -1 ; SIO 0: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE +SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP] SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR SIO0ACLK .EQU CPUOSC ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO0ADIV .EQU 1 ; SIO 0A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5) SIO0ACFG .EQU DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG +SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE SIO0BCLK .EQU CPUOSC ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO0BDIV .EQU 1 ; SIO 0B: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5) SIO0BCFG .EQU DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG -SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80] -SIO1CTCC .EQU -1 ; SIO 1: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE +SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE +SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP] SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR SIO1ACLK .EQU CPUOSC ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO1ADIV .EQU 1 ; SIO 1A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5) SIO1ACFG .EQU DEFSERCFG ; SIO 1A: SERIAL LINE CONFIG +SIO1ACTCC .EQU -1 ; SIO 1A: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE SIO1BCLK .EQU CPUOSC ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO1BDIV .EQU 1 ; SIO 1B: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5) SIO1BCFG .EQU DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG +SIO1BCTCC .EQU -1 ; SIO 1B: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE ; XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG ; diff --git a/Source/HBIOS/cfg_sbc.asm b/Source/HBIOS/cfg_sbc.asm index e451213d..0121cce9 100644 --- a/Source/HBIOS/cfg_sbc.asm +++ b/Source/HBIOS/cfg_sbc.asm @@ -88,15 +88,15 @@ ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) SIOENABLE .EQU TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT SIOCNT .EQU 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP -SIO0MODE .EQU SIOMODE_ZP ; SIO 0: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80] +SIO0MODE .EQU SIOMODE_ZP ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP] SIO0CTCC .EQU -1 ; SIO 0: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE SIO0BASE .EQU $B0 ; SIO 0: REGISTERS BASE ADR -SIO0ACLK .EQU 4915200 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO0ADIV .EQU 8 ; SIO 0A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5) +SIO0ACLK .EQU (4915200/8) ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 SIO0ACFG .EQU DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG -SIO0BCLK .EQU 4915200 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO0BDIV .EQU 8 ; SIO 0B: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5) +SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE +SIO0BCLK .EQU (4915200/8) ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 SIO0BCFG .EQU DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG +SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE ; XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG ; diff --git a/Source/HBIOS/cfg_scz180.asm b/Source/HBIOS/cfg_scz180.asm index a92c4105..cc92824b 100644 --- a/Source/HBIOS/cfg_scz180.asm +++ b/Source/HBIOS/cfg_scz180.asm @@ -86,24 +86,22 @@ ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) SIOENABLE .EQU TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP -SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80] -SIO0CTCC .EQU -1 ; SIO 0: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE +SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP] SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR SIO0ACLK .EQU 7372800 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO0ADIV .EQU 1 ; SIO 0A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5) SIO0ACFG .EQU SER_115200_8N1 ; SIO 0A: SERIAL LINE CONFIG +SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE SIO0BCLK .EQU 7372800 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO0BDIV .EQU 1 ; SIO 0B: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5) SIO0BCFG .EQU SER_115200_8N1 ; SIO 0B: SERIAL LINE CONFIG -SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80] -SIO1CTCC .EQU -1 ; SIO 1: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE +SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE +SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP] SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR SIO1ACLK .EQU 7372800 ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO1ADIV .EQU 1 ; SIO 1A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5) SIO1ACFG .EQU SER_115200_8N1 ; SIO 1A: SERIAL LINE CONFIG +SIO1ACTCC .EQU -1 ; SIO 1A: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE SIO1BCLK .EQU 7372800 ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO1BDIV .EQU 1 ; SIO 1B: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5) SIO1BCFG .EQU SER_115200_8N1 ; SIO 1B: SERIAL LINE CONFIG +SIO1BCTCC .EQU -1 ; SIO 1B: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE ; XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG ; diff --git a/Source/HBIOS/sd.asm b/Source/HBIOS/sd.asm index b0b2e379..ef187081 100644 --- a/Source/HBIOS/sd.asm +++ b/Source/HBIOS/sd.asm @@ -41,7 +41,7 @@ ; THE CLOCK IS LOW. THE DATA IS CAPTURED ON THE CLOCK'S LOW-TO-HIGH ; TRANSITION AND PROPAGATED ON HIGH-TO-LOW CLOCK TRANSITION. ; -; NOTE: THE CSIO IMPLEMENTATION (INCLUDE MK4) USES SPI MODE 4 +; NOTE: THE CSIO IMPLEMENTATION (INCLUDE MK4) USES SPI MODE 3 ; (CPOL=1, CPHA=1) BECAUSE THAT IS THE WAY THAT THE Z180 CSIO ; INTERFACE WORKS. ALL OF THE CLOCK TRANSITIONS LISTED ABOVE ; ARE REVERSED FOR CSIO. @@ -104,7 +104,7 @@ ; IS FLOATING IT IS IMPOSSIBLE TO DETERMINE IF THE BYTE RECEIVED IS A FILL ; BYTE OR NOT. BASED ON WHAT I HAVE READ, THERE WILL ALWAYS BE AT LEAST ; ONE FILL BYTE PRIOR TO THE ACTUAL RESULT. ADDITIONALLY, THE SD CARD WILL -; START DRIVING MISO SOMETIME WITHING THAT FIRST FILL BYTE. SO, WE NOW +; START DRIVING MISO SOMETIME WITHIN THAT FIRST FILL BYTE. SO, WE NOW ; JUST DISCARD THE FIRST BYTE RECEIVED AFTER A COMMAND IS SENT WITH THE ; ASSUMPTION THAT IT MUST BE A FILL BYTE AND IS NOT RELIABLE DUE TO FLOATING ; MISO. @@ -1025,6 +1025,7 @@ SD_INITCARD5: ; PER SPEC, THE CARD SHOULD NOW BE ABLE TO HANDLE FULL SPEED OPERATION ; SO, FOR CSIO OPERATION, WE SET CSIO TO MAXIMUM SPEED CALL SD_WAITTX ; MAKE SURE WE ARE DONE SENDING + CALL DLY4 ; WAIT A BIT MORE FOR FINAL BIT XOR A ; ZERO MEANS MAX SPEED OUT (Z180_CNTR),A ; NOW SET CSIO PORT #ENDIF @@ -1703,19 +1704,19 @@ SD_DESELECT: ; ; CSIO WAIT FOR TRANSMIT READY (TX REGSITER EMPTY) ; -SD_WAITTX: ; WAIT FOR TX EMPTY +SD_WAITTX: IN0 A,(SD_CNTR) ; GET CSIO STATUS BIT 4,A ; TX EMPTY? - JR NZ,SD_WAITTX - RET + JR NZ,SD_WAITTX ; LOOP WHILE BUSY + RET ; DONE ; ; CSIO WAIT FOR RECEIVER READY (BYTE AVAILABLE) ; SD_WAITRX: IN0 A,(SD_CNTR) ; WAIT FOR RECEIVER TO FINISH - BIT 5,A - JR NZ,SD_WAITRX - RET + BIT 5,A ; RX EMPTY? + JR NZ,SD_WAITRX ; LOOP WHILE BUSY + RET ; DONE ; #ENDIF ; diff --git a/Source/HBIOS/sio.asm b/Source/HBIOS/sio.asm index 31000849..ae4129df 100644 --- a/Source/HBIOS/sio.asm +++ b/Source/HBIOS/sio.asm @@ -39,6 +39,13 @@ SIO1_VEC .EQU VEC(INT_SIO1) ; #ENDIF ; +#IF (SIO0MODE == SIOMODE_STD) +SIO0A_CMD .EQU SIO0BASE + $01 +SIO0A_DAT .EQU SIO0BASE + $00 +SIO0B_CMD .EQU SIO0BASE + $03 +SIO0B_DAT .EQU SIO0BASE + $02 +#ENDIF +; #IF (SIO0MODE == SIOMODE_RC) SIO0A_CMD .EQU SIO0BASE + $00 SIO0A_DAT .EQU SIO0BASE + $01 @@ -60,15 +67,15 @@ SIO0B_CMD .EQU SIO0BASE + $07 SIO0B_DAT .EQU SIO0BASE + $05 #ENDIF ; -#IF (SIO0MODE == SIOMODE_EZZ80) -SIO0A_CMD .EQU SIO0BASE + $01 -SIO0A_DAT .EQU SIO0BASE + $00 -SIO0B_CMD .EQU SIO0BASE + $03 -SIO0B_DAT .EQU SIO0BASE + $02 -#ENDIF -; #IF (SIOCNT >= 2) ; +#IF (SIO1MODE == SIOMODE_STD) +SIO1A_CMD .EQU SIO1BASE + $01 +SIO1A_DAT .EQU SIO1BASE + $00 +SIO1B_CMD .EQU SIO1BASE + $03 +SIO1B_DAT .EQU SIO1BASE + $02 +#ENDIF +; #IF (SIO1MODE == SIOMODE_RC) SIO1A_CMD .EQU SIO1BASE + $00 SIO1A_DAT .EQU SIO1BASE + $01 @@ -90,13 +97,6 @@ SIO1B_CMD .EQU SIO1BASE + $07 SIO1B_DAT .EQU SIO1BASE + $05 #ENDIF ; -#IF (SIO1MODE == SIOMODE_EZZ80) -SIO1A_CMD .EQU SIO1BASE + $01 -SIO1A_DAT .EQU SIO1BASE + $00 -SIO1B_CMD .EQU SIO1BASE + $03 -SIO1B_DAT .EQU SIO1BASE + $02 -#ENDIF -; #ENDIF ; SIO_PREINIT: @@ -158,44 +158,6 @@ SIO_PREINIT2: ; #ENDIF ; -; FOR NOW, THIS IS SPECIFICALLY FOR A CTC TO DRIVE AN SIO -; AT 1:1 USING CTC CHANNELS A & B. IN OTHER WORDS, IT JUST -; PASSES THE INCOMING TRIGGER OUT AT 1:1. -; -#IF (SIOCNT >= 1) - #IF (SIO0CTCC >= 0) - LD A,%01010111 ; CTCC CONTROL WORD VALUE - ; |||||||+-- 1=CONTROL WORD FLAG - ; ||||||+--- 1=SOFTWARE RESET - ; |||||+---- 1=TIME CONSTANT FOLLOWS - ; ||||+----- 0=AUTO TRIGGER WHEN TIME CONST LOADED - ; |||+------ 1=RISING EDGE TRIGGER - ; ||+------- 0=PRESCALER OF 16 (NOT USED) - ; |+-------- 1=COUNTER MODE - ; +--------- 0=NO INTERRUPTS - OUT (CTCA + SIO0CTCC),A ; SETUP CTCC - LD A,1 ; CTC TIMER CONSTANT = 1 - OUT (CTCA + SIO0CTCC),A ; SETUP CTC TIMER CONSTANT - #ENDIF -#ENDIF -; -#IF (SIOCNT >= 2) - #IF (SIO1CTCC >= 0) - LD A,%01010111 ; CTCC CONTROL WORD VALUE - ; |||||||+-- 1=CONTROL WORD FLAG - ; ||||||+--- 1=SOFTWARE RESET - ; |||||+---- 1=TIME CONSTANT FOLLOWS - ; ||||+----- 0=AUTO TRIGGER WHEN TIME CONST LOADED - ; |||+------ 1=RISING EDGE TRIGGER - ; ||+------- 0=PRESCALER OF 16 (NOT USED) - ; |+-------- 1=COUNTER MODE - ; +--------- 0=NO INTERRUPTS - OUT (CTCA + SIO1CTCC),A ; SETUP CTCC - LD A,1 ; CTC TIMER CONSTANT = 1 - OUT (CTCA + SIO1CTCC),A ; SETUP CTC TIMER CONSTANT - #ENDIF -#ENDIF -; SIO_PREINIT3: XOR A ; SIGNAL SUCCESS RET ; AND RETURN @@ -538,72 +500,195 @@ SIO_INITDEV1: CALL PRTHEXWORD #ENDIF ; - LD A,E ; GET CONFIG LSB - AND $E0 ; CHECK FOR DTR, XON, PARITY=MARK/SPACE - JR NZ,SIO_INITFAIL ; IF ANY BIT SET, FAIL, NOT SUPPORTED + PUSH DE ; SAVE TARGET CONFIG +; + ; WE WANT TO DETERMINE A DIVISOR FOR THE SIO CLOCK + ; THAT RESULTS IN THE DESIRED BAUD RATE. + ; BAUD RATE = SIO CLK / DIVISOR, OR TO SOLVE FOR DIVISOR + ; DIVISOR = SIO CLK / BAUDRATE. + ; TAKE ADVANTAGE OF ENCODED BAUD RATES ALWAYS BEING A FACTOR OF 75. + ; SO, WE CAN USE (SIO OSC / 75) / (BAUDRATE / 75) +; + ; GET SERIAL CLOCK VALUE AND DIVIDE IT BY 75 + PUSH IY ; GET CONFIG TABLE ENTRY PTR + POP HL ; MOVE TO HL + LD A,9 ; OFFSET TO CLK VALUE + CALL ADDHLA ; HL IS NOW PTR TO 32 BIT CLK + CALL LD32 ; LOAD DE:HL W/ RAW CLK VAL + LD C,75 ; DIVIDE BY 75 LIKE BAUD RATE + CALL DIV32X8 ; HL NOW HAS (CLK / 75) +; + #IF (SIODEBUG) + PRTS(" CLK75=$") + CALL PRTHEX32 + #ENDIF +; + ; SCALE DOWN THE 32 BIT VALUE TO FIT IN 16 BITS KEEPING + ; TRACK OF THE NUMBER OF BITS SHIFTED OUT IN B + LD B,0 +SIO_INITDEV1A: + LD A,D + OR E + JR Z,SIO_INITDEV1B + SRL D + RR E + RR H + RR L + INC B + JR SIO_INITDEV1A +SIO_INITDEV1B: +; + #IF (SIODEBUG) + PRTS(" CLK=$") + CALL PRTHEX32 + #ENDIF ; + POP DE ; RECOVER INCOMING TARGET CFG + PUSH DE ; RESAVE IT + PUSH HL ; SAVE CLK VALUE + PUSH BC ; SAVE BITS SHIFTED + + ; NOW DECODE THE BAUDRATE, BUT WE USE A CONSTANT OF 1 INSTEAD + ; OF THE NORMAL 75. THIS PRODUCES (BAUDRATE / 75). LD A,D ; GET CONFIG MSB AND $1F ; ISOLATE ENCODED BAUD RATE + LD L,A ; PUT IN L + LD H,0 ; H IS ALWAYS ZERO + LD DE,1 ; USE 1 FOR ENCODING CONSTANT + CALL DECODE ; DE:HL := BAUD RATE, ERRORS IGNORED +; + #IF (SIODEBUG) + PRTS(" BAUD75=$") + CALL PRTHEX32 + #ENDIF +; + ; SCALE DOWN CLK BY SAME AMOUNT AS BAUD RATE + POP BC ; RESTORE BITS TO SHIFT + LD A,B + OR A + JR Z,SIO_INITDEV1D +SIO_INITDEV1C: + SRL D + RR E + RR H + RR L + DJNZ SIO_INITDEV1C +SIO_INITDEV1D: +; + #IF (SIODEBUG) + PRTS(" BAUD=$") + CALL PRTHEX32 + #ENDIF +; + POP DE ; RECOVER CLOCK + EX DE,HL ; SWAP CLOCK & BAUD FOR DIV + ; *** HANDLE DIVIDE BY ZERO??? *** + CALL DIV16 ; BC := HL/DE == TARGET DIVISOR ; -#IF (SIODEBUG) - PRTS(" ENC=$") + #IF (SIODEBUG) + PRTS(" DIV=$") + CALL PRTHEXWORD + #ENDIF +; + ; NOW THAT WE HAVE THE TARGET BAUD RATE DIVISOR, WE WILL + ; ATTEMPT TO IMPLEMENT IT. THE SIO ITSELF CAN APPLY + ; A DIVISOR OF 1, 16, 32, OR 64. IF A CTC CHANNEL IS + ; CONFIGURED FOR THIS SERIAL PORT, THEN WE CAN ADDITIONALLY + ; APPLY A SCALER OF 1-256. +; + ; WE START BY DETERMINING THE MAXIMUM POSSIBLE SIO + ; SCALING. +; + ; WARNING: IF THE INCOMING SIO CLOCK IS THE SAME AS THE + ; CPU CLOCK AND WE USE THE 1:1 DIVISOR, THE SIO WILL NOT + ; WORK WELL. +; + PUSH BC ; MOVE WORKING DIVISOR VALUE + POP HL ; ... TO HL + LD A,L ; LOAD LSB OF DIVISOR + LD BC,$0004 ; SHIFT 0 BITS / SIO WR4 DIV 1 + LD A,L ; LOAD LSB OF DIVISOR + AND %00001111 ; DIV 16 POSSIBLE? + JR NZ,SIO_INITDEV2 ; NOPE, DONE TRYING + LD BC,$0444 ; SHIFT 4 BITS / SIO WR4 DIV 16 + LD A,L ; LOAD LSB OF DIVISOR + AND %00011111 ; DIV 32 POSSIBLE? + JR NZ,SIO_INITDEV2 ; NOPE, DONE TRYING + LD BC,$0584 ; SHIFT 5 BITS / SIO WR4 DIV 32 + LD A,L ; LOAD LSB OF DIVISOR + AND %00111111 ; DIV 32 POSSIBLE? + JR NZ,SIO_INITDEV2 ; NOPE, DONE TRYING + LD BC,$06C4 ; SHIFT 6 BITS / SIO WR4 DIV 64 +; + ; NOW APPLY THE SIO DIVISOR TO THE WORKING DIVISOR + ; AND SAVE THE RESULTANT SIO REGISTER VALUE TO APPLY LATER. +SIO_INITDEV2: + ; SHIFT BITS + XOR A ; ZERO ACCUM + OR B ; ZERO BITS TO SHIFT? + JR Z,SIO_INITDEV4 ; BYPASS SHIFTING IF SO +SIO_INITDEV3: + RR H ; SHIFT HL RIGHT BY + RR L ; ONE BIT + DJNZ SIO_INITDEV3 ; UNTIL ALL BITS DONE +SIO_INITDEV4: + LD B,C ; MOVE SIO WR4 VALUE TO B +; + POP DE ; RESTORE DE = SERIAL CONFIG +; + #IF (SIODEBUG) + PUSH BC + PUSH HL + POP BC + PRTS(" CTCDIV=$") + CALL PRTHEXWORD + POP BC + #ENDIF +; +#IF (CTCENABLE) + LD A,(IY+13) ; GET CTC CHANNEL + INC A ; $FF -> 0 + JR Z,SIO_NOCTC ; NO CTC CHANNEL, BYPASS +; + ; HL HAS THE DIVISOR THAT WE WANT TO PROGRAM INTO THE + ; DESIGNATED CTC CHANNEL. HOWEVER, THE CTC REGISTER IS ONE + ; BYTE. A VALUE OF 0 MEANS 256. SO WE NEED TO VALIDATE + ; THAT HL IS BETWEEN 1 AND 256. + DEC HL ; 1-256 -> 0-255 + LD A,H ; MSB NOW MUST BE ZERO + OR A ; SET FLAGS + JR NZ,SIO_INITFAIL ; IF ANY BIT SET, FAIL + INC HL ; RESTORE HL +; + ; ALL GOOD. PROGRAM THE CTC CHANNEL + LD A,(IY+13) ; GET CTC CHANNEL + ADD A,CTCA ; ADD TO CTC BASE PORT ADR + #IF (SIODEBUG) + PRTS(" CTC=$") CALL PRTHEXBYTE + #ENDIF + LD C,A ; AND PUT IN C FOR I/O + LD A,%01010111 ; CTCC CONTROL WORD VALUE + ; |||||||+-- 1=CONTROL WORD FLAG + ; ||||||+--- 1=SOFTWARE RESET + ; |||||+---- 1=TIME CONSTANT FOLLOWS + ; ||||+----- 0=AUTO TRIGGER WHEN TIME CONST LOADED + ; |||+------ 1=RISING EDGE TRIGGER + ; ||+------- 0=PRESCALER OF 16 (NOT USED) + ; |+-------- 1=COUNTER MODE + ; +--------- 0=NO INTERRUPTS + OUT (C),A ; PREP CTC CHANNEL + OUT (C),L ; SET CTC TIMER CONSTANT + JR SIO_INITBROK ; AND REJOIN MAIN SETUP +; #ENDIF ; - PUSH DE ; SAVE REQUESTED CONFIG - LD L,(IY+9) ; LOAD CLK FREQ - LD H,(IY+10) ; ... INTO DE:HL - LD E,(IY+11) ; ... " - LD D,(IY+12) ; ... " - LD C,75 ; BAUD RATE ENCODING CONSTANT - CALL ENCODE ; C = TEST BAUD RATE (ENCODED) = BAUDTST - POP DE ; GET REQ CONFIG BACK, D = BAUDREQ -; - ; BIT 4 (DIV 3) OF BAUDREQ AND BAUDTST MUST MATCH! - LD A,C ; A = BAUDTST - XOR D ; XOR WITH BAUDREQ - BIT 4,A ; DO BIT 4 VALS MATCH? - JR NZ,SIO_INITFAIL ; IF NOT, BAIL OUT -; - LD A,C ; BAUDTST TO A - AND $0F ; ISOLATE DIV 2 BAUD BITS - LD C,A ; C = BAUDTST -; - LD A,D ; MSB W/ BAUD RATE TO A - AND $0F ; ISOLATE DIV 2 BAUD BITS - LD L,A ; L = BAUDREQ -; -; PUSH AF ; *DEBUG* -; CALL NEWLINE ; *DEBUG* -; LD A,L ; *DEBUG* -; CALL PRTHEXBYTE ; *DEBUG* -; LD A,C ; *DEBUG* -; CALL PRTHEXBYTE ; *DEBUG* -; CALL NEWLINE ; *DEBUG* -; POP AF ; *DEBUG* -; - LD A,C ; A = BAUDTST - LD B,$04 ; SIO R4 VAL FOR DIV 1 - CP L ; BAUDTST = BAUDREQ? - JR Z,SIO_INITBROK ; IF MATCH, WE ARE DONE -; - SUB 4 ; DIVIDE BY 16 (NOW DIV 16 TOT) - JR C,SIO_INITFAIL ; FAIL IF UNDERFLOW - LD B,$44 ; SIO R4 VAL FOR DIV 16 - CP L ; BAUDTST = BAUDREQ? - JR Z,SIO_INITBROK ; IF MATCH, WE ARE DONE -; - SUB 1 ; DIVIDE BY 2 (NOW DIV 32 TOT) - JR C,SIO_INITFAIL ; FAIL IF UNDERFLOW - LD B,$84 ; SIO R4 VAL FOR DIV 32 - CP L ; BAUDTST = BAUDREQ? - JR Z,SIO_INITBROK ; IF MATCH, WE ARE DONE -; - SUB 1 ; DIVIDE BY 2 (NOW DIV 64 TOT) - JR C,SIO_INITFAIL ; FAIL IF UNDERFLOW - LD B,$C4 ; SIO R4 VAL FOR DIV 64 - CP L ; BAUDTST = BAUDREQ? - JR Z,SIO_INITBROK ; IF MATCH, WE ARE DONE +SIO_NOCTC: + ; IF THERE IS NO CTC, THEN THE REMAINING DIVISOR + ; NEEDS TO BE EXACTLY 1 OR WE HAVE A PROBLEM. + LD A,L ; GET REMAINING DIVISOR + DEC A ; 1 -> 0 + JR Z,SIO_INITBROK ; FAIL IF NOT 1 ; SIO_INITFAIL: ; @@ -665,6 +750,28 @@ SIO_INITBROK: ; FAILS. ; SIO_INITSAFE: +; +#IF (CTCENABLE) +; + ; CHECK IF A CTC CHANNEL IS CONFIGURED + LD A,(IY+13) ; GET CTC CHANNEL + INC A ; $FF -> 0 + JR Z,SIO_INITSAFE2 ; NO CTC CHANNEL, BYPASS +; + ; IF A CTC CHANNEL IS CONFIGURED, PROGRAM IT FOR + ; SIMPLE 1:1 SCALING. + LD A,(IY+13) ; GET CTC CHANNEL + ADD A,CTCA ; ADD TO CTC BASE PORT ADR + LD C,A ; AND PUT IN C FOR I/O + LD A,%01010111 ; CTCC CONTROL WORD VALUE + OUT (C),A ; PREP CTC CHANNEL + LD A,1 ; TIMER CONSTANT IS 1 + OUT (C),A ; SET CTC TIMER CONSTANT +; +#ENDIF +; +SIO_INITSAFE2: + ; SETUP DEFAULT VALUES FOR SIO REGISTERS LD HL,SIO_INITDEFS LD DE,SIO_INITVALS LD BC,SIO_INITLEN @@ -764,7 +871,8 @@ SIO_INITLEN .EQU $ - SIO_INITVALS ; SIO_INITDEFS: .DB $00, $18 ; WR0: CHANNEL RESET CMD - .DB $04, $C4 ; WR4: CLK BAUD PARITY STOP BIT + ;.DB $04, $C4 ; WR4: CLK BAUD PARITY STOP BIT + .DB $04, $44 ; WR4: CLK BAUD PARITY STOP BIT .DB $01, SIO_WR1VAL ; WR1: INTERRUPT STYLE .DB $02, $00 ; WR2: IM2 VEC OFFSET .DB $03, $E1 ; WR3: 8 BIT RCV, CTS/DCD AUTO, RX ENABLE @@ -984,8 +1092,9 @@ SIO0A_CFG: .DB SIO0A_DAT ; DATA PORT .DW SIO0ACFG ; LINE CONFIGURATION .DW SIO0A_RCVBUF ; POINTER TO RCV BUFFER STRUCT - .DW (SIO0ACLK / SIO0ADIV) & $FFFF ; CLOCK FREQ AS - .DW (SIO0ACLK / SIO0ADIV) >> 16 ; ... DWORD VALUE + .DW SIO0ACLK & $FFFF ; CLOCK FREQ AS + .DW SIO0ACLK >> 16 ; ... DWORD VALUE + .DB SIO0ACTCC ; CTC CHANNEL ; SIO_CFGSIZ .EQU $ - SIO_CFG ; SIZE OF ONE CFG TABLE ENTRY ; @@ -998,8 +1107,9 @@ SIO0B_CFG: .DB SIO0B_DAT ; DATA PORT .DW SIO0BCFG ; LINE CONFIGURATION .DW SIO0B_RCVBUF ; POINTER TO RCV BUFFER STRUCT - .DW (SIO0BCLK / SIO0BDIV) & $FFFF ; CLOCK FREQ AS - .DW (SIO0BCLK / SIO0BDIV) >> 16 ; ... DWORD VALUE + .DW SIO0BCLK & $FFFF ; CLOCK FREQ AS + .DW SIO0BCLK >> 16 ; ... DWORD VALUE + .DB SIO0BCTCC ; CTC CHANNEL ; #IF (SIOCNT >= 2) ; @@ -1012,8 +1122,9 @@ SIO1A_CFG: .DB SIO1A_DAT ; DATA PORT .DW SIO1ACFG ; LINE CONFIGURATION .DW SIO1A_RCVBUF ; POINTER TO RCV BUFFER STRUCT - .DW (SIO1ACLK / SIO1ADIV) & $FFFF ; CLOCK FREQ AS - .DW (SIO1ACLK / SIO1ADIV) >> 16 ; ... DWORD VALUE + .DW SIO1ACLK & $FFFF ; CLOCK FREQ AS + .DW SIO1ACLK >> 16 ; ... DWORD VALUE + .DB SIO1ACTCC ; CTC CHANNEL ; ; SIO1 CHANNEL B SIO1B_CFG: @@ -1024,8 +1135,9 @@ SIO1B_CFG: .DB SIO1B_DAT ; DATA PORT .DW SIO1BCFG ; LINE CONFIGURATION .DW SIO1B_RCVBUF ; POINTER TO RCV BUFFER STRUCT - .DW (SIO1BCLK / SIO1BDIV) & $FFFF ; CLOCK FREQ AS - .DW (SIO1BCLK / SIO1BDIV) >> 16 ; ... DWORD VALUE + .DW SIO1BCLK & $FFFF ; CLOCK FREQ AS + .DW SIO1BCLK >> 16 ; ... DWORD VALUE + .DB SIO1BCTCC ; CTC CHANNEL ; #ENDIF ; diff --git a/Source/HBIOS/std.asm b/Source/HBIOS/std.asm index f0aa880d..af024490 100644 --- a/Source/HBIOS/std.asm +++ b/Source/HBIOS/std.asm @@ -119,10 +119,10 @@ DSRTCMODE_MFPIC .EQU 2 ; MF/PIC VARIANT ; SIO MODE SELECTIONS ; SIOMODE_NONE .EQU 0 -SIOMODE_RC .EQU 1 ; RC2014 SIO MODULE (SPENCER OWEN) -SIOMODE_SMB .EQU 2 ; RC2014 SIO MODULE (SCOTT BAKER) -SIOMODE_ZP .EQU 3 ; ECB-ZILOG PERIPHERALS BOARD -SIOMODE_EZZ80 .EQU 4 ; EASY Z80 ON-BOARD SIO/0 +SIOMODE_STD .EQU 1 ; STD SIO REG CFG (EZZ80, KIO) +SIOMODE_RC .EQU 2 ; RC2014 SIO MODULE (SPENCER OWEN) +SIOMODE_SMB .EQU 3 ; RC2014 SIO MODULE (SCOTT BAKER) +SIOMODE_ZP .EQU 4 ; ECB-ZILOG PERIPHERALS BOARD ; ; TYPE OF CONSOLE BELL TO USE ; diff --git a/Source/Images/Common/COMP.COM b/Source/Images/Common/COMP.COM new file mode 100644 index 0000000000000000000000000000000000000000..d91f079fc8756f8ff331854380b94959580d54d7 GIT binary patch literal 1024 zcmaJ;O=uHA6yBN56dKvY(t?1n~i8ea1OKIzW2@dzV{vzgbSw~ z5_Jemi1s8_rUZx9nCM)D%ih91f5&%^O@xt}$gxOV+>YPMn8-mQcM~~8M&uq6Cvq=g zg3v4}-DLZr^&BZZWYl_!DriaQ5ZV~Xbm7*|7z3Ryyti6gMl3|WK1TOqa(NlWq9sSD zy~CU?jB(MWQK%63@UejHDQvyLb_I!@!SW<()+={?7|fJ58`UOT7t5bez2a-LzaeWE zg(d3?D(|92hg#bxJ~&czl(qO^vC7%drF}vy`*D-)@MkO~mb*pvh~IqXUmHmZSQXOLJ5?l}B;66&nQ62aI+Fg9LYT-mT!5tzhW z=olz$qk~!w`w+mr#%8J7tk^$LqucHi?N>Np4~X__+*st_7g*_qsXgNk-HBF#0ogb$ zuOf)CUB09WM=v>IHFs$tvQqP7*6!hMhCo6Z|1+!>XI!~doYbw<}xNAi;Q zMj<<`=BYkQrx#4spfh?lm&~gvN)_s!L6G@N%BGEM(wvzG=B!@OQb$OVH{rfb8{jpq znQA^?$eC&?B1qoJc|8vSUdEhPsae!%+EA!4#+^n%q=jUTS}IV0Gc&3-XU@|kxCZN{ zszIZm0q=Q}20c?S3du}nfkt3dlGhEMjZixN$LBek%;?%2Ev7+-OD0pPylNN}x}>SJ tk;^0(z$BmMEu9t&RpGGJ`<1x6fU#@WuSR(RdRgIEZWV*U{O9bx{{?|ZNuU4# literal 0 HcmV?d00001 diff --git a/Source/Images/Common/COMPARE.COM b/Source/Images/Common/COMPARE.COM deleted file mode 100644 index 29fa41e620a8411a9327359272f7a2b403aefa7b..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 2560 zcmd^A?@tqV82{c~?+aIGp<=dxbNiO^LMxJTW-i{aq{tOqpmlA@BuL0<3p6X#^@oK` zE1E4b-!02#Voa80yfJ%$Q4@?IPVRuTO)e2KiK*EO;^4)|UKqo&Y{|LjuAnaQKk#0B zzt8u%=lOh|&vVb+t=2y@w8iZ66YtS3vDsJ~tVAf|2K0LffjvnNC@ezu z7_wcVOSsj=~{?Z9@1dd-_=|3Lbnd0rvlQJ?pfLa!JzvmnxCQ73~*IL68J#(6RW z6F=_pbPZL{3U0T=)G3jhdNbE~ZU2cs;S)I3$_GyzDav7Y5N z?f;Z#|8litG(q;74!ZU!2Tf1&?q2>`Imm!i(eK^jZX`Z`sATg1sDQ3H`o8e2TbcGL;8I2Q>3WrBF8bKTvPGAYU{_p^w6|LyY39}kD`oj7n^|BqJ{e)w z@$^Z4;o;hVRUentrMbM7y!#wXzKpY9M79%1ongoMNqUSwfwCGZ++ZEHSjjoTjPWs) zhgXN6VDfIn-^99o3qM@TIy9m1h}9YkBG&9h5i9fTYF6_UEqKMFRTs#Sy8UT6Jd zmo80Qy3nEQ#$y@*2k-rujzbB{r*RFgaFZQ1tlW=0jrBGzT*oz`(l-_C^R%}I z`up{qaN2;2pH4;Nqf(576VWpfB8`SgIvGjm_arhHPmt7bq{QB2F&ogK-eV-1-0~-q zDUu$QMovbD((!cCh$L{1l%n~jSE7@VQ*j;sb>TX(#hi)8ppeL*l#ZoHDo$SV4U+h1 zY@CGCyr7d0L9L@eVKIlGycZg#g8I$ViRg%wh(fqtzwvj3JsBN|#-v0^i^Z%9HRyuF z@eGlGR|eyY diff --git a/Source/ver.inc b/Source/ver.inc index 91ca16d7..26c4f45a 100644 --- a/Source/ver.inc +++ b/Source/ver.inc @@ -2,4 +2,4 @@ #DEFINE RMN 1 #DEFINE RUP 0 #DEFINE RTP 0 -#DEFINE BIOSVER "3.1-pre.2" +#DEFINE BIOSVER "3.1-pre.3" diff --git a/Source/ver.lib b/Source/ver.lib index bc39cfbf..a650a444 100644 --- a/Source/ver.lib +++ b/Source/ver.lib @@ -3,5 +3,5 @@ rmn equ 1 rup equ 0 rtp equ 0 biosver macro - db "3.1-pre.2" + db "3.1-pre.3" endm