From 8c0c75253e7622a7e9e51acc2949b85b7ed365ff Mon Sep 17 00:00:00 2001
From: Wayne Warthen <wwarthen@gmail.com>
Date: Wed, 4 Sep 2019 20:46:29 -0700
Subject: [PATCH] Z180 Variant CPU Speed Handling

Check Z180 CPU variant when attempting to change CPU speed multipliers and handle appropriately.
---
 Source/HBIOS/hbios.asm  | 54 ++++++++++++++++++++++++++++++-----------
 Source/HBIOS/romldr.asm |  2 +-
 2 files changed, 41 insertions(+), 15 deletions(-)

diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm
index 29bf9a01..15ba1681 100644
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@@ -796,7 +796,7 @@ HB_START:
 	OUT0	(Z180_DCNTL),A
 
 #IF ((MEMMGR == MM_Z180) | (MEMMGR == MM_N8))
-	; MMU SETUP
+	; Z180 MMU SETUP
 	LD	A,$80
 	OUT0	(Z180_CBAR),A		; SETUP FOR 32K/32K BANK CONFIG
 ;#IFDEF ROMBOOT
@@ -806,19 +806,7 @@ HB_START:
 	LD	A,(RAMSIZE + RAMBIAS - 64) >> 2
 	OUT0	(Z180_CBR),A		; COMMON BASE = LAST (TOP) BANK
 #ENDIF
-
-#IF (Z180_CLKDIV >= 1)
-	; SET CLOCK DIVIDE TO 1 RESULTING IN FULL XTAL SPEED
-	LD	A,$80
-	OUT0	(Z180_CCR),A
-#ENDIF
-
-#IF (Z180_CLKDIV >= 2)
-	; SET CPU MULTIPLIER TO 1 RESULTING IN XTAL * 2 SPEED
-	LD	A,$80
-	OUT0	(Z180_CMR),A
-#ENDIF
-
+;
 #ENDIF
 ;
 #IF (MEMMGR == MM_Z2)
@@ -1004,6 +992,44 @@ HB_CPU1:
 	LD	A,L
 	LD	(HB_CPUTYPE),A
 ;
+#IF (CPUFAM == CPU_Z180)
+;
+	; AT BOOT, Z180 PHI IS OSC / 2
+	LD	C,(CPUOSC / 2) / 1000000
+	LD	DE,(CPUOSC / 2) / 1000
+;
+#IF (Z180_CLKDIV >= 1)
+	LD	A,L		; CPU TYPE
+	CP	2		; Z8S180 REV K OR BETTER?
+	JR	C,HB_CPU2	; IF NOT, NOT POSSIBLE!
+	; SET CLOCK DIVIDE TO 1 RESULTING IN FULL XTAL SPEED
+	LD	A,$80
+	OUT0	(Z180_CCR),A
+	; REFLECT SPEED CHANGE
+	LD	C,CPUOSC / 1000000
+	LD	DE,CPUOSC / 1000
+#ENDIF
+
+#IF (Z180_CLKDIV >= 2)
+	LD	A,L		; CPU TYPE
+	CP	3		; Z8S180 REV N OR BETTER?
+	JR	C,HB_CPU2	; IF NOT, NOT POSSIBLE!
+	; SET CPU MULTIPLIER TO 1 RESULTING IN XTAL * 2 SPEED
+	LD	A,$80
+	OUT0	(Z180_CMR),A
+	; REFLECT SPEED CHANGE
+	LD	C,(CPUOSC * 2) / 1000000
+	LD	DE,(CPUOSC * 2) / 1000
+#ENDIF
+;
+HB_CPU2:
+	; SAVE CPU SPEED IN CONFIG BLOCK
+	LD	A,C
+	LD	(CB_CPUMHZ),A
+	LD	(CB_CPUKHZ),DE
+;
+#ENDIF
+;
 ; PERFORM DYNAMIC CPU SPEED DERIVATION
 ;
 	CALL	HB_CPUSPD		; CPU SPEED DETECTION
diff --git a/Source/HBIOS/romldr.asm b/Source/HBIOS/romldr.asm
index c14327b7..0e1d9dec 100644
--- a/Source/HBIOS/romldr.asm
+++ b/Source/HBIOS/romldr.asm
@@ -737,7 +737,7 @@ PRTDRV1:	; HANDLE RAM/ROM
 	LD	DE,DEVROM		; ASSUME ROM
 	JR	Z,PRTDRV2		; IF SO, PRINT IT
 	LD	DE,DEVRAM		; OTHERWISE RAM
-	JR	PRTDRV2		; PRINT IT
+	JR	PRTDRV2			; PRINT IT
 ;
 PRTDRV2:	; PRINT DEVICE
 	POP	BC			; RECOVER UNIT