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@ -131,8 +131,9 @@ UART0_IST1: ; CHECK FOR STAT0.RDRF (DATA READY) |
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IN A,(SIO_LSR) ; READ LINE STATUS REGISTER |
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AND $01 ; TEST IF DATA IN RECEIVE BUFFER |
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#ENDIF |
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JP Z,CIO_IDLE ; DO IDLE PROCESSING |
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LD A,$01 ; SIGNAL DATA PENDING |
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JP Z,CIO_IDLE ; DO IDLE PROCESSING AND RETURN |
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XOR A |
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INC A ; SIGNAL CHAR READY, A = 1 |
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RET |
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; |
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; |
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@ -153,14 +154,13 @@ UART0_OST: |
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#IF (PLATFORM == PLT_N8) |
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IN0 A,(CPU_STAT0) |
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AND $02 |
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JR Z,UART0_OST |
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#ELSE |
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IN A,(SIO_LSR) ; READ LINE STATUS REGISTER |
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AND $20 |
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JR Z,UART0_OST ; IF NOT REPEAT |
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#ENDIF |
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JP Z,CIO_IDLE ; DO IDLE PROCESSING |
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LD A,$01 ; SIGNAL DATA PENDING |
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JP Z,CIO_IDLE ; DO IDLE PROCESSING AND RETURN |
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XOR A |
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INC A ; SIGNAL BUFFER EMPTY, A = 1 |
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RET |
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; |
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; |
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@ -205,8 +205,9 @@ UART1_IST: |
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UART1_IST1: ; CHECK FOR STAT0.RDRF (DATA READY) |
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IN0 A,(CPU_STAT1) ; READ LINE STATUS REGISTER |
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AND $80 ; TEST IF DATA IN RECEIVE BUFFER |
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JP Z,CIO_IDLE ; DO IDLE PROCESSING |
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LD A,$01 ; SIGNAL DATA PENDING |
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JP Z,CIO_IDLE ; DO IDLE PROCESSING AND RETURN |
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XOR A |
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INC A ; SIGNAL CHAR READY, A = 1 |
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RET |
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; |
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; |
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@ -223,7 +224,8 @@ UART1_OST: |
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IN0 A,(CPU_STAT1) |
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AND $02 |
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JR Z,UART1_OST |
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JP Z,CIO_IDLE ; DO IDLE PROCESSING |
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LD A,$01 ; SIGNAL DATA PENDING |
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JP Z,CIO_IDLE ; DO IDLE PROCESSING AND RETURN |
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XOR A |
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INC A ; SIGNAL BUFFER EMPTY, A = 1 |
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RET |
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#ENDIF |
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