diff --git a/Source/HBIOS/cfg_rcz280.asm b/Source/HBIOS/cfg_rcz280.asm
index 3b70b249..39ea9909 100644
--- a/Source/HBIOS/cfg_rcz280.asm
+++ b/Source/HBIOS/cfg_rcz280.asm
@@ -28,7 +28,7 @@ BOOT_DELAY	.EQU	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
 ;
 CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
-CPUOSC		.EQU	12000000	; CPU OSC FREQ IN MHZ
+CPUOSC		.EQU	24000000	; CPU OSC FREQ IN MHZ
 INTMODE		.EQU	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
 DEFSERCFG	.EQU	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm
index bacea45a..f42a920a 100644
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@@ -2094,6 +2094,15 @@ HB_CPU2:
 HB_CPU3:
 #ENDIF
 ;
+#IF (CPUFAM == CPU_Z280)
+;
+	; Z280 ALWAYS HALVES THE INPUT OSCILLATOR TO DERIVE
+	; ACTUAL CPU SPEED.
+	; ADJUST HL TO REFLECT HALF SPEED OPERATION
+	SRL	H		; ADJUST HL ASSUMING
+	RR	L		; HALF SPEED OPERATION
+#ENDIF
+;
 ; HL SHOULD NOW HAVE FINAL CPU RUNNING SPEED IN KHZ.
 ; UPDATE CB_CPUMHZ/CB_CPUKHZ WITH THIS VALUE.
 ;
diff --git a/Source/ZZRCC/zzrcc_mon.bin b/Source/ZZRCC/zzrcc_mon.bin
index e9a04d74..cedad49d 100644
Binary files a/Source/ZZRCC/zzrcc_mon.bin and b/Source/ZZRCC/zzrcc_mon.bin differ
diff --git a/Source/ver.inc b/Source/ver.inc
index 2d1e939f..6ca89abe 100644
--- a/Source/ver.inc
+++ b/Source/ver.inc
@@ -2,7 +2,7 @@
 #DEFINE	RMN	4
 #DEFINE	RUP	0
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"3.4.0-rc.1"
+#DEFINE BIOSVER	"3.4.0-rc.2"
 #define rmj	RMJ
 #define rmn	RMN
 #define rup	RUP
diff --git a/Source/ver.lib b/Source/ver.lib
index eb1f478d..0ac7cc51 100644
--- a/Source/ver.lib
+++ b/Source/ver.lib
@@ -3,5 +3,5 @@ rmn	equ	4
 rup	equ	0
 rtp	equ	0
 biosver	macro
-	db	"3.4.0-rc.1"
+	db	"3.4.0-rc.2"
 	endm