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Merge pull request #22 from wwarthen/master

Finalize SCZ180 Configurations
patch
b1ackmai1er 6 years ago
committed by GitHub
parent
commit
98bec91318
No known key found for this signature in database GPG Key ID: 4AEE18F83AFDEB23
  1. 28
      Binary/RomList.txt
  2. 1
      Doc/ChangeLog.txt
  3. 4
      Doc/Contrib/LinuxBuild.txt
  4. 8
      ReadMe.txt
  5. 12
      Source/Apps/RTC.asm
  6. 6
      Source/Apps/Tune/Tune.asm
  7. 2
      Source/CBIOS/ver.inc
  8. 3
      Source/HBIOS/Build.ps1
  9. 2
      Source/HBIOS/Config/MK4_std.asm
  10. 2
      Source/HBIOS/Config/SBC_std.asm
  11. 4
      Source/HBIOS/Config/SCZ180_126.asm
  12. 49
      Source/HBIOS/Config/SCZ180_130.asm
  13. 4
      Source/HBIOS/cfg_ezz80.asm
  14. 4
      Source/HBIOS/cfg_master.asm
  15. 4
      Source/HBIOS/cfg_mk4.asm
  16. 4
      Source/HBIOS/cfg_n8.asm
  17. 4
      Source/HBIOS/cfg_rcz180.asm
  18. 4
      Source/HBIOS/cfg_rcz80.asm
  19. 4
      Source/HBIOS/cfg_sbc.asm
  20. 10
      Source/HBIOS/cfg_scz180.asm
  21. 2
      Source/HBIOS/cfg_una.asm
  22. 4
      Source/HBIOS/cfg_zeta.asm
  23. 4
      Source/HBIOS/cfg_zeta2.asm
  24. 2
      Source/HBIOS/dsrtc.asm
  25. 12
      Source/HBIOS/romldr.asm
  26. 28
      Source/HBIOS/sd.asm
  27. 6
      Source/HBIOS/std.asm
  28. 2
      Source/HBIOS/ver.inc
  29. 7
      Source/ReadMe.txt

28
Binary/RomList.txt

@ -31,9 +31,10 @@ image to use for each platform:
Zeta V2 ZETA2_std.rom
N8 N8_std.rom
Mark IV MK4_std.rom
RC2014 RC_std.rom
RC2014 w/ Z180 RC180_nat.rom (native Z180 memory addressing)
RC2014 w/ Z180 RC180_ext.rom (512K RAM/ROM module)
RC2014 w/ Z80 RCZ80_std.rom
RC2014 w/ Z180 RCZ180_nat.rom (native Z180 memory addressing)
RC2014 w/ Z180 RCZ180_ext.rom (external 512K RAM/ROM module)
SC-series SC126, SC130
Easy Z80 EZZ180_std.rom
You will find there is one additional ROM image called
@ -155,6 +156,16 @@ RCZ80 (RCZ80_std.rom):
- Support for Scott Baker floppy controllers (SMC & WDC) may
be enabled in config
RCZ80 w/ KIO (RCZ80_kio.rom):
- Assumes CPU oscillator of 7.3728 MHz
- Requires 512K RAM/ROM module
- Requires KIO module
- Includes support for Compact Flash Module
- Support for PPIDE Module may be enabled in config
- Support for Scott Baker SIO board may be enabled in config
- Support for Scott Baker floppy controllers (SMC & WDC) may
be enabled in config
RCZ180 (RCZ180_nat.rom & RCZ180_ext.rom):
- Assumes CPU oscillator of 18.432 MHz
- Console attached to Z180 onboard serial ports at 38400 baud
@ -171,6 +182,17 @@ RCZ180 (RCZ180_nat.rom & RCZ180_ext.rom):
- RCZ180_ext.rom uses external bank management to access
memory, such as the 512K RAM/ROM module.
SCZ180 (SCZ180_126.rom & SCZ180_130.rom):
- Assumes CPU oscillator of 18.432 MHz
- Console attached to Z180 onboard serial ports at 38400 baud
- Includes support for Compact Flash Module
- Support for PPIDE Module may be enabled in config
- Support for alternative serial modules may be enabled in config
- Support for Scott Baker floppy controllers (SMC & WDC) may
be enabled in config
- The _126 and _130 varians are functionally identical, they just
display a different system label at startup
EZZ80 (EZZ80_std.rom):
- Assumes CPU oscillator of 10.000 MHz
- Includes support for on-board SIO

1
Doc/ChangeLog.txt

@ -21,6 +21,7 @@ Version 2.9.2
- N?B: Made ZCAL Y2K compliant
- WBW: Show disk activity on diagnostic LEDs
- WBW: DSRTC now detects DS-1302 presence dynamically
- WBW: SC126 platform renamed to SCZ180 w/ configs for SC126, SC130
- WBW: Add status LED support
Version 2.9.1

4
Doc/Contrib/LinuxBuild.txt

@ -1,5 +1,9 @@
Assembling the RomWBW firmware under Linux.
Note: This process is generally deprecated as it has not been maintained.
This document remains in the hope that someday it will be useful for
resurrecting a Linux build.
Note: Updated on 6/25/2013 to eliminate the need for the separate Linux
makefile. The standard makefile now has conditionals to allow it to be
used under Windows or Linux (I hope) --WW

8
ReadMe.txt

@ -7,12 +7,12 @@
***********************************************************************
Wayne Warthen (wwarthen@gmail.com)
Version 2.9.2-pre.12, 2019-09-29
Version 2.9.2-pre.13, 2019-10-02
https://www.retrobrewcomputers.org/
RomWBW is a ROM-based implementation of CP/M-80 2.2 and Z-System for
all RetroBrew Computers Z80/Z180 hardware platforms including SBC
1/2, Zeta 1/2, N8, Mark IV, RC2014, and Easy Z80. Virtually all
1/2, Zeta 1/2, N8, Mark IV, RC2014, SC, and Easy Z80. Virtually all
RetroBrew hardware is supported including floppy, hard disk (IDE, CF
Card, SD Card), Video, and keyboard. VT-100 terminal emulation is
built-in.
@ -145,10 +145,8 @@ few things that UNA does not support:
- Floppy Drives
- Video/Keyboard/Terminal Emulation
- Zeta 1, N8, and RC2014 systems
- Zeta 1, N8, RC2014, SC, and Easy Z80 systems
- Some older support boards
- RC2014 systems
- Easy Z80 systems
If you wish to try the UNA variant of RomWBW, then just program your
ROM with the ROM image called "UNA_std.rom" in the Binary directory.

12
Source/Apps/RTC.asm

@ -21,7 +21,7 @@
;
;[2019/06/21] v1.3 Finalized RC2014 Z180 support.
;
;[2019/08/11] v1.4 Support SC126 platform.
;[2019/08/11] v1.4 Support SCZ180 platform.
;
;
; Constants
@ -36,7 +36,7 @@ PORT_N8 .EQU $88 ; RTC port for N8
PORT_MK4 .EQU $8A ; RTC port for MK4
PORT_RCZ80 .EQU $C0 ; RTC port for RC2014
PORT_RCZ180 .EQU $0C ; RTC port for RC2014
PORT_SC126 .EQU $0C ; RTC port for SBC126
PORT_SCZ180 .EQU $0C ; RTC port for SBCZ180
PORT_EZZ80 .EQU $C0 ; RTC port for EZZ80 (actually does not have one!!!)
BDOS .EQU 5 ; BDOS invocation vector
@ -1081,9 +1081,9 @@ HINIT:
LD DE,PLT_RCZ180
CP $08 ; RC2014 w/ Z180
JR Z,RTC_INIT2
LD C,PORT_SC126
LD DE,PLT_SC126
CP $0A ; SC126
LD C,PORT_SCZ180
LD DE,PLT_SCZ180
CP $0A ; SCZ180
JR Z,RTC_INIT2
;LD C,PORT_EZZ80
;LD DE,PLT_EZZ80
@ -1675,7 +1675,7 @@ PLT_N8 .TEXT ", N8 RTC Latch Port 0x88\r\n$"
PLT_MK4 .TEXT ", Mark 4 RTC Latch Port 0x8A\r\n$"
PLT_RCZ80 .TEXT ", RC2014 Z80 RTC Module Latch Port 0xC0\r\n$"
PLT_RCZ180 .TEXT ", RC2014 Z180 RTC Module Latch Port 0x0C\r\n$"
PLT_SC126 .TEXT ", SC126 Z180 RTC Module Latch Port 0x0C\r\n$"
PLT_SCZ180 .TEXT ", SC Z180 RTC Module Latch Port 0x0C\r\n$"
PLT_EZZ80 .TEXT ", Easy Z80 RTC Module Latch Port 0xC0\r\n$"
;

6
Source/Apps/Tune/Tune.asm

@ -93,8 +93,8 @@ TYPMYM .EQU 3 ; FILTYP value for MYM sound file
LD DE,MSGRCZ180 ; Message for RC2014 Z180 platform
CP 8 ; RC2014 Z80?
JR Z,_SETP ; If so, set ports
LD DE,MSGSC126 ; Message for SC126 Z180 platform
CP 10 ; SC126?
LD DE,MSGSCZ180 ; Message for SC Z180 platform
CP 10 ; SCZ180?
JR Z,_SETP ; If so, same ports as RC2014
LD HL,$9D9C ; For N8, RSEL=9C, RDAT=9D
LD DE,MSGN8 ; Message for N8 platform
@ -621,7 +621,7 @@ MSGFIL .DB "Sound file not found!",0
MSGSIZ .DB "Sound file too large to load!",0
MSGRCZ80 .DB "RC2014 Z80 w/ Ed Brindley Sound Module",0
MSGRCZ180 .DB "RC2014 Z180 w/ Ed Brindley Sound Module",0
MSGSC126 .DB "SC126 Z180 w/ Ed Brindley Sound Module",0
MSGSCZ180 .DB "SC Z180 w/ Ed Brindley Sound Module",0
MSGEZ .DB "Easy Z80 w/ Ed Brindley Sound Module",0
MSGN8 .DB "RetroBrew N8 Onboard Sound System",0
MSGSCG .DB "RetroBrew SCG ECB Adapter Sound System",0

2
Source/CBIOS/ver.inc

@ -2,4 +2,4 @@
#DEFINE RMN 9
#DEFINE RUP 2
#DEFINE RTP 0
#DEFINE BIOSVER "2.9.2-pre.12"
#DEFINE BIOSVER "2.9.2-pre.13"

3
Source/HBIOS/Build.ps1

@ -20,7 +20,7 @@ param([string]$Platform = "", [string]$Config = "", [string]$RomSize = "512", [s
# UNA BIOS is simply imbedded, it is not built here.
#
$PlatformListZ80 = "SBC", "ZETA", "ZETA2", "RCZ80", "EZZ80", "UNA"
$PlatformListZ180 = "N8", "MK4", "RCZ180", "SC126"
$PlatformListZ180 = "N8", "MK4", "RCZ180", "SCZ180"
#
# Establish the build platform. It may have been passed in on the command line. Validate
@ -72,7 +72,6 @@ while ($true)
# TASM should be invoked with the proper CPU type. Below, the CPU type is inferred
# from the platform.
#
#if (($Platform -eq "N8") -or ($Platform -eq "MK4") -or ($Platform -eq "RCZ180") -or ($Platform -eq "SC126")) {$CPUType = "180"} else {$CPUType = "80"}
if ($PlatformListZ180 -contains $Platform) {$CPUType = "180"} else {$CPUType = "80"}
#

2
Source/HBIOS/Config/MK4_std.asm

@ -44,6 +44,6 @@ PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM
PPIDEMODE .SET PPIDEMODE_MFP ; PPIDE: DRIVER MODE: PPIDEMODE_[SBC|DIO3|MFP|N8|RC]
;
SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .SET SDMODE_MK4 ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC126]
SDMODE .SET SDMODE_MK4 ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC]
;
PRPENABLE .SET TRUE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)

2
Source/HBIOS/Config/SBC_std.asm

@ -40,6 +40,6 @@ PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
PPIDEMODE .SET PPIDEMODE_SBC ; PPIDE: DRIVER MODE: PPIDEMODE_[SBC|DIO3|MFP|N8|RC]
;
SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .SET SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC126]
SDMODE .SET SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC]
;
PRPENABLE .SET TRUE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)

4
Source/HBIOS/Config/SC126_std.asm → Source/HBIOS/Config/SCZ180_126.asm

@ -22,7 +22,9 @@
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
; DIRECTORIES ABOVE THIS ONE).
;
#include "cfg_sc126.asm"
#DEFINE PLATFORM_NAME "SC126"
;
#include "cfg_scz180.asm"
;
CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ
;

49
Source/HBIOS/Config/SCZ180_130.asm

@ -0,0 +1,49 @@
;
;==================================================================================================
; SC130 STANDARD CONFIGURATION
;==================================================================================================
;
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
; YOUR FILE IN THE BUILD PROCESS.
;
; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
; SETTINGS.
;
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
;
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
; DIRECTORIES ABOVE THIS ONE).
;
#DEFINE PLATFORM_NAME "SC130"
;
#include "cfg_scz180.asm"
;
CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ
;
Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3)
Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
;
LEDENABLE .SET TRUE ; ENABLES STATUS LED (SINGLE LED)
;
ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
;
FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|DIDE|N8|DIO3]
;
IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
IDEMODE .SET IDEMODE_RC ; IDE: DRIVER MODE: IDEMODE_[DIO|DIDE]
;
PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
;
SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)

4
Source/HBIOS/cfg_ezz80.asm

@ -13,7 +13,7 @@
;
#DEFINE PLATFORM_NAME "EASYZ80"
;
PLATFORM .EQU PLT_EZZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SC126]
PLATFORM .EQU PLT_EZZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180]
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@ -124,7 +124,7 @@ PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDE8BIT .EQU FALSE ; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
;
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC126]
SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC]
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
;

4
Source/HBIOS/cfg_master.asm

@ -10,7 +10,7 @@
;
#DEFINE PLATFORM_NAME "ROMWBW"
;
PLATFORM .EQU PLT_SBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SC126]
PLATFORM .EQU PLT_SBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180]
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@ -166,7 +166,7 @@ PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDE8BIT .EQU FALSE ; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
;
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_NONE ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC126]
SDMODE .EQU SDMODE_NONE ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC]
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
;

4
Source/HBIOS/cfg_mk4.asm

@ -13,7 +13,7 @@
;
#DEFINE PLATFORM_NAME "MARK IV"
;
PLATFORM .EQU PLT_MK4 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SC126]
PLATFORM .EQU PLT_MK4 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180]
CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@ -124,7 +124,7 @@ PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDE8BIT .EQU FALSE ; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
;
SDENABLE .EQU TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_MK4 ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC126]
SDMODE .EQU SDMODE_MK4 ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC]
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
SDCSIOFAST .EQU TRUE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
;

4
Source/HBIOS/cfg_n8.asm

@ -13,7 +13,7 @@
;
#DEFINE PLATFORM_NAME "N8"
;
PLATFORM .EQU PLT_N8 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SC126]
PLATFORM .EQU PLT_N8 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180]
CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@ -127,7 +127,7 @@ PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDE8BIT .EQU FALSE ; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
;
SDENABLE .EQU TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_CSIO ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC126]
SDMODE .EQU SDMODE_CSIO ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC]
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
;

4
Source/HBIOS/cfg_rcz180.asm

@ -13,7 +13,7 @@
;
#DEFINE PLATFORM_NAME "RC2014"
;
PLATFORM .EQU PLT_RCZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SC126]
PLATFORM .EQU PLT_RCZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180]
CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@ -130,7 +130,7 @@ PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDE8BIT .EQU FALSE ; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
;
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC126]
SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC]
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
;

4
Source/HBIOS/cfg_rcz80.asm

@ -13,7 +13,7 @@
;
#DEFINE PLATFORM_NAME "RC2014"
;
PLATFORM .EQU PLT_RCZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SC126]
PLATFORM .EQU PLT_RCZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180]
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@ -133,7 +133,7 @@ PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDE8BIT .EQU FALSE ; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
;
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC126]
SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC]
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
;

4
Source/HBIOS/cfg_sbc.asm

@ -13,7 +13,7 @@
;
#DEFINE PLATFORM_NAME "SBC"
;
PLATFORM .EQU PLT_SBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SC126]
PLATFORM .EQU PLT_SBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180]
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@ -124,7 +124,7 @@ PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDE8BIT .EQU FALSE ; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
;
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_JUHA ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC126]
SDMODE .EQU SDMODE_JUHA ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC]
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
;

10
Source/HBIOS/cfg_sc126.asm → Source/HBIOS/cfg_scz180.asm

@ -1,6 +1,6 @@
;
;==================================================================================================
; ROMWBW 2.X CONFIGURATION DEFAULTS FOR SC126
; ROMWBW 2.X CONFIGURATION DEFAULTS FOR SC Z180 VARIANTS (SC126, SC130, ETC.)
;==================================================================================================
;
; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
@ -11,9 +11,9 @@
; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
; FOR THE PLATFORM.
;
#DEFINE PLATFORM_NAME "SC126"
#DEFINE PLATFORM_NAME "SCZ180"
;
PLATFORM .EQU PLT_SC126 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SC126]
PLATFORM .EQU PLT_SCZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180]
CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@ -46,7 +46,7 @@ DIAGENABLE .EQU TRUE ; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
DIAGPORT .EQU $0D ; DIAGNOSTIC PORT ADDRESS
DIAGDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
;
LEDENABLE .EQU TRUE ; ENABLES STATUS LED (SINGLE LED)
LEDENABLE .EQU FALSE ; ENABLES STATUS LED (SINGLE LED)
LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS
LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED
;
@ -125,7 +125,7 @@ PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDE8BIT .EQU FALSE ; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
;
SDENABLE .EQU TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_SC126 ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC126]
SDMODE .EQU SDMODE_SC ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC]
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
;

2
Source/HBIOS/cfg_una.asm

@ -13,7 +13,7 @@
;
#DEFINE PLATFORM_NAME "UNA"
;
PLATFORM .EQU PLT_UNA ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SC126]
PLATFORM .EQU PLT_UNA ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180]
BIOS .EQU BIOS_UNA ; HARDWARE BIOS: BIOS_[WBW|UNA]
;
BOOTTYPE .EQU BT_MENU ; BT_[MENU|AUTO], IF AUTO, BOOT DEFAULT AFTER TIMEOUT

4
Source/HBIOS/cfg_zeta.asm

@ -13,7 +13,7 @@
;
#DEFINE PLATFORM_NAME "ZETA"
;
PLATFORM .EQU PLT_ZETA ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SC126]
PLATFORM .EQU PLT_ZETA ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180]
CPUFAM .EQU CPU_Z80 ; CPU_[Z80|Z180]: CPU FAMILY
BIOS .EQU BIOS_WBW ; BIOS_[WBW|UNA]: HARDWARE BIOS
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@ -103,7 +103,7 @@ PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDE8BIT .EQU FALSE ; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
;
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC126]
SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC]
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
;

4
Source/HBIOS/cfg_zeta2.asm

@ -13,7 +13,7 @@
;
#DEFINE PLATFORM_NAME "ZETA V2"
;
PLATFORM .EQU PLT_ZETA2 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SC126]
PLATFORM .EQU PLT_ZETA2 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180]
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@ -107,7 +107,7 @@ PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDE8BIT .EQU FALSE ; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
;
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC126]
SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC]
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
;

2
Source/HBIOS/dsrtc.asm

@ -63,7 +63,7 @@
;
; CONSTANTS
;
; RTC SBC SBC-004 MFPIC N8 N8-CSIO SC126
; RTC SBC SBC-004 MFPIC N8 N8-CSIO SC
; ----- ------- ------- ------- ------- ------- -------
; D7 WR RTC_OUT RTC_OUT -- RTC_OUT RTC_OUT RTC_OUT, I2C_SDA
; D6 WR RTC_CLK RTC_CLK -- RTC_CLK RTC_CLK RTC_CLK

12
Source/HBIOS/romldr.asm

@ -216,6 +216,10 @@ SEL:
XOR A ; ZERO ACCUM
OUT (DIAGPORT),A ; CLEAR DIAG LEDS
#ENDIF
#IF (LEDENABLE)
OR $FF ; LED IS INVERTED
OUT (LEDPORT),A ; CLEAR LED
#ENDIF
#ENDIF
CALL CINUC ; GET THE KEY
CALL COUT ; ECHO KEY
@ -232,6 +236,10 @@ SEL1:
XOR A ; ZERO ACCUM
OUT (DIAGPORT),A ; CLEAR DIAG LEDS
#ENDIF
#IF (LEDENABLE)
OR $FF ; LED IS INVERTED
OUT (LEDPORT),A ; CLEAR LED
#ENDIF
#ENDIF
CALL DSKY_GETKEY ; GET PENDING KEY PRESS
JR MATK ; AND HANDLE IT
@ -254,6 +262,10 @@ SEL2:
XOR A ; ZERO ACCUM
OUT (DIAGPORT),A ; CLEAR DIAG LEDS
#ENDIF
#IF (LEDENABLE)
OR $FF ; LED IS INVERTED
OUT (LEDPORT),A ; CLEAR LED
#ENDIF
#ENDIF
LD A,BOOT_DEFAULT ; TIMEOUT EXPIRED,
JR MATS ; PERFORM DEFAULT BOOT ACTION

28
Source/HBIOS/sd.asm

@ -10,7 +10,7 @@
; - TRY TO GET INIT TO FAIL, REMOVE DELAYS AT START OF GOIDLE?
;
;--------------------------------------------------------------------------------------
; SD Signal Active JUHA N8 CSIO PPI UART DSD MK4 SC126
; SD Signal Active JUHA N8 CSIO PPI UART DSD MK4 SC
; ------------ ------- ------- ------- ------- ------- ------- ------- ------- -------
; CS (DAT3) LO -> RTC:2 RTC:2 RTC:2 ~PC:4 ~MCR:3 OPR:2 SD:2 ~RTC:2
; CLK HI -> RTC:1 RTC:1 CSIO PC:1 ~MCR:2 OPR:1 CSIO CSIO
@ -194,7 +194,7 @@ SD_CNTR .EQU Z180_CNTR
SD_TRDR .EQU Z180_TRDR
#ENDIF
;
#IF (SDMODE == SDMODE_SC126) ; SC126
#IF (SDMODE == SDMODE_SC) ; SC
SD_DEVCNT .EQU 1 ; NUMBER OF PHYSICAL UNITS (SOCKETS)
SD_OPRREG .EQU RTCIO ; USES RTC LATCHES FOR OPERATION
SD_OPRDEF .EQU %00001100 ; QUIESCENT STATE (/CS1 & /CS2 DEASSERTED)
@ -373,8 +373,8 @@ SD_INIT:
CALL PRTHEXBYTE
#ENDIF
;
#IF (SDMODE == SDMODE_SC126)
PRTS(" MODE=SC126$")
#IF (SDMODE == SDMODE_SC)
PRTS(" MODE=SC$")
#IF (SDCSIOFAST)
PRTS(" FAST$")
#ENDIF
@ -920,7 +920,7 @@ SD_INITCARD5:
CALL SD_EXECCMDND ; EXEC COMMAND W/ NO DATA
RET NZ ; ABORT ON ERROR
#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC126))
#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC))
; PER SPEC, THE CARD SHOULD NOW BE ABLE TO HANDLE FULL SPEED OPERATION
; SO, FOR CSIO OPERATION, WE SET CSIO TO MAXIMUM SPEED
CALL SD_WAITTX ; MAKE SURE WE ARE DONE SENDING
@ -1393,14 +1393,14 @@ SD_SETUP:
OUT (SD_PPIX),A
#ENDIF
;
#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC126))
#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC))
; CSIO SETUP FOR Z180 CSIO
; LD A,2 ; 18MHz/20 <= 400kHz
LD A,6 ; ???
OUT0 (SD_CNTR),A
#ENDIF
;
#IF ((SDMODE == SDMODE_JUHA) | (SDMODE == SDMODE_N8) | (SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_SC126))
#IF ((SDMODE == SDMODE_JUHA) | (SDMODE == SDMODE_N8) | (SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_SC))
LD A,(RTCVAL)
LD (SD_OPRVAL),A
OUT (SD_OPRREG),A
@ -1463,7 +1463,7 @@ SD_CHKWP:
;
SD_SELECT:
LD A,(SD_OPRVAL)
#IF ((SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_UART) | (SDMODE == SDMODE_SC126))
#IF ((SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_UART) | (SDMODE == SDMODE_SC))
AND ~SD_CS ; SET SD_CS (CHIP SELECT)
#ELSE
OR SD_CS ; SET SD_CS (CHIP SELECT)
@ -1476,7 +1476,7 @@ SD_SELECT:
;
SD_DESELECT:
LD A,(SD_OPRVAL)
#IF ((SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_UART) | (SDMODE == SDMODE_SC126))
#IF ((SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_UART) | (SDMODE == SDMODE_SC))
OR SD_CS ; RESET SD_CS (CHIP SELECT)
#ELSE
AND ~SD_CS ; RESET SD_CS (CHIP SELECT)
@ -1485,7 +1485,7 @@ SD_DESELECT:
OUT (SD_OPRREG),A
RET
;
#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC126))
#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC))
;
; CSIO WAIT FOR TRANSMIT READY (TX REGSITER EMPTY)
;
@ -1508,7 +1508,7 @@ SD_WAITRX:
; SEND ONE BYTE
;
SD_PUT:
#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC126))
#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC))
CALL MIRROR ; MSB<-->LSB MIRROR BITS, RESULT IN C
CALL SD_WAITTX ; MAKE SURE WE ARE DONE SENDING
OUT0 (SD_TRDR),C ; PUT BYTE IN BUFFER
@ -1540,7 +1540,7 @@ SD_PUT1:
; RECEIVE ONE BYTE
;
SD_GET:
#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC126))
#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC))
CALL SD_WAITTX ; MAKE SURE WE ARE DONE SENDING
IN0 A,(Z180_CNTR) ; GET CSIO STATUS
SET 5,A ; START RECEIVER
@ -1839,7 +1839,7 @@ SD_DSKBUF .DW 0 ; ADR OF ACTIVE DISK BUFFER
; MSB<-->LSB MIRROR BITS IN A, RESULT IN C
;
MIRROR:
#IF (((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC126)) & SDCSIOFAST)
#IF (((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC)) & SDCSIOFAST)
LD BC,MIRTAB ; 256 BYTE MIRROR TABLE
ADD A,C ; ADD OFFSET
LD C,A
@ -1860,7 +1860,7 @@ MIRROR1:
;
; LOOKUP TABLE TO MIRROR BITS IN A BYTE
;
#IF (((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC126)) & SDCSIOFAST)
#IF (((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC)) & SDCSIOFAST)
MIRTAB .DB 00H, 80H, 40H, 0C0H, 20H, 0A0H, 60H, 0E0H, 10H, 90H, 50H, 0D0H, 30H, 0B0H, 70H, 0F0H
.DB 08H, 88H, 48H, 0C8H, 28H, 0A8H, 68H, 0E8H, 18H, 98H, 58H, 0D8H, 38H, 0B8H, 78H, 0F8H

6
Source/HBIOS/std.asm

@ -11,7 +11,7 @@
; 7. RCZ80 RC2014 based system with 512K banked RAM/ROM card
; 8. RCZ180 RC2014 based system with Z180 CPU
; 9. EZZ80 Easy Z80, Z80 SBC w/ RC2014 bus and CTC
; 10. SC126 SC126 Z180 based system
; 10. SCZ180 Steve Cousins Z180 based system
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
@ -40,7 +40,7 @@ PLT_UNA .EQU 6 ; UNA BIOS
PLT_RCZ80 .EQU 7 ; RC2014 W Z80
PLT_RCZ180 .EQU 8 ; RC2014 W/ Z180
PLT_EZZ80 .EQU 9 ; EASY Z80
PLT_SC126 .EQU 10 ; SC126
PLT_SCZ180 .EQU 10 ; SCZ180
;
#IF (BIOS == BIOS_WBW)
#INCLUDE "hbios.inc"
@ -154,7 +154,7 @@ SDMODE_PPI .EQU 4 ; PPISD MINI BOARD
SDMODE_UART .EQU 5 ; SD INTERFACE VIA UART
SDMODE_DSD .EQU 6 ; DUAL SD
SDMODE_MK4 .EQU 7 ; MARK IV
SDMODE_SC126 .EQU 8 ; SC126
SDMODE_SC .EQU 8 ; SC (Steve Cousins)
;
; SOUND CHIP MODE SELECTIONS
;

2
Source/HBIOS/ver.inc

@ -2,4 +2,4 @@
#DEFINE RMN 9
#DEFINE RUP 2
#DEFINE RTP 0
#DEFINE BIOSVER "2.9.2-pre.12"
#DEFINE BIOSVER "2.9.2-pre.13"

7
Source/ReadMe.txt

@ -98,9 +98,10 @@ to determine the <plt> component of the configuration filename:
Zeta V2 ZETA2_std.rom
N8 N8_std.rom
Mark IV MK4_std.rom
RC2014 RC_std.rom
RC2014 w/ Z180 RC180_nat.rom (native Z180 memory addressing)
RC2014 w/ Z180 RC180_ext.rom (512K RAM/ROM module)
RC2014 w/ Z80 RCZ80_std.rom
RC2014 w/ Z180 RCZ180_nat.rom (native Z180 memory addressing)
RC2014 w/ Z180 RCZ180_ext.rom (external 512K RAM/ROM module)
SC-series SC126, SC130
Easy Z80 EZZ180_std.rom
You can use any name you choose for the <cfg> component of the

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