diff --git a/Binary/RomList.txt b/Binary/RomList.txt
index 02ca2f53..312308f2 100644
--- a/Binary/RomList.txt
+++ b/Binary/RomList.txt
@@ -177,44 +177,28 @@ RCZ180 (RCZ180_nat.rom & RCZ180_ext.rom):
  - Support for Scott Baker floppy controllers (SMC & WDC) may
    be enabled in config
  - Support for J.B. Lang TMS9918 video card may be enabled in config
- - You must pick the _nat or _ext variant depending on which
-   memory module you are using:
-   - RCZ180_nat.rom uses the built-in Z180 memory manager
-     for use with memory modules allow direct physical
-     addressing of memory, such as the SC119
+ - You must pick the variant (_ext or _nat) depending
+   on which memory module you are using:
    - RCZ180_ext.rom uses external bank management to access
      memory, such as the 512K RAM/ROM module.
+   - RCZ180_nat.rom uses the built-in Z180 memory manager
+     for use with memory modules using direct physical
+     addressing of memory, such as the SC119.
  - Support for PropIO V2 may be enabled in config (PRPENABLE).  If
    enabled, will auto-detect and install associated
    video, keyboard and SD Card support if present.
 
-RCZ280 (RCZ280_ext.rom):
+RCZ280 (RCZ280_ext.rom, RCZ280_nat.rom, RCZ280_nat_zz.rom):
  - Assumes CPU oscillator of 24 MHz
- - Bus clock will be 6 MHz, so does not match RC2014 standard!!!
- - Requires 512K RAM/ROM module
+ - Bus clock will be 6 MHz or 12 MHz, so does not match RC2014 standard!!!
+ - Requires 512K RAM/ROM module (unless using ZZ80MB)
  - Auto detects Serial I/O Module (ACIA), Dual Serial
-   Module (SIO/2), and EP Dual UART.
+   Module (SIO), EP Dual UART (DUART), and built-in Z280 UART (Z2U).
+ - ACIA module is only supported on _ext variant.
+ - Built-in Z280 UART (Z2U) is buffered and interrupt driven only
+   on _nat and _nat_zz variants.  It uses polling I/O on _ext.
  - Console on whichever serial module is installed,
-   order of priority is UART, SIO, then ACIA.
- - Baud rate is determined by hardware, but normally 115200.
- - Auto support for RC2014 Compact Flash Module
- - Auto support for RC2014 PPIDE Module
- - Support for Scott Baker SIO board may be enabled in config
- - Support for Scott Baker floppy controllers (SMC & WDC) may
-   be enabled in config
- - Support for J.B. Lang TMS9918 video card may be enabled in config
- - Support for PropIO V2 may be enabled in config (PRPENABLE).  If
-   enabled, will auto-detect and install associated
-   video, keyboard and SD Card support if present.
-
-RCZ280 (RCZ280_nat.rom):
- - Assumes CPU oscillator of 24 MHz
- - Bus clock will be 6 MHz, so does not match RC2014 standard!!!
- - Requires native RAM/ROM module (linear memory)
- - Interrupt Mode 3 only (no ACIA support possible)
- - Auto detects Dual Serial Module (SIO/2), and EP Dual UART.
- - Console on whichever serial module is installed,
-   order of priority is UART, then SIO.
+   order of priority is UART, SIO, DUART, ACIA, Z2U
  - Baud rate is determined by hardware, but normally 115200.
  - Auto support for RC2014 Compact Flash Module
  - Auto support for RC2014 PPIDE Module
@@ -222,6 +206,15 @@ RCZ280 (RCZ280_nat.rom):
  - Support for Scott Baker floppy controllers (SMC & WDC) may
    be enabled in config
  - Support for J.B. Lang TMS9918 video card may be enabled in config
+ - You must pick the variant (_ext, _nat, or _nat_zz) depending
+   on which platform or memory module you are using:
+   - RCZ280_ext.rom uses external bank management to access
+     memory, such as the 512K RAM/ROM module.
+   - RCZ280_nat.rom uses the built-in Z280 memory manager
+     for use with memory modules using direct physical
+     addressing of memory, such as the SC119.
+   - RCZ280_nat_zz.rom is specifically for the ZZ80MB platform
+     which has both CPU and memory onboard.
  - Support for PropIO V2 may be enabled in config (PRPENABLE).  If
    enabled, will auto-detect and install associated
    video, keyboard and SD Card support if present.
diff --git a/Source/HBIOS/Config/RCZ280_ext.asm b/Source/HBIOS/Config/RCZ280_ext.asm
index f38142f3..1a82285b 100644
--- a/Source/HBIOS/Config/RCZ280_ext.asm
+++ b/Source/HBIOS/Config/RCZ280_ext.asm
@@ -32,7 +32,8 @@ CPUOSC		.SET	24000000	; CPU OSC FREQ IN MHZ
 ;
 INTMODE		.SET	1
 ;
-Z280_MEMWAIT	.SET	0		; Z280: MEMORY WAIT STATES (0-3)
+Z280_MEMLOWAIT	.SET	0		; Z280: LOW 8MB MEMORY WAIT STATES (0-3)
+Z280_MEMHIWAIT	.SET	0		; Z280: HIGH 8MB MEMORY WAIT STATES (0-3)
 Z280_IOWAIT	.SET	1		; Z280: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
 Z280_INTWAIT	.SET	0		; Z280: INT ACK WAIT STATUS (0-3)
 ;
diff --git a/Source/HBIOS/Config/RCZ280_nat.asm b/Source/HBIOS/Config/RCZ280_nat.asm
index 36da6105..0282c2b2 100644
--- a/Source/HBIOS/Config/RCZ280_nat.asm
+++ b/Source/HBIOS/Config/RCZ280_nat.asm
@@ -30,11 +30,12 @@ CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
 CPUOSC		.SET	24000000	; CPU OSC FREQ IN MHZ
 ;
-MEMMGR		.SET	MM_Z280RC	; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280RC|Z280ZZ]
+MEMMGR		.SET	MM_Z280		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
 ;
 INTMODE		.SET	3
 ;
-Z280_MEMWAIT	.SET	0		; Z280: MEMORY WAIT STATES (0-3)
+Z280_MEMLOWAIT	.SET	0		; Z280: LOW 8MB MEMORY WAIT STATES (0-3)
+Z280_MEMHIWAIT	.SET	0		; Z280: HIGH 8MB MEMORY WAIT STATES (0-3)
 Z280_IOWAIT	.SET	1		; Z280: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
 Z280_INTWAIT	.SET	0		; Z280: INT ACK WAIT STATUS (0-3)
 ;
diff --git a/Source/HBIOS/Config/RCZ280_nat_zz.asm b/Source/HBIOS/Config/RCZ280_nat_zz.asm
index d9bb9534..991b662e 100644
--- a/Source/HBIOS/Config/RCZ280_nat_zz.asm
+++ b/Source/HBIOS/Config/RCZ280_nat_zz.asm
@@ -26,4 +26,4 @@
 ;
 #include "Config/RCZ280_nat.asm"
 ;
-MEMMGR		.SET	MM_Z280ZZ	; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280RC|Z280ZZ]
+RAMLOC		.SET	23		; START OF RAM AS POWER OF 2 (2^N)
diff --git a/Source/HBIOS/cfg_dyno.asm b/Source/HBIOS/cfg_dyno.asm
index ad5f4b4e..e966dc92 100644
--- a/Source/HBIOS/cfg_dyno.asm
+++ b/Source/HBIOS/cfg_dyno.asm
@@ -28,8 +28,9 @@ INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280RC|Z280ZZ]
+MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
 RAMBIAS		.EQU	512		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
+RAMLOC		.EQU	19		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
diff --git a/Source/HBIOS/cfg_ezz80.asm b/Source/HBIOS/cfg_ezz80.asm
index 78cb75a6..77bf5c87 100644
--- a/Source/HBIOS/cfg_ezz80.asm
+++ b/Source/HBIOS/cfg_ezz80.asm
@@ -28,7 +28,7 @@ INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280RC|Z280ZZ]
+MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
diff --git a/Source/HBIOS/cfg_master.asm b/Source/HBIOS/cfg_master.asm
index 2dff0c7c..8cb58185 100644
--- a/Source/HBIOS/cfg_master.asm
+++ b/Source/HBIOS/cfg_master.asm
@@ -25,8 +25,9 @@ INTMODE		.EQU	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.SET	MM_NONE		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280RC|Z280ZZ]
+MEMMGR		.SET	MM_NONE		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
 RAMBIAS		.EQU	0		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
+RAMLOC		.EQU	19		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
 MPCL_RAM	.EQU	$78		; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
 MPCL_ROM	.EQU	$7C		; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
@@ -40,7 +41,8 @@ Z180_CLKDIV	.EQU	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
 Z180_MEMWAIT	.EQU	0		; Z180: MEMORY WAIT STATES (0-3)
 Z180_IOWAIT	.EQU	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
 ;
-Z280_MEMWAIT	.EQU	0		; Z280: MEMORY WAIT STATES (0-3)
+Z280_MEMLOWAIT	.EQU	0		; Z280: LOW 8MB MEMORY WAIT STATES (0-3)
+Z280_MEMHIWAIT	.EQU	0		; Z280: HIGH 8MB MEMORY WAIT STATES (0-3)
 Z280_IOWAIT	.EQU	1		; Z280: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
 Z280_INTWAIT	.EQU	0		; Z280: INT ACK WAIT STATUS (0-3)
 ;
diff --git a/Source/HBIOS/cfg_mk4.asm b/Source/HBIOS/cfg_mk4.asm
index 0ba2c819..fc39c4c6 100644
--- a/Source/HBIOS/cfg_mk4.asm
+++ b/Source/HBIOS/cfg_mk4.asm
@@ -28,8 +28,9 @@ INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280RC|Z280ZZ]
+MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
 RAMBIAS		.EQU	512		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
+RAMLOC		.EQU	19		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
 ;
 Z180_BASE	.EQU	$40		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
 Z180_CLKDIV	.EQU	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
diff --git a/Source/HBIOS/cfg_n8.asm b/Source/HBIOS/cfg_n8.asm
index b608d298..0401c625 100644
--- a/Source/HBIOS/cfg_n8.asm
+++ b/Source/HBIOS/cfg_n8.asm
@@ -28,8 +28,9 @@ INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_N8		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280RC|Z280ZZ]
+MEMMGR		.EQU	MM_N8		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
 RAMBIAS		.EQU	0		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
+RAMLOC		.EQU	0		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
 ;
 Z180_BASE	.EQU	$40		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
 Z180_CLKDIV	.EQU	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
diff --git a/Source/HBIOS/cfg_rcz180.asm b/Source/HBIOS/cfg_rcz180.asm
index 27009182..cc60a55b 100644
--- a/Source/HBIOS/cfg_rcz180.asm
+++ b/Source/HBIOS/cfg_rcz180.asm
@@ -28,8 +28,9 @@ INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280RC|Z280ZZ]
+MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
 RAMBIAS		.EQU	512		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
+RAMLOC		.EQU	19		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
diff --git a/Source/HBIOS/cfg_rcz280.asm b/Source/HBIOS/cfg_rcz280.asm
index 24426f23..19fd27b4 100644
--- a/Source/HBIOS/cfg_rcz280.asm
+++ b/Source/HBIOS/cfg_rcz280.asm
@@ -28,14 +28,17 @@ INTMODE		.EQU	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280RC|Z280ZZ]
+MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
+RAMBIAS		.EQU	512		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
+RAMLOC		.EQU	19		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_3	.EQU	$7B		; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
 MPGENA		.EQU	$7C		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
 ;
-Z280_MEMWAIT	.EQU	0		; Z280: MEMORY WAIT STATES (0-3)
+Z280_MEMLOWAIT	.EQU	0		; Z280: LOW 8MB MEMORY WAIT STATES (0-3)
+Z280_MEMHIWAIT	.EQU	0		; Z280: HIGH 8MB MEMORY WAIT STATES (0-3)
 Z280_IOWAIT	.EQU	1		; Z280: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
 Z280_INTWAIT	.EQU	0		; Z280: INT ACK WAIT STATUS (0-3)
 ;
diff --git a/Source/HBIOS/cfg_rcz80.asm b/Source/HBIOS/cfg_rcz80.asm
index 3ccce22e..138ca616 100644
--- a/Source/HBIOS/cfg_rcz80.asm
+++ b/Source/HBIOS/cfg_rcz80.asm
@@ -28,7 +28,7 @@ INTMODE		.EQU	1		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280RC|Z280ZZ]
+MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
diff --git a/Source/HBIOS/cfg_sbc.asm b/Source/HBIOS/cfg_sbc.asm
index 48b1c3c1..0ccbbd77 100644
--- a/Source/HBIOS/cfg_sbc.asm
+++ b/Source/HBIOS/cfg_sbc.asm
@@ -28,7 +28,7 @@ INTMODE		.EQU	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_SBC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280RC|Z280ZZ]
+MEMMGR		.EQU	MM_SBC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
 MPCL_RAM	.EQU	$78		; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
 MPCL_ROM	.EQU	$7C		; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
 ;
diff --git a/Source/HBIOS/cfg_scz180.asm b/Source/HBIOS/cfg_scz180.asm
index 96f93de4..0acf5a2a 100644
--- a/Source/HBIOS/cfg_scz180.asm
+++ b/Source/HBIOS/cfg_scz180.asm
@@ -28,8 +28,9 @@ INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280RC|Z280ZZ]
+MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
 RAMBIAS		.EQU	512		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
+RAMLOC		.EQU	19		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
 ;
 Z180_BASE	.EQU	$C0		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
 Z180_CLKDIV	.EQU	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
diff --git a/Source/HBIOS/cfg_zeta.asm b/Source/HBIOS/cfg_zeta.asm
index 77863aff..86c283a9 100644
--- a/Source/HBIOS/cfg_zeta.asm
+++ b/Source/HBIOS/cfg_zeta.asm
@@ -28,7 +28,7 @@ INTMODE		.EQU	0		; INTERRUPT MODE: 0=NONE, 1=MODE 1, 2=MODE 2
 DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_SBC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280RC|Z280ZZ]
+MEMMGR		.EQU	MM_SBC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
 MPCL_RAM	.EQU	$78		; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
 MPCL_ROM	.EQU	$7C		; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
 ;
diff --git a/Source/HBIOS/cfg_zeta2.asm b/Source/HBIOS/cfg_zeta2.asm
index 801aeebb..0e5f226c 100644
--- a/Source/HBIOS/cfg_zeta2.asm
+++ b/Source/HBIOS/cfg_zeta2.asm
@@ -28,7 +28,7 @@ INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280RC|Z280ZZ]
+MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm
index 102c5a70..a0ca1453 100644
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@@ -64,6 +64,10 @@
 ;  - dsky.asm
 ;  - unlzsa2s.asm
 ;
+; TODO:
+;  - DELAY_INIT MAKES A SYSTEM CALL VIA RST 08 EARLIER THAN
+;    WE REALLY EXPECT SYSTEM CALLS TO HAPPEN
+;
 ; INCLUDE GENERIC STUFF
 ;
 #INCLUDE "std.asm"
@@ -134,17 +138,19 @@ MODCNT	.SET	MODCNT + 1
 	.ECHO	"*** ERROR: INVALID INTMODE SETTING!!!\n"
 	!!!	; FORCE AN ASSEMBLY ERROR
 #ENDIF
+;
 #IF (INTMODE == 3)
   #IF (CPUFAM != CPU_Z280)
 	.ECHO	"*** ERROR: INTMODE 3 REQUIRES Z280 FAMILY CPU!!!\n"
 	!!!	; FORCE AN ASSEMBLY ERROR
   #ENDIF
-  #IF ((MEMMGR != MM_Z280RC) & (MEMMGR != MM_Z280ZZ))
+  #IF (MEMMGR != MM_Z280)
 	.ECHO	"*** ERROR: INTMODE 3 REQUIRES Z280 MEMORY MANAGER!!!\n"
 	!!!	; FORCE AN ASSEMBLY ERROR
   #ENDIF
 #ENDIF
-  #IF ((MEMMGR == MM_Z280RC) | (MEMMGR == MM_Z280ZZ))
+;
+#IF (MEMMGR == MM_Z280)
   #IF (INTMODE != 3)
 	.ECHO	"*** ERROR: Z280 MEMORY MANAGER REQUIRES INTMODE 3!!!\n"
 	!!!	; FORCE AN ASSEMBLY ERROR
@@ -312,7 +318,7 @@ HBX_IDENT:
 ; WARNING: HBX_INVOKE IS *NOT* REENTRANT!
 ;
 HBX_INVOKE:
-
+;
 #IF (HBIOS_MUTEX == TRUE)
 	PUSH	HL			; SAVE HL
 	LD	HL,HB_LOCK		; POINT TO LOCK
@@ -320,55 +326,55 @@ HBX_INVOKE:
 	JR	C,$-2			; KEEP TRYING ON FAILURE
 	POP	HL			; RESTORE HL
 #ENDIF
-
-#IF ((MEMMGR == MM_Z280RC) | (MEMMGR == MM_Z280ZZ))
-
+;
+#IF (MEMMGR == MM_Z280)
+;
 	LD	A,(HB_CURBNK)		; GET CURRENT BANK
 	LD	(HB_INVBNK),A		; SAVE INVOCATION BANK
-	
+;	
 	LD	A,BID_BIOS		; HBIOS BANK
 	LD	(HB_CURBNK),A		; SET AS CURRENT BANK
-
+;
 	.DB	$ED,$71			; SC
 	.DW	HB_DISPATCH		; SC PARAMETER
-	
+;	
 	PUSH	AF
 	LD	A,(HB_INVBNK)
 	LD	(HB_CURBNK),A
 	POP	AF
-
+;
 #ELSE
-
+;
 	LD	(HBX_INVSP),SP		; SAVE ORIGINAL STACK FRAME
 	LD	SP,HBX_BUF_END		; BORROW HBX_BUF FOR TEMP STACK
-
+;
 	LD	A,(HB_CURBNK)		; GET CURRENT BANK
 	LD	(HB_INVBNK),A		; SAVE INVOCATION BANK
-
+;
 	LD	A,BID_BIOS		; HBIOS BANK
 	CALL	HBX_BNKSEL		; SELECT IT
 	LD	SP,HB_STACK		; NOW USE FULL HBIOS STACK IN HBIOS BANK
-
+;
 	CALL	HB_DISPATCH		; CALL HBIOS FUNCTION DISPATCHER
-
+;
 	LD	SP,HBX_BUF_END		; BORROW HBX_BUF FOR TEMP STACK
 	PUSH	AF			; SAVE AF (FUNCTION RETURN)
-
+;
 	LD	A,(HB_INVBNK)		; LOAD ORIGINAL BANK
 	CALL	HBX_BNKSEL		; SELECT IT
 	POP	AF			; RESTORE AF
 	LD	SP,0			; RESTORE ORIGINAL STACK FRAME
 HBX_INVSP	.EQU	$ - 2
-
+;
 #ENDIF
-
+;
 #IF (HBIOS_MUTEX == TRUE)
 	PUSH	HL			; SAVE HL
 	LD	HL,HB_LOCK		; POINT TO LOCK
 	LD	(HL),$FE		; RELEASE MUTEX LOCK
 	POP	HL			; RESTORE HL
 #ENDIF
-
+;
 	RET				; RETURN TO CALLER
 ;
 ;;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
@@ -423,7 +429,8 @@ HBX_ROM:
 	INC	A			;
 	OUT	(MPGSEL_1),A		; BANK_1: 16K - 32K
 #IF (CPUFAM == CPU_Z280)
-	.DB	$ED,$65			; PCACHE
+	;.DB	$ED,$65			; PCACHE
+	PCACHE
 #ENDIF
 	RET				; DONE
 #ENDIF
@@ -462,7 +469,7 @@ HBX_BNKSEL1:
 	RET				; DONE
 #ENDIF
 ;
-#IF ((MEMMGR == MM_Z280RC) | (MEMMGR == MM_Z280ZZ))
+#IF (MEMMGR == MM_Z280)
 	PUSH	BC			; SAVE BC
 	PUSH	HL			; SAVE HL
 	LD	B,$00			; FIRST USER PDR
@@ -499,7 +506,7 @@ HBX_ROM:
 ;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
 ;
 HBX_BNKCPY:
-#IF ((MEMMGR == MM_Z280RC) | (MEMMGR == MM_Z280ZZ))
+#IF (MEMMGR == MM_Z280)
 	.DB	$ED,$71			; SC
 	.DW	Z280_BNKCPY		; SC PARAMETER
 	RET
@@ -508,7 +515,7 @@ HBX_BNKCPY:
 	PUSH	HL
 	PUSH	BC
 	LD	C,Z280_MSR
-	.DB	$ED,$66			; LDCTL HL,(C)
+	LDCTL	HL,(C)
 	POP	BC
 	EX	(SP),HL
 	HB_DI
@@ -550,7 +557,7 @@ HBX_BC_SP	.EQU	$ - 2		; ... TO ORIGINAL VALUE
 	EX	(SP),HL			; SAVE HL, RECOVER MSR
 	PUSH	BC			; SAVE BC
 	LD	C,Z280_MSR
-	.DB	$ED,$6E			; LDCTL (C),HL
+	LDCTL	(C),HL
 	POP	BC			; RECOVER BC
 	POP	HL			; RECOVER HL
   #ELSE
@@ -588,21 +595,22 @@ HBX_BC_ITER:
 ;
 HBX_BNKCALL:
 ;
-#IF ((MEMMGR == MM_Z280RC) | (MEMMGR == MM_Z280ZZ))
+#IF (MEMMGR == MM_Z280)
 	CP	BID_BIOS		; CALLING HBIOS?
 	JR	NZ,HBX_BNKCALL3		; NOPE, DO NORMAL PROCESSING
 	.DB	$ED,$71			; SC
 	.DW	HBX_BNKCALL2		; CALL HERE IN SYSTEM MODE
 	RET				; THEN RETURN
-
+;
 HBX_BNKCALL2:
 	HB_EI				; INTS ARE OK
 	LD	(HBX_BNKCALL_GO+1),IX	; SETUP DEST ADR
-	.DB	$ED,$65			; PCACHE (CRITICAL!!!)
+	;.DB	$ED,$65			; PCACHE (CRITICAL!!!)
+	PCACHE				; CRITICAL!!!
 HBX_BNKCALL_GO:
 	JP	$FFFF			; DO THE REAL WORK AND RETURN
 #ENDIF
-
+;
 HBX_BNKCALL3:
 	LD	(HBX_BNKCALL_BNK+1),A	; STUFF TARGET BANK TO CALL INTO CODE BELOW
 	LD	(HBX_BNKCALL_ADR+1),IX	; STUFF ADDRESS TO CALL INTO CODE BELOW
@@ -656,7 +664,7 @@ HBX_POKE:
 ;
 HBX_PPRET:
 	POP	AF
-#IF ((MEMMGR == MM_Z280RC) | (MEMMGR == MM_Z280ZZ))
+#IF (MEMMGR == MM_Z280)
 	LD	A,(HB_INVBNK)		; SPECIAL CASE FOR Z280 MEM MGR
 #ENDIF
 	CALL	HBX_BNKSEL
@@ -753,7 +761,7 @@ INT_IM1:
 ;
 HBX_INT:	; COMMON INTERRUPT ROUTING CODE
 ;
-  #IF ((MEMMGR == MM_Z280RC) | (MEMMGR == MM_Z280ZZ))
+  #IF (MEMMGR == MM_Z280)
 ;
 	EX	(SP),HL			; SAVE HL AND GET INT JP TABLE OFFSET
 	
@@ -778,7 +786,7 @@ HBX_INT:	; COMMON INTERRUPT ROUTING CODE
 	; BURN THE REASON CODE
 	EX	(SP),HL			; HL TO STK, RC TO HL
 	POP	HL			; RESTORE HL
-
+;
 	CALL	HBX_RETI		; RETI FOR Z80 PERIPHERALS
 	.DB	$ED,$55			; RETIL
 ;
@@ -964,7 +972,7 @@ HB_IVT0F:	JP	HB_BADINT \ .DB 0
 ;
 HB_START:
 #IFDEF APPBOOT
-  #IF ((MEMMGR == MM_Z280RC) | (MEMMGR == MM_Z280ZZ))
+  #IF (MEMMGR == MM_Z280)
 	LD	A,%00000001
 	OUT	(DIAGPORT),A
 	LD	DE,Z280_BOOTERR
@@ -994,15 +1002,14 @@ Z280_BOOTERR	.TEXT	"\r\n\r\n*** Application mode boot not supported under Z280 n
 	; SET MAXIMUM I/O WAIT STATES FOR NOW
 	LD	C,Z280_BTCR		; BUS TIMING AND CONTROL REGISTER
 	LD	HL,$0033		; 3 I/O WAIT STATES ADDED
-	.DB	$ED,$6E			; LDCTL	(C),HL
-
-  #IF ((MEMMGR == MM_Z280RC) | (MEMMGR == MM_Z280ZZ))
-  
-	; INITIALIZE MMU
+	LDCTL	(C),HL
+;
 	; START BY SELECTING I/O PAGE $FF
 	LD	L,$FF			; MMU AND DMA PAGE I/O REG IS $FF
 	LD	C,Z280_IOPR		; REG C POINTS TO I/O PAGE REGISTER
-	.DB	$ED,$6E			; LDCTL	(C),HL
+	LDCTL	(C),HL
+;
+  #IF (MEMMGR == MM_Z280)
 ;
 	; INITIALIZE ALL OF THE SYSTEM PAGE DESCRIPTORS WITH BLOCK MOVE
 	XOR	A			; FIRST USER PDR
@@ -1028,22 +1035,17 @@ Z280_BOOTERR	.TEXT	"\r\n\r\n*** Application mode boot not supported under Z280 n
 	; DISABLE MEMORY REFRESH CYCLES
 	LD	A,$08			; DISABLED
 	OUT	(Z280_RRR),A		; SET REFRESH RATE REGISTER
-;	
-	; RESTORE I/O PAGE TO $00
-	LD	L,$00			; NORMAL I/O REG IS $00
-	LD	C,Z280_IOPR		; REG C POINTS TO I/O PAGE REGISTER
-	.DB	$ED,$6E			; LDCTL	(C),HL
 ;
 	; CONFIGURE Z280 INT/TRAP VECTOR TABLE POINTER REGISTER
 	; WILL POINT TO ROM COPY FOR NOW, UPDATED TO RAM LATER ON
 	LD	C,Z280_VPR
 	LD	HL,Z280_IVT >> 8	; TOP 16 BITS OF PHYSICAL ADR OF IVT
-	.DB	$ED,$6E			; LDCTL	(C),HL
+	LDCTL	(C),HL
 ;
-	JP	Z280_INITZ		; JUMP TO CODE CONTINUATION
+	JR	Z280_INITZ		; JUMP TO CODE CONTINUATION
 ;
     #IF (($ % 2) == 1)
-	; BYTE ALIGN THE TABLE
+	; WORD ALIGN THE TABLE
 	.DB	0
     #ENDIF
 ;
@@ -1058,30 +1060,23 @@ Z280_BOOTPDRTBL:
 	.DW	($006 << 4) | $A
 	.DW	($007 << 4) | $A
 	; UPPER 32 K (COMMON)
-;
-    #IF (MEMMGR == MM_Z280ZZ)
-	.DW	($878 << 4) | $A
-	.DW	($879 << 4) | $A
-	.DW	($87A << 4) | $A
-	.DW	($87B << 4) | $A
-	.DW	($87C << 4) | $A
-	.DW	($87D << 4) | $A
-	.DW	($87E << 4) | $A
-	.DW	($87F << 4) | $A
-    #ELSE
-	.DW	($0F8 << 4) | $A
-	.DW	($0F9 << 4) | $A
-	.DW	($0FA << 4) | $A
-	.DW	($0FB << 4) | $A
-	.DW	($0FC << 4) | $A
-	.DW	($0FD << 4) | $A
-	.DW	($0FE << 4) | $A
-	.DW	($0FF << 4) | $A
-    #ENDIF
+	.DW	(($78 + (1 << (RAMLOC - 12))) << 4) | $A
+	.DW	(($79 + (1 << (RAMLOC - 12))) << 4) | $A
+	.DW	(($7A + (1 << (RAMLOC - 12))) << 4) | $A
+	.DW	(($7B + (1 << (RAMLOC - 12))) << 4) | $A
+	.DW	(($7C + (1 << (RAMLOC - 12))) << 4) | $A
+	.DW	(($7D + (1 << (RAMLOC - 12))) << 4) | $A
+	.DW	(($7E + (1 << (RAMLOC - 12))) << 4) | $A
+	.DW	(($7F + (1 << (RAMLOC - 12))) << 4) | $A
 ;
 Z280_INITZ:
 ;
   #ENDIF 
+;
+	; RESTORE I/O PAGE TO $00
+	LD	L,$00			; NORMAL I/O REG IS $00
+	LD	C,Z280_IOPR		; REG C POINTS TO I/O PAGE REGISTER
+	LDCTL	(C),HL
 ;	
 #ENDIF
 ;
@@ -1238,11 +1233,10 @@ Z280_INITZ:
 ;
 ; TRANSITION TO HBIOS IN RAM BANK
 ;
-#IF ((MEMMGR == MM_Z280RC) | (MEMMGR == MM_Z280ZZ))
+#IF (MEMMGR == MM_Z280)
 	LD	A,BID_BIOS
 	LD	B,$10			; FIRST SYSTEM PDR
 	CALL	Z280_BNKSEL
-;
 	JR	HB_START1
 #ELSE
 	LD	A,BID_BIOS		; BIOS BANK ID
@@ -1266,15 +1260,13 @@ HB_START1:				; BNKCALL ARRIVES HERE, BUT NOW RUNNING IN RAM BANK
 	LD	A,TRUE			; ACCUM := TRUE
 	LD	(HB_RAMFLAG),A		; SET RAMFLAG
 ;
-#IF ((MEMMGR == MM_Z280RC) | (MEMMGR == MM_Z280ZZ))
+#IF (MEMMGR == MM_Z280)
 	; NOW POINT TO RAM COPY OF Z280 INT/TRAP TABLE
+	; HL IS TOP 16 BITS OF PHYSICAL ADDRESS OF IVT
+	; IVT *MUST* BE ON A 4K BOUNDARY
 	LD	C,Z280_VPR
-  #IF (MEMMGR == MM_Z280ZZ)
-	LD	HL,$8680+(Z280_IVT >> 8)	; TOP 16 BITS OF PHYSICAL ADR OF IVT
-  #ELSE
-	LD	HL,$0E80+(Z280_IVT >> 8)	; TOP 16 BITS OF PHYSICAL ADR OF IVT
-  #ENDIF
-	.DB	$ED,$6E			; LDCTL	(C),HL
+	LD	HL,0 + ((((BID_BIOS & $7F) * 8) + (1 << (RAMLOC - 12))) << 4) + (Z280_IVT >> 8)
+	LDCTL	(C),HL
 #ENDIF
 ;
 ; IF APPBOOT, WE NEED TO FIX UP A FEW THINGS IN PAGE ZERO
@@ -1284,7 +1276,7 @@ HB_START1:				; BNKCALL ARRIVES HERE, BUT NOW RUNNING IN RAM BANK
 	; GET AND SAVE APP BOOT BANK ID
 	LD	A,(HBX_LOC - 2)
 	LD	(HB_APPBNK),A
-
+;
 	; MAKE SURE RST 08 VECTOR IS RIGHT
 	LD	A,$C3
 	LD	($0008),A
@@ -1513,21 +1505,22 @@ HB_CPU2:
 #IF (CPUFAM == CPU_Z280)
 ;
 	LD	C,Z280_BTCR		; BUS TIMING AND CONTROL REG
-	.DB	$ED,$66			; LDCTL	HL,(C)
+	LDCTL	HL,(C)
 	LD	A,L			; PUT IN A
-	AND	%00111100		; CLEAR DC AND I/O FIELDS
-	OR	Z280_INTWAIT << 6	; SET INT ACK WAIT STATES
-	OR	Z280_IOWAIT		; SET I/O WAIT STATES
+	AND	%00111100		; CLEAR DC,HM, AND IO FIELDS
+	OR	Z280_INTWAIT << 6	; SET INT ACK WAIT STATE BITS (DC)
+	OR	Z280_MEMHIWAIT << 2	; SET HIGH 8MB WAIT STATE BITS (HM)
+	OR	Z280_IOWAIT		; SET I/O WAIT STATE BITS
 	LD	L,A			; BACK TO L
-	.DB	$ED,$6E			; LDCTL	(C),HL
+	LDCTL	(C),HL
 ;
 	LD	C,Z280_BTIR		; BUS TIMING AND INIT REG
-	.DB	$ED,$66			; LDCTL	HL,(C)
+	LDCTL	HL,(C)
 	LD	A,L			; PUT IN A
-	AND	%11110011		; CLEAR LOW MEM WAIT STATES
-	OR	Z280_MEMWAIT << 2	; SET LOW MEM WAIT STATES
+	AND	%11110011		; CLEAR LM FIELD
+	OR	Z280_MEMLOWAIT << 2	; SET LOW 8MB WAIT STATE BITS
 	LD	L,A			; BACK TO L
-	.DB	$ED,$6E			; LDCTL	(C),HL
+	LDCTL	(C),HL
 ;
 #ENDIF
 ;
@@ -1550,9 +1543,9 @@ HB_CPU2:
 	; SETUP Z280 INT A FOR VECTORED INTERRUPTS
 	LD	HL,%0010000000000000
 	LD	C,Z280_ISR
-	.DB	$ED,$6E			; LDCTL (C),HL
+	LDCTL	(C),HL
 ;
-	.DB	$ED,$4E			; IM 3
+	IM	3
 ;
 #ENDIF
 ;
@@ -1629,10 +1622,10 @@ Z280_TC	.EQU	CPUOSC / 4 / 50 / 2	; TIME CONSTANT
 ;
 	; SELECT I/O PAGE $FE
 	LD	C,Z280_IOPR		; I/O PAGE REGISTER
-	.DB	$ED,$66			; LDCTL HL,(C) ; GET CURRENT I/O PAGE
+	LDCTL	HL,(C)			; GET CURRENT I/O PAGE
 	PUSH	HL			; SAVE IT
 	LD	L,$FE			; I/O PAGE $FE
-	.DB	$ED,$6E			; LDCTL (C),HL
+	LDCTL	(C),HL
 ;
 	LD	A,%10100000		; CONFIG: C, RE, IE
 	OUT	(Z280_CT0_CFG),A	; SET C/T 0
@@ -1647,7 +1640,7 @@ Z280_TC	.EQU	CPUOSC / 4 / 50 / 2	; TIME CONSTANT
 	; RESTORE I/O PAGE
 	LD	C,Z280_IOPR		; I/O PAGE REGISTER
 	POP	HL			; RESTORE I/O PAGE
-	.DB	$ED,$6E			; LDCTL (C),HL
+	LDCTL	(C),HL
 ;
   #ENDIF
 ;
@@ -1840,7 +1833,7 @@ HB_SPDTST:
 	CALL	PRTSTRD
 	.TEXT	", BUS @ $"
 	LD	C,Z280_BTIR		; BUS TIMING AND CTL REG
-	.DB	$ED,$66			; LDCTL	HL,(C)
+	LDCTL	HL,(C)
 	LD	A,L			; MOVE TO A
 	AND	%00000011		; ISOLATE CS FIELD
 	LD	HL,(CB_CPUKHZ)		; GET CPU SPEED
@@ -1865,16 +1858,25 @@ HB_Z280BUS1:
 ; DISPLAY CPU CONFIG
 ;
 	CALL	NEWLINE
+	
+#IF (CPUFAM == CPU_Z280)
+	LD	A,Z280_MEMLOWAIT
+	CALL	PRTDECB
+	CALL	PRTSTRD
+	.TEXT	" MEM LO W/S, $"
+	LD	A,Z280_MEMHIWAIT
+	CALL	PRTDECB
+	CALL	PRTSTRD
+	.TEXT	" MEM HI W/S, $"
+#ELSE
 	XOR	A
-#IF (CPUFAM == CPU_Z180)
+  #IF (CPUFAM == CPU_Z180)
 	LD	A,Z180_MEMWAIT
-#ENDIF
-#IF (CPUFAM == CPU_Z280)
-	LD	A,Z280_MEMWAIT
-#ENDIF
+  #ENDIF
 	CALL	PRTDECB
 	CALL	PRTSTRD
 	.TEXT	" MEM W/S, $"
+#ENDIF
 	LD	A,1
 #IF (CPUFAM == CPU_Z180)
 	LD	A,Z180_IOWAIT + 1
@@ -1918,14 +1920,11 @@ HB_Z280BUS1:
 #IF (MEMMGR == MM_Z180)
 	.TEXT	"Z180$"
 #ENDIF
+#IF (MEMMGR == MM_Z280)
+	.TEXT	"Z280$"
+#ENDIF
 #IF (MEMMGR == MM_ZRC)
 	.TEXT	"ZRC$"
-#ENDIF
-#IF (MEMMGR == MM_Z280RC)
-	.TEXT	"Z280RC$"
-#ENDIF
-#IF (MEMMGR == MM_Z280ZZ)
-	.TEXT	"Z280ZZ$"
 #ENDIF
 	CALL	PRTSTRD
 	.TEXT	" MMU$"
@@ -1947,22 +1946,22 @@ HB_Z280BUS1:
 	PRTS("Z280: $")
 	PRTS("MSR=$")
 	LD	C,Z280_MSR		; MASTER STATUS REGISTER
-	.DB	$ED,$66			; LDCTL	HL,(C)
+	LDCTL	HL,(C)
 	CALL	PRTHEXWORDHL
 	CALL	PC_SPACE
 	PRTS("BTCR=$")
 	LD	C,Z280_BTCR		; BUS TIMING AND CONTROL REGISTER
-	.DB	$ED,$66			; LDTCL	HL,(C)
+	LDCTL	HL,(C)
 	CALL	PRTHEXWORDHL
 	CALL	PC_SPACE
 	PRTS("BTIR=$")
 	LD	C,Z280_BTIR		; BUS TIMING AND CONTROL REGISTER
-	.DB	$ED,$66			; LDTCL	HL,(C)
+	LDCTL	HL,(C)
 	CALL	PRTHEXWORDHL
 	CALL	PC_SPACE
 	PRTS("CCR=$")
 	LD	C,Z280_CCR		; CACHE CONTROL REGISTER
-	.DB	$ED,$66			; LDTCL	HL,(C)
+	LDCTL	HL,(C)
 	CALL	PRTHEXWORDHL
 #ENDIF
 ;
@@ -2080,26 +2079,26 @@ INITSYS3:
 ;
 INITSYS4:
 ;
-#IF ((MEMMGR == MM_Z280RC) | (MEMMGR == MM_Z280ZZ))
+#IF (MEMMGR == MM_Z280)
 	; LEAVE SYSTEM MODE STACK POINTING TO AN OK PLACE
 	LD	SP,HB_STACK		; NOW USE REAL SYSTEM STACK LOC
-	
+;
 	HB_DI				; NOT SURE THIS IS NEEDED
-
+;
 	; ACTIVATE THE CORRECT USER MODE BANK
 	LD	A,(HB_CURBNK)		; GET CURRENT BANK
 	CALL	HBX_BNKSEL
-
+;
 	; PRESET THE USER MODE STACK
 	LD	HL,HBX_LOC
-	.DB	$ED,$8F			; LDCTL	USP,HL
-
+	LDCTL	USP,HL
+;
 	HB_EI				; NOT SURE THIS IS NEEDED
-
+;
 	; SWITCH TO USER MODE NOW
 	LD	C,Z280_MSR
 	LD	HL,$407F
-	.DB	$ED,$6E			; LDCTL	(C),HL
+	LDCTL	(C),HL
 #ENDIF
 ;
 ; CHAIN TO OS LOADER
@@ -2347,7 +2346,7 @@ IDLE:
 ;
 HB_DISPATCH:
 ;
-#IF ((MEMMGR == MM_Z280RC) | (MEMMGR == MM_Z280ZZ))
+#IF (MEMMGR == MM_Z280)
 	; FOR Z280 MEMMGR, WE DISPATCH VIA THE Z280 SYSCALL.
 	; THE SYSCALL MECHANISM WILL CLEAR INTERRUPTS.  IN
 	; GENERAL, INTERRUPTS ARE OK DURING API PROCESSING,
@@ -2930,7 +2929,7 @@ SYS_RESINT:
 SYS_RESWARM:
 	CALL	SYS_RESINT
 ;	
-#IF ((MEMMGR == MM_Z280RC) | (MEMMGR == MM_Z280ZZ))
+#IF (MEMMGR == MM_Z280)
 	JP	INITSYS4
 #ELSE
 	; PERFORM BANK CALL TO OS IMAGES BANK IN ROM
@@ -2969,7 +2968,7 @@ SYS_VER:
 ;   CALLER MUST ESTABLISH UPPER MEMORY STACK BEFORE INVOKING THIS FUNCTION!
 ;
 SYS_SETBNK:
-#IF ((MEMMGR == MM_Z280RC) | (MEMMGR == MM_Z280ZZ))
+#IF (MEMMGR == MM_Z280)
 	; FOR Z280 MEMMGR, WE ARE IN SYSTEM MODE HERE, SO WE CAN UPDATE
 	; THE USER MODE BANK WITHOUT IMPACTING THE RUNNING CODE.  IT
 	; TAKE EFFECT UPON RETURN TO USER MODE.
@@ -3356,7 +3355,7 @@ SYS_PEEK:
   #IF (CPUFAM == CPU_Z280)
 	PUSH	IY
 	LD	C,Z280_MSR
-	.DB	$FD,$ED,$66		; LDCTL	IY,(C)
+	LDCTL	IY,(C)
 	PUSH	IY
 	HB_DI
   #ELSE
@@ -3370,7 +3369,7 @@ SYS_PEEK:
   #IF (CPUFAM == CPU_Z280)
 	LD	C,Z280_MSR
 	POP	IY
-	.DB	$FD,$ED,$6E		; LDCTL	(C),IY
+	LDCTL	(C),IY
 	POP	IY
   #ELSE
 	POP	AF			; RECALL INITIAL INTERRUPT STATUS
@@ -3393,7 +3392,7 @@ SYS_POKE:
   #IF (CPUFAM == CPU_Z280)
 	PUSH	IY
 	LD	C,Z280_MSR
-	.DB	$FD,$ED,$66		; LDCTL	IY,(C)
+	LDCTL	IY,(C)
 	PUSH	IY
 	HB_DI
   #ELSE
@@ -3407,7 +3406,7 @@ SYS_POKE:
   #IF (CPUFAM == CPU_Z280)
 	LD	C,Z280_MSR
 	POP	IY
-	.DB	$FD,$ED,$6E		; LDCTL	(C),IY
+	LDCTL	(C),IY
 	POP	IY
   #ELSE
 	POP	AF			; RECALL INITIAL INTERRUPT STATUS
@@ -3572,8 +3571,8 @@ HB_IM1PTR	.DW	HB_IVT		; POINTER FOR NEXT IM1 ENTRY
 ;
 ;
 ;
-#IF ((MEMMGR == MM_Z280RC) | (MEMMGR == MM_Z280ZZ))
-
+#IF (MEMMGR == MM_Z280)
+;
 Z280_TIMINT:
 	; DISCARD REASON CODE
 	INC	SP
@@ -3590,10 +3589,10 @@ Z280_TIMINT:
 ;
 	; SELECT I/O PAGE $FE (SAVING PREVIOUS VALUE)
 	LD	C,Z280_IOPR		; REG C POINTS TO I/O PAGE REGISTER
-	.DB	$ED,$66			; LDCTL HL,(C) ; GET CURRENT I/O PAGE
+	LDCTL	HL,(C)			; GET CURRENT I/O PAGE
 	PUSH	HL			; SAVE IT
 	LD	L,$FE			; NEW COUNTER/TIMER I/O PAGE
-	.DB	$ED,$6E			; LDCTL	(C),HL
+	LDCTL	(C),HL
 ;
 	; CLEAR END OF COUNT CONDITION TO RESET INTERRUPT
 	IN	A,(Z280_CT0_CMDST)	; GET STATUS
@@ -3603,7 +3602,7 @@ Z280_TIMINT:
 	; RESTORE I/O PAGE
 	LD	C,Z280_IOPR		; REG C POINTS TO I/O PAGE REGISTER
 	POP	HL			; RECOVER ORIGINAL I/O PAGE
-	.DB	$ED,$6E			; LDCTL	(C),HL
+	LDCTL	(C),HL
 ;
 	; RESTORE REGISTERS
 	POP	HL
@@ -3699,7 +3698,7 @@ HB_BADINTCNT	.DB	0
 ;
 ; Z280 BAD INT HANDLER
 ;
-#IF ((MEMMGR == MM_Z280RC) | (MEMMGR == MM_Z280ZZ))
+#IF (MEMMGR == MM_Z280)
 ;
 Z280_BADINT:
 	; SAVE REASON CODE FOR POSSIBLE RETURN VIA RETIL
@@ -3810,7 +3809,7 @@ Z280_ACCVIOSTR	.TEXT	"ACCESS VIOLATION $"
 ;
 ; Z280 PRIVILEGED INSTRUCTION HANDLER
 ;
-#IF ((MEMMGR == MM_Z280RC) | (MEMMGR == MM_Z280ZZ))
+#IF (MEMMGR == MM_Z280)
 ;
 Z280_PRIVINST:
 	; SAVE HL AND MSR FOR POSSIBLE RETURN VIA RETIL
@@ -3824,10 +3823,6 @@ Z280_PRIVINST:
 	PUSH	DE
 ;	
 	.DB	$ED,$96			; LDUP	A,(HL)
-	
-	;CALL	PC_LBKT
-	;CALL	PRTHEXBYTE
-	;CALL	PC_RBKT
 ;	
 	; HANDLE DI
 	CP	$F3			; DI?
@@ -4058,7 +4053,7 @@ HB_TMPREF	.DW	0
 ;   Z280 INTERRUPT VECTOR TABLE
 ;==================================================================================================
 ;
-#IF ((MEMMGR == MM_Z280RC) | (MEMMGR == MM_Z280ZZ))
+#IF (MEMMGR == MM_Z280)
 ;
 	; THE Z280 IVT MUST BE ON A 4K BOUNDARY.  IT HAS BEEN LOCATED
 	; HERE IN AN EFFORT TO MINIMIZE WASTED SPACE.  THERE SHOULD BE
@@ -4144,360 +4139,7 @@ Z280_IVT:
 ;
 ; Z280 BANK SELECTION (CALLED FROM PROXY)
 ;
-; THIS VERSION USES A MASSIVE (512 BYTE) TABLE TO OPTIMIZE THE
-; SPEED OF THE BANK SWITCH.  BY USING THE TABLE, IT IS POSSIBLE
-; EXECUTE THE CORE OF THE BANKSWITCH WITH A SINGLE OTIRW.
-;
-#IF ((MEMMGR == MM_Z280RC) | (MEMMGR == MM_Z280ZZ)) & FALSE
-;
-; REG A HAS BANK ID, REG B HAS INITIAL PDR TO PROGRAM
-; REGISTERS AF, BC, HL DESTROYED
-;
-Z280_BNKSEL:
-;
-	; SELECT I/O PAGE FOR MMU
-	LD	L,$FF			; MMU AT I/O PAGE $FF
-	LD	C,Z280_IOPR		; I/O PAGE REGISTER TO C
-	.DB	$ED,$6E			; LDCTL (C),HL
-;
-	; POINT HL TO STARTING ENTRY TO PROGRAM.
-	; OPTIMIZED TO ASSUME HL IS PAGE ALIGNED!
-	LD	H,Z280_PDRTBL >> 8
-	SLA	A
-	JR	NC,Z280_BNKSEL1
-	INC	H
-Z280_BNKSEL1:
-	RLCA
-	RLCA
-	RLCA
-	LD	L,A
-;
-Z280_BNKSEL2:
-	; POINT TO FIRST PDR TO PROGRAM
-	LD	A,B			; FIRST PDR TO PROG
-	OUT	(Z280_MMUPDRPTR),A	; SET THE PDR POINTER
-;
-	; PROGRAM 8 PDRS
-	LD	C,Z280_MMUBLKMOV	; PDR BLOCK MOVE PORT
-	LD	B,8			; PROGRAM 8 PDRS
-	.DB	$ED,$93			; OTIRW
-;	
-	; RESTORE I/O PAGE TO $00
-	LD	L,$00			; NORMAL I/O PAGE $00
-	LD	C,Z280_IOPR		; I/O PAGE REGISTER TO C
-	.DB	$ED,$6E			; LDCTL (C),HL
-;	
-	RET
-;
-#IF (($ & $FF) != 0)
-	; PAGE ALIGN THE TABLE
-	.FILL	$100 - ($ & $FF)
-#ENDIF
-;
-#IF (($ % 2) == 1)
-	; WORD ALIGN THE TABLE
-	.DB	0
-#ENDIF
-;
-Z280_PDRTBL:
-	; BANK $00
-	.DW	($000 << 4) | $A
-	.DW	($001 << 4) | $A
-	.DW	($002 << 4) | $A
-	.DW	($003 << 4) | $A
-	.DW	($004 << 4) | $A
-	.DW	($005 << 4) | $A
-	.DW	($006 << 4) | $A
-	.DW	($007 << 4) | $A
-	; BANK $01
-	.DW	($008 << 4) | $A
-	.DW	($009 << 4) | $A
-	.DW	($00A << 4) | $A
-	.DW	($00B << 4) | $A
-	.DW	($00C << 4) | $A
-	.DW	($00D << 4) | $A
-	.DW	($00E << 4) | $A
-	.DW	($00F << 4) | $A
-	; BANK $02
-	.DW	($010 << 4) | $A
-	.DW	($011 << 4) | $A
-	.DW	($012 << 4) | $A
-	.DW	($013 << 4) | $A
-	.DW	($014 << 4) | $A
-	.DW	($015 << 4) | $A
-	.DW	($016 << 4) | $A
-	.DW	($017 << 4) | $A
-	; BANK $03
-	.DW	($018 << 4) | $A
-	.DW	($019 << 4) | $A
-	.DW	($01A << 4) | $A
-	.DW	($01B << 4) | $A
-	.DW	($01C << 4) | $A
-	.DW	($01D << 4) | $A
-	.DW	($01E << 4) | $A
-	.DW	($01F << 4) | $A
-	; BANK $04
-	.DW	($020 << 4) | $A
-	.DW	($021 << 4) | $A
-	.DW	($022 << 4) | $A
-	.DW	($023 << 4) | $A
-	.DW	($024 << 4) | $A
-	.DW	($025 << 4) | $A
-	.DW	($026 << 4) | $A
-	.DW	($027 << 4) | $A
-	; BANK $05
-	.DW	($028 << 4) | $A
-	.DW	($029 << 4) | $A
-	.DW	($02A << 4) | $A
-	.DW	($02B << 4) | $A
-	.DW	($02C << 4) | $A
-	.DW	($02D << 4) | $A
-	.DW	($02E << 4) | $A
-	.DW	($02F << 4) | $A
-	; BANK $06
-	.DW	($030 << 4) | $A
-	.DW	($031 << 4) | $A
-	.DW	($032 << 4) | $A
-	.DW	($033 << 4) | $A
-	.DW	($034 << 4) | $A
-	.DW	($035 << 4) | $A
-	.DW	($036 << 4) | $A
-	.DW	($037 << 4) | $A
-	; BANK $07
-	.DW	($038 << 4) | $A
-	.DW	($039 << 4) | $A
-	.DW	($03A << 4) | $A
-	.DW	($03B << 4) | $A
-	.DW	($03C << 4) | $A
-	.DW	($03D << 4) | $A
-	.DW	($03E << 4) | $A
-	.DW	($03F << 4) | $A
-	; BANK $08
-	.DW	($040 << 4) | $A
-	.DW	($041 << 4) | $A
-	.DW	($042 << 4) | $A
-	.DW	($043 << 4) | $A
-	.DW	($044 << 4) | $A
-	.DW	($045 << 4) | $A
-	.DW	($046 << 4) | $A
-	.DW	($047 << 4) | $A
-	; BANK $09
-	.DW	($048 << 4) | $A
-	.DW	($049 << 4) | $A
-	.DW	($04A << 4) | $A
-	.DW	($04B << 4) | $A
-	.DW	($04C << 4) | $A
-	.DW	($04D << 4) | $A
-	.DW	($04E << 4) | $A
-	.DW	($04F << 4) | $A
-	; BANK $0A
-	.DW	($050 << 4) | $A
-	.DW	($051 << 4) | $A
-	.DW	($052 << 4) | $A
-	.DW	($053 << 4) | $A
-	.DW	($054 << 4) | $A
-	.DW	($055 << 4) | $A
-	.DW	($056 << 4) | $A
-	.DW	($057 << 4) | $A
-	; BANK $0B
-	.DW	($058 << 4) | $A
-	.DW	($059 << 4) | $A
-	.DW	($05A << 4) | $A
-	.DW	($05B << 4) | $A
-	.DW	($05C << 4) | $A
-	.DW	($05D << 4) | $A
-	.DW	($05E << 4) | $A
-	.DW	($05F << 4) | $A
-	; BANK $0C
-	.DW	($060 << 4) | $A
-	.DW	($061 << 4) | $A
-	.DW	($062 << 4) | $A
-	.DW	($063 << 4) | $A
-	.DW	($064 << 4) | $A
-	.DW	($065 << 4) | $A
-	.DW	($066 << 4) | $A
-	.DW	($067 << 4) | $A
-	; BANK $0D
-	.DW	($068 << 4) | $A
-	.DW	($069 << 4) | $A
-	.DW	($06A << 4) | $A
-	.DW	($06B << 4) | $A
-	.DW	($06C << 4) | $A
-	.DW	($06D << 4) | $A
-	.DW	($06E << 4) | $A
-	.DW	($06F << 4) | $A
-	; BANK $0E
-	.DW	($070 << 4) | $A
-	.DW	($071 << 4) | $A
-	.DW	($072 << 4) | $A
-	.DW	($073 << 4) | $A
-	.DW	($074 << 4) | $A
-	.DW	($075 << 4) | $A
-	.DW	($076 << 4) | $A
-	.DW	($077 << 4) | $A
-	; BANK $0F
-	.DW	($078 << 4) | $A
-	.DW	($079 << 4) | $A
-	.DW	($07A << 4) | $A
-	.DW	($07B << 4) | $A
-	.DW	($07C << 4) | $A
-	.DW	($07D << 4) | $A
-	.DW	($07E << 4) | $A
-	.DW	($07F << 4) | $A
-
-	; BANK $10
-	.DW	($080 << 4) | $A
-	.DW	($081 << 4) | $A
-	.DW	($082 << 4) | $A
-	.DW	($083 << 4) | $A
-	.DW	($084 << 4) | $A
-	.DW	($085 << 4) | $A
-	.DW	($086 << 4) | $A
-	.DW	($087 << 4) | $A
-	; BANK $11
-	.DW	($088 << 4) | $A
-	.DW	($089 << 4) | $A
-	.DW	($08A << 4) | $A
-	.DW	($08B << 4) | $A
-	.DW	($08C << 4) | $A
-	.DW	($08D << 4) | $A
-	.DW	($08E << 4) | $A
-	.DW	($08F << 4) | $A
-	; BANK $12
-	.DW	($090 << 4) | $A
-	.DW	($091 << 4) | $A
-	.DW	($092 << 4) | $A
-	.DW	($093 << 4) | $A
-	.DW	($094 << 4) | $A
-	.DW	($095 << 4) | $A
-	.DW	($096 << 4) | $A
-	.DW	($097 << 4) | $A
-	; BANK $13
-	.DW	($098 << 4) | $A
-	.DW	($099 << 4) | $A
-	.DW	($09A << 4) | $A
-	.DW	($09B << 4) | $A
-	.DW	($09C << 4) | $A
-	.DW	($09D << 4) | $A
-	.DW	($09E << 4) | $A
-	.DW	($09F << 4) | $A
-	; BANK $14
-	.DW	($0A0 << 4) | $A
-	.DW	($0A1 << 4) | $A
-	.DW	($0A2 << 4) | $A
-	.DW	($0A3 << 4) | $A
-	.DW	($0A4 << 4) | $A
-	.DW	($0A5 << 4) | $A
-	.DW	($0A6 << 4) | $A
-	.DW	($0A7 << 4) | $A
-	; BANK $15
-	.DW	($0A8 << 4) | $A
-	.DW	($0A9 << 4) | $A
-	.DW	($0AA << 4) | $A
-	.DW	($0AB << 4) | $A
-	.DW	($0AC << 4) | $A
-	.DW	($0AD << 4) | $A
-	.DW	($0AE << 4) | $A
-	.DW	($0AF << 4) | $A
-	; BANK $16
-	.DW	($0B0 << 4) | $A
-	.DW	($0B1 << 4) | $A
-	.DW	($0B2 << 4) | $A
-	.DW	($0B3 << 4) | $A
-	.DW	($0B4 << 4) | $A
-	.DW	($0B5 << 4) | $A
-	.DW	($0B6 << 4) | $A
-	.DW	($0B7 << 4) | $A
-	; BANK $17
-	.DW	($0B8 << 4) | $A
-	.DW	($0B9 << 4) | $A
-	.DW	($0BA << 4) | $A
-	.DW	($0BB << 4) | $A
-	.DW	($0BC << 4) | $A
-	.DW	($0BD << 4) | $A
-	.DW	($0BE << 4) | $A
-	.DW	($0BF << 4) | $A
-	; BANK $18
-	.DW	($0C0 << 4) | $A
-	.DW	($0C1 << 4) | $A
-	.DW	($0C2 << 4) | $A
-	.DW	($0C3 << 4) | $A
-	.DW	($0C4 << 4) | $A
-	.DW	($0C5 << 4) | $A
-	.DW	($0C6 << 4) | $A
-	.DW	($0C7 << 4) | $A
-	; BANK $19
-	.DW	($0C8 << 4) | $A
-	.DW	($0C9 << 4) | $A
-	.DW	($0CA << 4) | $A
-	.DW	($0CB << 4) | $A
-	.DW	($0CC << 4) | $A
-	.DW	($0CD << 4) | $A
-	.DW	($0CE << 4) | $A
-	.DW	($0CF << 4) | $A
-	; BANK $1A
-	.DW	($0D0 << 4) | $A
-	.DW	($0D1 << 4) | $A
-	.DW	($0D2 << 4) | $A
-	.DW	($0D3 << 4) | $A
-	.DW	($0D4 << 4) | $A
-	.DW	($0D5 << 4) | $A
-	.DW	($0D6 << 4) | $A
-	.DW	($0D7 << 4) | $A
-	; BANK $1B
-	.DW	($0D8 << 4) | $A
-	.DW	($0D9 << 4) | $A
-	.DW	($0DA << 4) | $A
-	.DW	($0DB << 4) | $A
-	.DW	($0DC << 4) | $A
-	.DW	($0DD << 4) | $A
-	.DW	($0DE << 4) | $A
-	.DW	($0DF << 4) | $A
-	; BANK $1C
-	.DW	($0E0 << 4) | $A
-	.DW	($0E1 << 4) | $A
-	.DW	($0E2 << 4) | $A
-	.DW	($0E3 << 4) | $A
-	.DW	($0E4 << 4) | $A
-	.DW	($0E5 << 4) | $A
-	.DW	($0E6 << 4) | $A
-	.DW	($0E7 << 4) | $A
-	; BANK $1D
-	.DW	($0E8 << 4) | $A
-	.DW	($0E9 << 4) | $A
-	.DW	($0EA << 4) | $A
-	.DW	($0EB << 4) | $A
-	.DW	($0EC << 4) | $A
-	.DW	($0ED << 4) | $A
-	.DW	($0EE << 4) | $A
-	.DW	($0EF << 4) | $A
-	; BANK $1E
-	.DW	($0F0 << 4) | $A
-	.DW	($0F1 << 4) | $A
-	.DW	($0F2 << 4) | $A
-	.DW	($0F3 << 4) | $A
-	.DW	($0F4 << 4) | $A
-	.DW	($0F5 << 4) | $A
-	.DW	($0F6 << 4) | $A
-	.DW	($0F7 << 4) | $A
-	; BANK $1F
-	.DW	($0F8 << 4) | $A
-	.DW	($0F9 << 4) | $A
-	.DW	($0FA << 4) | $A
-	.DW	($0FB << 4) | $A
-	.DW	($0FC << 4) | $A
-	.DW	($0FD << 4) | $A
-	.DW	($0FE << 4) | $A
-	.DW	($0FF << 4) | $A
-;
-#ENDIF
-;
-; Z280 BANK SELECTION (CALLED FROM PROXY)
-;
-; THIS VERSION IS SLOWER, BUT AVOIDS THE USE OF THE 512+
-; BYTE TABLE.
-;
-#IF ((MEMMGR == MM_Z280RC) | (MEMMGR == MM_Z280ZZ))
+#IF (MEMMGR == MM_Z280)
 ;
 ; REG A HAS BANK ID, REG B HAS INITIAL PDR TO PROGRAM
 ; REGISTERS AF, BC, HL DESTROYED
@@ -4505,40 +4147,24 @@ Z280_PDRTBL:
 Z280_BNKSEL:
 	; SELECT I/O PAGE $FE (SAVING PREVIOUS VALUE)
 	LD	C,Z280_IOPR		; REG C POINTS TO I/O PAGE REGISTER
-	.DB	$ED,$66			; LDCTL HL,(C) ; GET CURRENT I/O PAGE
+	LDCTL	HL,(C)			; GET CURRENT I/O PAGE
 	PUSH	HL			; SAVE IT
 	LD	L,$FF			; NEW I/O PAGE
-	.DB	$ED,$6E			; LDCTL	(C),HL
-;
-  #IF (MEMMGR == MM_Z280ZZ)
-;
+	LDCTL	(C),HL
+;  
 	; CONVERT BANK ID TO TOP 12 BITS OF PHYSICAL ADDRESS
 	; WITH $0A IN THE LOW ORDER NIBBLE:
 	; BANK ID: R000 BBBB
-	; PDR: R000 0BBB B000 1010	
+	; PDR: R000 0BBB B000 1010 (RC2014)
+	; PDR: 0000 RBBB B000 1010 (ZZ80MB)
 ;
 	;MULTU	A,$80			; HL=0R00 0BBB B000 0000
-	.DB	$FD,$ED,$F9,$80		; MULTU A,$80
+	;.DB	$FD,$ED,$F9,$80		; MULTU A,$80
+	MULTU	A,$80			; HL=0R00 0BBB B000 0000
 	BIT	6,H			; RAM BIT SET?
 	JR	Z,Z280_BNKSEL2		; IF NOT, ALL DONE
 	RES	6,H			; OTHERWISE, MOVE RAM BIT
-	SET	7,H			; HL=R000 0BBB B000 0000
-;
-  #ELSE
-;
-	; CONVERT BANK ID TO TOP 12 BITS OF PHYSICAL ADDRESS
-	; WITH $0A IN THE LOW ORDER NIBBLE:
-	; BANK ID: R000 BBBB
-	; PDR: 0000 RBBB B000 1010
-;
-	;MULTU	A,$80			; HL=0R00 0BBB B000 0000
-	.DB	$FD,$ED,$F9,$80		; MULTU A,$80
-	BIT	6,H			; RAM BIT SET?
-	JR	Z,Z280_BNKSEL2		; IF NOT, ALL DONE
-	RES	6,H			; OTHERWISE, MOVE RAM BIT
-	SET	3,H			; HL=0000 RBBB B000 0000
-;
-  #ENDIF
+	SET	RAMLOC-16,H		; HL=0000 RBBB B000 0000
 ;	
 Z280_BNKSEL2:
 ;
@@ -4578,14 +4204,14 @@ Z280_BNKSEL3:
 	; RESTORE I/O PAGE
 	LD	C,Z280_IOPR		; REG C POINTS TO I/O PAGE REGISTER
 	POP	HL			; RECOVER ORIGINAL I/O PAGE
-	.DB	$ED,$6E			; LDCTL	(C),HL
+	LDCTL	(C),HL
 ;
 	RET
 #ENDIF
 ;
 ; Z280 BANK COPY (CALLED FROM PROXY)
 ;
-#IF ((MEMMGR == MM_Z280RC) | (MEMMGR == MM_Z280ZZ))
+#IF (MEMMGR == MM_Z280)
 ;
 Z280_BNKCPY:
 	; Z280 MEMORY TO MEMORY DMA
@@ -4608,10 +4234,10 @@ Z280_BNKCPY:
 ;	
 	; SELECT I/O PAGE $FF
 	LD	C,Z280_IOPR		; I/O PAGE REGISTER
-	.DB	$ED,$66			; LDCTL HL,(C) ; GET CURRENT I/O PAGE
+	LDCTL	HL,(C)			; GET CURRENT I/O PAGE
 	LD	(IOPRVAL),HL		; SAVE IT
 	LD	L,$FF			; I/O PAGE $FF
-	.DB	$ED,$6E			; LDCTL (C),HL
+	LDCTL	(C),HL
 ;	
 	LD	C,Z280_DMA0_DSTL	; START WITH DEST REG LO
 ;
@@ -4638,7 +4264,7 @@ Z2DMALOOP:
 	; RESTORE I/O PAGE
 	LD	C,Z280_IOPR		; I/O PAGE REGISTER
 	LD	HL,(IOPRVAL)		; RESTORE I/O PAGE
-	.DB	$ED,$6E			; LDCTL (C),HL
+	LDCTL	(C),HL
 ;
 	; SETUP RETURN VALUES
 	POP	BC			; RECOVER ORIGINAL BC
@@ -4672,25 +4298,15 @@ Z2DMAADR1:
 	LD	A,$0F			; A=0000 1111
 	OR	L			; A=BAAA 1111
 	LD	L,A			; L=BAAA 1111
-	
-  #IF (MEMMGR == MM_Z280ZZ)
-	; IF ZZ80MB, THEN THE RAM/ROM SELECT BIT IS THE
-	; HIGH BIT.  MOVE THE RAM/ROM BIT.
-	; DMA HI=0000 RBBB BAAA 1111 LO=1111 AAAA AAAA AAAA
-	BIT	6,H
-	JR	Z,Z2DMAADR2
-	RES	6,H
-	SET	7,H
-  #ELSE
-	; IF NOT ZZ80MB, THEN THE RAM/ROM SELECT BIT IS BIT 3 OF
-	; HI WORD OF THE HI DMA ADDRESS.  MOVE THE RAM/ROM BIT.
-	; DMA HI=R000 0BBB BAAA 1111 LO=1111 AAAA AAAA AAAA
+;	
+	; MOVE THE RAM/ROM BIT.
+	; RC2014 DMA HI=0000 RBBB BAAA 1111 LO=1111 AAAA AAAA AAAA
+	; ZZ80MB DMA HI=R000 0BBB BAAA 1111 LO=1111 AAAA AAAA AAAA
 	BIT	6,H
 	JR	Z,Z2DMAADR2
 	RES	6,H
-	SET	3,H
-  #ENDIF
-	
+	SET	RAMLOC-16,H
+;
 Z2DMAADR2:
 	PUSH	HL			; SAVE IT FOR NOW
 
@@ -4699,16 +4315,16 @@ Z2DMAADR2:
 	LD	A,$F0			; A=1111 0000
 	OR	D			; A=1111 AAAA
 	LD	H,A			; HL=1111 AAAA AAAA AAAA
-
+;
 	; SET ADR LO REG
 	.DB	$ED,$BF			; OUTW (C),HL
 	INC	C			; BUMP TO ADR HI REG
-
+;
 	; SET ADR HI REG
 	POP	HL			; RECOVER THE HI VAL
 	.DB	$ED,$BF			; OUTW (C),HL
 	INC	C			; BUMP TO NEXT REG
-	
+;	
 	RET
 #ENDIF
 ;
@@ -4716,7 +4332,7 @@ Z2DMAADR2:
 ; ADDRESS AND CALLS IT.  ALLOWS ANY USER MODE CODE TO CALL INTO AN
 ; ARBITRARY LOCATION OF SYSTEM MODE CODE.
 ;
-#IF ((MEMMGR == MM_Z280RC) | (MEMMGR == MM_Z280ZZ))
+#IF (MEMMGR == MM_Z280)
 Z280_SYSCALL:
 	EX	(SP),HL
 	LD	(Z280_SYSCALL_GO+1),HL
diff --git a/Source/HBIOS/std.asm b/Source/HBIOS/std.asm
index 1fdeb7e9..ded5a73b 100644
--- a/Source/HBIOS/std.asm
+++ b/Source/HBIOS/std.asm
@@ -82,9 +82,8 @@ MM_SBC		.EQU	1		; ORIGINAL N8VEM/RBC Z80 SBC BANKED MEMORY
 MM_Z2		.EQU	2		; 16K X 4 BANKED MEMORY INTRODUCED ON ZETA2
 MM_N8		.EQU	3		; Z180 CUSTOMIZED FOR N8 MEMORY EXTENSIONS
 MM_Z180		.EQU	4		; Z180 NATIVE MEMORY MANAGER
-MM_Z280RC	.EQU	5		; Z280 NATIVE MEMORY MANAGER (RC STYLE)
-MM_Z280ZZ	.EQU	6		; Z280 NATIVE MEMORY MANAGER (ZZ80MB STYLE)
-MM_ZRC		.EQU	7		; ZRC BANK SWITCHING
+MM_Z280		.EQU	5		; Z280 NATIVE MEMORY MANAGER
+MM_ZRC		.EQU	6		; ZRC BANK SWITCHING
 ;
 ; BOOT STYLE
 ;
diff --git a/Source/HBIOS/z280.inc b/Source/HBIOS/z280.inc
index 5da6234c..e2aea667 100644
--- a/Source/HBIOS/z280.inc
+++ b/Source/HBIOS/z280.inc
@@ -57,7 +57,6 @@ Z280_UARTXCTL	.EQU	$12	; UART TRANSMIT CONTROL/STATUS REG
 Z280_UARTRCTL	.EQU	$14	; UART RECEIVE CONTROL/STATUS REG
 Z280_UARTRECV	.EQU	$16	; UART RECEIVE DATA REG
 Z280_UARTXMIT	.EQU	$18	; UART TRANSMIT DATA REG
-
 ;
 Z280_CT0_CFG	.EQU	$E0	; COUNTER/TIMER 0 CONFIG REG
 Z280_CT0_CMDST	.EQU	$E1	; COUNTER/TIMER 0 COMMAND/STATUS REG
@@ -73,4 +72,16 @@ Z280_CT2_CFG	.EQU	$F8	; COUNTER/TIMER 2 CONFIG REG
 Z280_CT2_CMDST	.EQU	$F9	; COUNTER/TIMER 2 COMMAND/STATUS REG
 Z280_CT2_TC	.EQU	$FA	; COUNTER/TIMER 2 TIME CONSTANT
 Z280_CT2_CT	.EQU	$FB	; COUNTER/TIMER 2 COUNT TIME
-
+;
+; Z280 INSTRUCTIONS (INCOMPLETE, JUST THE ONES USED)
+;
+.ADDINSTR	PCACHE	""	65ED	2 NOP 1
+.ADDINSTR	LDCTL	(C),HL	6EED	2 NOP 1
+.ADDINSTR	LDCTL	HL,(C)	66ED	2 NOP 1
+.ADDINSTR	IM	3	4EED	2 NOP 1
+.ADDINSTR	LDCTL	USP,HL	8FED	2 NOP 1
+.ADDINSTR	LDCTL	IY,(C)	66EDFD	3 NOP 1
+.ADDINSTR	LDCTL	(C),IY	6EEDFD	3 NOP 1
+.ADDINSTR	MULTU	A,*	F9EDFD	4 NOP 1
+.ADDINSTR	LD2	HL,(HL)	26ED	2 NOP 1
+.ADDINSTR	LD2	(HL),DE	1EED	2 NOP 1
diff --git a/Source/HBIOS/z2u.asm b/Source/HBIOS/z2u.asm
index 40032c1b..275ffbe1 100644
--- a/Source/HBIOS/z2u.asm
+++ b/Source/HBIOS/z2u.asm
@@ -173,10 +173,10 @@ Z2U_INT:
 ;
 	; START BY SELECTING I/O PAGE $FE (SAVING PREVIOUS VALUE)
 	LD	C,Z280_IOPR		; REG C POINTS TO I/O PAGE REGISTER
-	.DB	$ED,$66			; LDCTL HL,(C) ; GET CURRENT I/O PAGE
+	LDCTL	HL,(C)			; GET CURRENT I/O PAGE
 	PUSH	HL			; SAVE IT
 	LD	L,$FE			; NEW COUNTER/TIMER I/O PAGE
-	.DB	$ED,$6E			; LDCTL	(C),HL
+	LDCTL	(C),HL
 ;
 	; CHECK TO SEE IF SOMETHING IS ACTUALLY THERE
 	IN	A,(Z280_UARTRCTL)	; GET STATUS
@@ -199,11 +199,7 @@ Z2U_INTRCV1:
 Z2U_INTRCV2:
 	INC	HL			; HL NOW HAS ADR OF HEAD PTR
 	PUSH	HL			; SAVE ADR OF HEAD PTR
-	;LD	A,(HL)			; DEREFERENCE HL
-	;INC	HL
-	;LD	H,(HL)
-	;LD	L,A			; HL IS NOW ACTUAL HEAD PTR
-	.DB	$ED,$26			; LD HL,(HL) ; DEREFERENCE HL, HL IS NOW ACTUAL HEAD PTR
+	LD2	HL,(HL)			; DEREFERENCE HL, HL IS NOW ACTUAL HEAD PTR
 	LD	(HL),B			; SAVE CHARACTER RECEIVED IN BUFFER AT HEAD
 	INC	HL			; BUMP HEAD POINTER
 	POP	DE			; RECOVER ADR OF HEAD PTR
@@ -219,10 +215,7 @@ Z2U_INTRCV2:
 	INC	HL			; ... SO HL NOW HAS ADR OF ACTUAL BUFFER START
 Z2U_INTRCV3:
 	EX	DE,HL			; DE := HEAD PTR VAL, HL := ADR OF HEAD PTR
-	;LD	(HL),E			; SAVE UPDATED HEAD PTR
-	;INC	HL
-	;LD	(HL),D
-	.DB	$ED,$1E			;LD (HL),DE ; SAVE UPDATED HEAD PTR
+	LD2	(HL),DE			; SAVE UPDATED HEAD PTR
 
 	; CHECK FOR MORE PENDING...
 	IN	A,(Z280_UARTRCTL)	; GET STATUS
@@ -233,7 +226,7 @@ Z2U_INTRCV4:
 	; RESTORE I/O PAGE
 	LD	C,Z280_IOPR		; REG C POINTS TO I/O PAGE REGISTER
 	POP	HL			; RECOVER ORIGINAL I/O PAGE
-	.DB	$ED,$6E			; LDCTL	(C),HL
+	LDCTL	(C),HL
 ;
 	; RESTORE REGISTERS
 	POP	HL
@@ -267,7 +260,7 @@ Z2U_IN:
 	; START BY SELECTING I/O PAGE $FE
 	LD	L,$FE			; Z280 UART REGISTERS AT I/O PAGE $FE
 	LD	C,Z280_IOPR		; REG C POINTS TO I/O PAGE REGISTER
-	.DB	$ED,$6E			; LDCTL	(C),HL
+	LDCTL	(C),HL
 ;
 	; GET CHAR
 	IN	A,(Z280_UARTRECV)	; GET A BYTE
@@ -276,7 +269,7 @@ Z2U_IN:
 	; RESTORE I/O PAGE TO $00
 	LD	L,$00			; NORMAL I/O REG IS $00
 	LD	C,Z280_IOPR		; REG C POINTS TO I/O PAGE REGISTER
-	.DB	$ED,$6E			; LDCTL	(C),HL
+	LDCTL	(C),HL
 ;
 	XOR	A			; SIGNAL SUCCESS
 	RET				; DONE
@@ -334,7 +327,7 @@ Z2U_OUT:
 	; START BY SELECTING I/O PAGE $FE
 	LD	L,$FE			; Z280 UART REGISTERS AT I/O PAGE $FE
 	LD	C,Z280_IOPR		; REG C POINTS TO I/O PAGE REGISTER
-	.DB	$ED,$6E			; LDCTL	(C),HL
+	LDCTL	(C),HL
 ;
 	; WRITE CHAR
 	LD	A,E			; BYTE TO A
@@ -343,7 +336,7 @@ Z2U_OUT:
 	; RESTORE I/O PAGE TO $00
 	LD	L,$00			; NORMAL I/O REG IS $00
 	LD	C,Z280_IOPR		; REG C POINTS TO I/O PAGE REGISTER
-	.DB	$ED,$6E			; LDCTL	(C),HL
+	LDCTL	(C),HL
 ;	
 	XOR	A			; SIGNAL SUCCESS
 	RET				; DONE
@@ -356,7 +349,7 @@ Z2U_IST:
 	; START BY SELECTING I/O PAGE $FE
 	LD	L,$FE			; Z280 UART REGISTERS AT I/O PAGE $FE
 	LD	C,Z280_IOPR		; REG C POINTS TO I/O PAGE REGISTER
-	.DB	$ED,$6E			; LDCTL	(C),HL
+	LDCTL	(C),HL
 ;
 	; GET RECEIVE STATUS
 	IN	A,(Z280_UARTRCTL)	; GET STATUS
@@ -365,11 +358,11 @@ Z2U_IST:
 	; RESTORE I/O PAGE TO $00
 	LD	L,$00			; NORMAL I/O REG IS $00
 	LD	C,Z280_IOPR		; REG C POINTS TO I/O PAGE REGISTER
-	.DB	$ED,$6E			; LDCTL	(C),HL
+	LDCTL	(C),HL
 ;
 	OR	A			; SET FLAGS
 	JP	Z,CIO_IDLE		; NOT READY, RETURN VIA IDLE PROCESSING
-	
+;	
 	RET
 ;
 #ELSE
@@ -391,7 +384,7 @@ Z2U_OST:
 	; START BY SELECTING I/O PAGE $FE
 	LD	L,$FE			; Z280 UART REGISTERS AT I/O PAGE $FE
 	LD	C,Z280_IOPR		; REG C POINTS TO I/O PAGE REGISTER
-	.DB	$ED,$6E			; LDCTL	(C),HL
+	LDCTL	(C),HL
 ;
 	; GET TRANSMIT STATUS
 	IN	A,(Z280_UARTXCTL)	; GET STATUS
@@ -399,7 +392,7 @@ Z2U_OST:
 	; RESTORE I/O PAGE TO $00
 	LD	L,$00			; NORMAL I/O REG IS $00
 	LD	C,Z280_IOPR		; REG C POINTS TO I/O PAGE REGISTER
-	.DB	$ED,$6E			; LDCTL	(C),HL
+	LDCTL	(C),HL
 ;
 	; CHECK FOR CHAR AVAILABLE
 	AND	$01			; ISOLATE CHAR AVAILABLE BIT
@@ -439,7 +432,6 @@ Z2U_INITDEVX:
 ;
 Z2U_INITDEV1:
 	LD	(Z2U_NEWCFG),DE		; SAVE NEW CONFIG
-	
 ;
 ; HACK FOR TESTING!!!
 ;
@@ -457,8 +449,6 @@ Z2U_INITDEV1:
 	;LD	HL,52			; 24MHZ / 8 / 52 = 57692 BAUD (~57600)
 	JP	Z2U_INITDEV8		; SKIP AHEAD TO IMPLMENT IT
 #ENDIF
-;
-;
 ;
 	LD	A,D			; HIWORD OF CONFIG
 	AND	$1F			; ISOLATE BAUD RATE
@@ -480,7 +470,6 @@ Z2U_INITDEV1:
 	; Z280 UART CAN USE 16, 32, OR 64 AS BAUD RATE DIVISOR
 	; SET E TO IMPLEMENT WHAT WE CAN
 	LD	E,%11000000		; 8N0, DIV 1, NO C/T
-	;JR	Z2U_INITDEV2		; *DEBUG*
 	CP	4			; DIV 16 POSSIBLE?
 	JR	C,Z2U_INITDEV2		; IF NOT, SKIP AHEAD
 	LD	E,%11000010		; 8N0, DIV 16, NO C/T
@@ -508,10 +497,7 @@ Z2U_INITDEV2:
 	LD	H,0			; H MUST BE ZERO
 	LD	DE,1			; RATIO, SO NO CONSTANT
 	CALL	DECODE			; DECODE INTO DE:HL
-	;LD	HL,626			; *DEBUG*
 	JR	NZ,Z2U_INITFAIL		; HANDLE FAILURE
-	;CALL	PC_SPACE		; *DEBUG* 
-	;CALL	PRTHEXWORDHL            ; *DEBUG*
 ;
 	; SAVE CONFIG PERMANENTLY NOW
 	LD	DE,(Z2U_NEWCFG)		; GET NEW CONFIG BACK
@@ -523,7 +509,7 @@ Z2U_INITDEV8:
 	PUSH	HL			; SAVE HL
 	LD	L,$FE			; Z280 UART REGISTERS AT I/O PAGE $FE
 	LD	C,Z280_IOPR		; REG C POINTS TO I/O PAGE REGISTER
-	.DB	$ED,$6E			; LDCTL	(C),HL
+	LDCTL	(C),HL
 	POP	HL			; RESTORE HL
 ;
 	DEC	HL			; ADJUST FOR T/C
@@ -566,7 +552,7 @@ Z2U_INITDEV9:
 	; RESTORE I/O PAGE TO $00
 	LD	L,$00			; NORMAL I/O REG IS $00
 	LD	C,Z280_IOPR		; REG C POINTS TO I/O PAGE REGISTER
-	.DB	$ED,$6E			; LDCTL	(C),HL
+	LDCTL	(C),HL
 ;
 #IF (INTMODE == 3)
 ;
diff --git a/Source/ver.inc b/Source/ver.inc
index 8d8598cb..09ba0f52 100644
--- a/Source/ver.inc
+++ b/Source/ver.inc
@@ -2,4 +2,4 @@
 #DEFINE	RMN	1
 #DEFINE	RUP	1
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"3.1.1-pre.47"
+#DEFINE BIOSVER	"3.1.1-pre.48"
diff --git a/Source/ver.lib b/Source/ver.lib
index 8c392042..8687f19a 100644
--- a/Source/ver.lib
+++ b/Source/ver.lib
@@ -3,5 +3,5 @@ rmn	equ	1
 rup	equ	1
 rtp	equ	0
 biosver	macro
-	db	"3.1.1-pre.47"
+	db	"3.1.1-pre.48"
 	endm