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@ -63,25 +63,25 @@ |
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; |
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; CONSTANTS |
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; |
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; RTC SBC SBC-004 MFPIC N8 N8-CSIO SC |
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; ----- ------- ------- ------- ------- ------- ------- |
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; D7 WR RTC_OUT RTC_OUT -- RTC_OUT RTC_OUT RTC_OUT, I2C_SDA |
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; D6 WR RTC_CLK RTC_CLK -- RTC_CLK RTC_CLK RTC_CLK |
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; D5 WR /RTC_WE /RTC_WE -- /RTC_WE /RTC_WE /RTC_WE |
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; D4 WR RTC_CE RTC_CE -- RTC_CE RTC_CE RTC_CE |
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; D3 WR NC SPK /RTC_CE NC NC /SPI_CS2 |
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; D2 WR NC CLKHI RTC_CLK SPI_CS SPI_CS /SPI_CS1 |
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; D1 WR -- -- RTC_WE SPI_CLK NC FS |
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; D0 WR -- -- RTC_OUT SPI_DI NC I2C_SCL |
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; |
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; D7 RD -- -- -- -- -- I2C_SDA |
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; D6 RD CFG CFG -- SPI_DO CFG -- |
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; D5 RD -- -- -- -- -- -- |
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; D4 RD -- -- -- -- -- -- |
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; D3 RD -- -- -- -- -- -- |
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; D2 RD -- -- -- -- -- -- |
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; D1 RD -- -- -- -- -- -- |
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; D0 RD RTC_IN RTC_IN RTC_IN RTC_IN RTC_IN RTC_IN |
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; RTC SBC SBC-004 MFPIC N8 N8-CSIO MK4 SC130 SC131 SC126 |
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; ----- ------- ------- ------- ------- ------- ------- ------- ------- ------- |
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; D7 WR RTC_OUT RTC_OUT -- RTC_OUT RTC_OUT RTC_OUT -- -- RTC_OUT, I2C_SDA |
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; D6 WR RTC_CLK RTC_CLK -- RTC_CLK RTC_CLK RTC_CLK -- -- RTC_CLK |
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; D5 WR /RTC_WE /RTC_WE -- /RTC_WE /RTC_WE /RTC_WE -- -- /RTC_WE |
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; D4 WR RTC_CE RTC_CE -- RTC_CE RTC_CE RTC_CE -- -- RTC_CE |
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; D3 WR NC SPK /RTC_CE NC NC NC -- -- /SPI_CS2 |
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; D2 WR NC CLKHI RTC_CLK SPI_CS SPI_CS NC /SPI_CS1/SPI_CS1/SPI_CS1 |
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; D1 WR -- -- RTC_WE SPI_CLK NC NC -- -- FS |
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; D0 WR -- -- RTC_OUT SPI_DI NC NC -- -- I2C_SCL |
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; |
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; D7 RD -- -- -- -- -- -- -- -- I2C_SDA |
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; D6 RD CFG CFG -- SPI_DO CFG -- -- -- -- |
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; D5 RD -- -- -- -- -- -- -- -- -- |
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; D4 RD -- -- -- -- -- -- -- -- -- |
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; D3 RD -- -- -- -- -- -- -- -- -- |
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; D2 RD -- -- -- -- -- -- -- -- -- |
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; D1 RD ---- -- -- -- -- -- -- -- -- |
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; D0 RD RTC_IN RTC_IN RTC_IN RTC_IN RTC_IN RTC_IN -- -- RTC_IN |
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; |
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#IF (DSRTCMODE == DSRTCMODE_STD) |
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; |
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@ -95,7 +95,7 @@ DSRTC_CE .EQU %00010000 ; BIT 4 IS CHIP ENABLE (CE) |
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DSRTC_MASK .EQU %11110000 ; MASK FOR BITS WE OWN IN RTC LATCH PORT |
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DSRTC_IDLE .EQU %00100000 ; QUIESCENT STATE |
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; |
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RTCDEF .SET DSRTC_IDLE ; FOR HBIOS MAINLINE |
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RTCDEF .SET RTCDEF | DSRTC_IDLE ; FOR HBIOS MAINLINE |
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; |
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#DEFINE DSRTC_OPRVAL RTCVAL |
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; |
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@ -195,7 +195,7 @@ DSRTC_INIT1: |
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CALL DSRTC_CLK2TIM |
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LD HL,DSRTC_TIMBUF |
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CALL PRTDT |
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; |
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; |
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#IF DSRTCCHG ; FORCE_RTC_CHARGE_ENABLE |
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LD C,$90 ; ACCESS CHARGE REGISTER |
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LD E,DS1d2k ; STD CHARGE VALUES |
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@ -234,11 +234,11 @@ DSRTC_DISPATCH: |
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DEC A |
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JP Z,DSRTC_GETBLK ; GET NVRAM DATA BLOCK VALUES |
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DEC A |
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JP Z,DSRTC_SETBLK ; SET NVRAM DATA BLOCK VALUES |
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JP Z,DSRTC_SETBLK ; SET NVRAM DATA BLOCK VALUES |
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DEC A |
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JP Z,DSRTC_GETALM ; GET ALARM |
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DEC A |
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JP Z,DSRTC_SETALM ; SET ALARM |
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JP Z,DSRTC_SETALM ; SET ALARM |
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DEC A |
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JP Z,DSRTC_DEVICE ; REPORT RTC DEVICE INFO |
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CALL SYSCHK |
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@ -393,7 +393,7 @@ DSRTC_CLK2TIM: |
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LD (HL),A |
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INC HL |
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LD A,(DSRTC_SEC) |
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LD (HL),A |
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LD (HL),A |
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RET |
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; |
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; CONVERT DATA IN TIME BUFFER AT HL TO CLOCK BUFFER |
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@ -431,20 +431,20 @@ DSRTC_TSTCHG: |
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LD A,E ; VALUE TO A |
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AND %11110000 ; CHECK FOR |
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CP %10100000 ; ... ENABLED FLAG |
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RET |
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RET |
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; |
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; DETECT RTC HARDWARE PRESENCE |
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; |
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DSRTC_DETECT: |
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LD C,31 ; NVRAM INDEX 31 |
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LD C,30 ; NVRAM INDEX 30 |
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CALL DSRTC_GETBYT ; GET VALUE |
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LD A,E ; TO ACCUM |
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LD (DSRTC_TEMP),A ; SAVE IT |
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XOR $FF ; FLIP ALL BITS |
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LD E,A ; TO E |
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LD C,31 ; NVRAM INDEX 31 |
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LD C,30 ; NVRAM INDEX 30 |
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CALL DSRTC_SETBYT ; WRITE IT |
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LD C,31 ; NVRAM INDEX 31 |
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LD C,30 ; NVRAM INDEX 30 |
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CALL DSRTC_GETBYT ; GET VALUE |
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LD A,(DSRTC_TEMP) ; GET SAVED VALUE |
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XOR $FF ; FLIP ALL BITS |
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@ -455,7 +455,7 @@ DSRTC_DETECT: |
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DSRTC_DETECT1: |
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PUSH AF ; SAVE STATUS |
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LD A,(DSRTC_TEMP) ; GET SAVED VALUE |
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LD C,31 ; NVRAM INDEX 31 |
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LD C,30 ; NVRAM INDEX 30 |
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CALL DSRTC_SETBYT ; SAVE IT |
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POP AF ; RECOVER STATUS |
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OR A ; SET FLAGS |
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@ -506,7 +506,7 @@ DSRTC_WRBYT: |
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DSRTC_WRBYTWP: |
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LD D,C ; WRITE CMD TO D |
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PUSH DE ; SAVE PARMS |
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; |
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; |
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; TURN OFF WRITE PROTECT |
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LD C,$8E ; CMD |
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LD E,0 ; WRITE PROTECT OFF |
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@ -517,7 +517,7 @@ DSRTC_WRBYTWP: |
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LD C,D ; WRITE CMD BACK TO C |
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CALL DSRTC_WRBYT ; DO IT |
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; |
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; TURN WRITE PROTECT BACK ON |
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; TURN WRITE PROTECT BACK ON |
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LD C,$8E ; WRITE CMD TO D |
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LD E,$80 ; WRITE PROTECT ON |
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CALL DSRTC_WRBYT ; DO IT |
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@ -619,7 +619,7 @@ DSRTC_PUT1: |
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AND ~DSRTC_CLK ; SET CLOCK LOW |
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OUT (DSRTC_IO),A ; DO IT |
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CALL DLY1 ; DELAY 27 T-STATES |
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#IF (DSRTCMODE == DSRTCMODE_MFPIC) |
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RRA ; PREP ACCUM TO GET DATA BIT IN CARRY |
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RR E ; ROTATE NEXT BIT TO SEND INTO CARRY |
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@ -628,7 +628,7 @@ DSRTC_PUT1: |
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RLA ; PREP ACCUM TO GET DATA BIT IN CARRY |
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RR E ; ROTATE NEXT BIT TO SEND INTO CARRY |
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RRA ; ROTATE BITS BACK TO CORRECT POSTIIONS |
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#ENDIF |
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#ENDIF |
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OUT (DSRTC_IO),A ; ASSERT DATA BIT ON BUS |
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OR DSRTC_CLK ; SET CLOCK HI |
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OUT (DSRTC_IO),A ; DO IT |
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@ -710,7 +710,9 @@ DSRTC_END: |
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DSRTC_STAT .DB 0 ; DEVICE STATUS (0=OK) |
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DSRTC_TEMP .DB 0 ; TEMP VALUE STORAGE |
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; |
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#IF (DSRTCMODE == DSRTCMODE_MFPIC) |
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DSRTC_RTCVAL .DB DSRTC_IDLE ; LOCAL LATCH SHADOW FOR MFPIC |
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#ENDIF |
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; |
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; DSRTC_BUF IS USED FOR BURST READ/WRITE OF CLOCK DATA TO DS-1302 |
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; FIELDS BELOW MATCH ORDER OF DS-1302 FIELDS (BCD) |
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b1ackmai1er
5 years ago
GitHub