Finalize CPUSPD

The CPUSPD app is now considered stable and fully supported.  I have added the application and the API's to the documentation.

ReadMe.md

@@ -3,7 +3,7 @@ author: "Wayne Warthen (mailto:wwarthen@gmail.com)"
 classoption:
 - oneside
 colorlinks: true
-date: 26 Jan 2022
+date: 01 Feb 2022
 documentclass: book
 fontfamily: helvet
 fontsize: 12pt
@@ -44,7 +44,7 @@ toc-depth: 1
 ## Z80/Z180 System Software
 
 Version 3.1 Pre-release  
-26 Jan 2022
+01 Feb 2022
 
 Wayne Warthen <wwarthen@gmail.com>
 

ReadMe.txt

@@ -1,6 +1,6 @@
 RomWBW Getting Started
 Wayne Warthen (mailto:wwarthen@gmail.com)
-26 Jan 2022
+01 Feb 2022
 
 
 
@@ -17,7 +17,7 @@ RomWBW
 Z80/Z180 System Software
 
 Version 3.1 Pre-release
-26 Jan 2022
+01 Feb 2022
 
 Wayne Warthen wwarthen@gmail.com
 

Source/Apps/Build.cmd

@@ -35,6 +35,7 @@ pushd ZMP && call Build || exit /b & popd
 pushd ZMD && call Build || exit /b & popd
 pushd Dev && call Build || exit /b & popd
 pushd VGM && call Build || exit /b & popd
+pushd cpuspd && call Build || exit /b & popd
 
 copy *.com %APPBIN%\ || exit /b
 

Source/Apps/Clean.cmd

@@ -16,3 +16,4 @@ pushd ZMP && call Clean || exit /b 1 & popd
 pushd ZMD && call Clean || exit /b 1 & popd
 pushd Dev && call Clean || exit /b 1 & popd
 pushd VGM && call Clean || exit /b 1 & popd
+pushd cpuspd && call Clean || exit /b 1 & popd

Source/Apps/Makefile

@@ -1,7 +1,7 @@
 OBJECTS = sysgen.com survey.com \
 	syscopy.com assign.com format.com talk.com mode.com rtc.com \
 	timer.com rtchb.com
-SUBDIRS = XM FDU FAT Tune Test ZMP ZMD Dev VGM
+SUBDIRS = XM FDU FAT Tune Test ZMP ZMD Dev VGM cpuspd
 DEST = ../../Binary/Apps
 TOOLS =../../Tools
 

Source/Apps/Test/Build.cmd

@@ -22,7 +22,6 @@ pushd rzsz && call Build || exit /b & popd
 pushd vdctest && call Build || exit /b & popd
 pushd kbdtest && call Build || exit /b & popd
 pushd ps2info && call Build || exit /b & popd
-pushd cpuspd && call Build || exit /b & popd
 
 goto :eof
 

Source/Apps/Test/Clean.cmd

@@ -17,4 +17,3 @@ pushd rzsz && call Clean || exit /b 1 & popd
 pushd vdctest && call Clean || exit /b 1 & popd
 pushd kbdtest && call Clean || exit /b 1 & popd
 pushd ps2info && call Clean || exit /b 1 & popd
-pushd cpuspd && call Clean || exit /b 1 & popd

Source/Apps/Test/Makefile

@@ -1,5 +1,5 @@
 OBJECTS = 
-SUBDIRS = DMAmon I2C inttest ppidetst ramtest tstdskng rzsz vdctest kbdtest ps2info cpuspd
+SUBDIRS = DMAmon I2C inttest ppidetst ramtest tstdskng rzsz vdctest kbdtest ps2info
 DEST = ../../../Binary/Apps/Test
 TOOLS =../../../Tools
 

Source/Apps/Test/cpuspd/Makefile

@@ -1,7 +0,0 @@
-OBJECTS = cpuspd.com
-DEST = ../../../../Binary/Apps/Test
-TOOLS =../../../../Tools
-
-USETASM=1
-
-include $(TOOLS)/Makefile.inc

Source/Apps/Test/cpuspd/Build.cmd → Source/Apps/cpuspd/Build.cmd

@@ -7,4 +7,4 @@ set TASMTABS=%TOOLS%\tasm32
 
 tasm -t180 -g3 -fFF cpuspd.asm cpuspd.com cpuspd.lst || exit /b
 
-copy /Y cpuspd.com ..\..\..\..\Binary\Apps\Test\ || exit /b
+copy /Y cpuspd.com ..\..\..\Binary\Apps\ || exit /b

Source/Apps/cpuspd/Makefile

@@ -0,0 +1,7 @@
+OBJECTS = cpuspd.com
+DEST = ../../../Binary/Apps
+TOOLS =../../../Tools
+
+USETASM=1
+
+include $(TOOLS)/Makefile.inc

Source/Apps/Test/cpuspd/cpuspd.asm → Source/Apps/cpuspd/cpuspd.asm

@@ -8,12 +8,14 @@
 ;
 ;=======================================================================
 ;
-#include "../../../HBIOS/hbios.inc"
+#include "../../HBIOS/hbios.inc"
 ;
 ; General operational equates (should not requre adjustment)
 ;
 stksiz		.equ	$40		; Working stack size
 ;
+cpumhz		.equ	30		; for time delay calculations (not critical)
+;
 rtc_port	.equ	$70		; RTC latch port adr
 ;
 restart		.equ	$0000		; CP/M restart vector
@@ -46,21 +48,64 @@ exit:
 ;=======================================================================
 ;
 main:
-;
-; Get HBIOS platform ID
-;
-	; Use first char of FCB for speed selection
-	ld	a,($5D)
-	cp	' '
-	jr	z,show_spd
-	and	$5F		; make upper case
-	cp	'D'		; double
-	jr	z,set_dbl
-	cp	'F'		; full
-	jr	z,set_full
-	cp	'H'		; half
+	; skip to start of first parm
+	ld	ix,$81		; point to start of parm area (past len byte)
+	call	nonblank	; skip to next non-blank char
+	jp	z,show_spd	; no parms, show current settings
+;
+main1:
+	; process options (if any)
+	cp	'/'		; option prefix?
+	jr	nz,main2	; not an option, continue
+	call	option		; process option
+	ret	nz		; some options mean we are done (e.g., "/?")
+	inc	ix		; skip option character
+	call 	nonblank	; skip whitespace
+	jr	main1		; continue option checking
+;
+main2:
+	; parse speed string (half, full, double)
+	call	getalpha	; extract speed ("HALF", "FULL", "DOUBLE")
+;
+	call	nonblank	; skip whitespace
+	jp	z,set_spd	; if nothing else, set new speed
+	cp	','		; parm separator
+	jp	nz,err_parm	; invalid format, show usage and abort
+	inc	ix		; pass separator
+	call	nonblank	; skip whitespace
+	jp	z,set_spd	; if nothing else, set new speed
+	call	isnum		; start of parm?
+	jr	c,main3		; nope, try skipping this parm
+	call	getnum		; get memory wait states
+	jp	c,err_parm	; if overflow, show usage and abort
+	ld	(ws_mem),a	; save memory wait states
+;
+main3:
+	call	nonblank	; skip whitespace
+	jp	z,set_spd	; if nothing else, set new speed
+	cp	','		; parm separator
+	jp	nz,err_parm	; invalid format, show usage and abort
+	inc	ix		; pass separator
+	call	nonblank	; skip whitespace
+	jp	z,set_spd	; if nothing else, set new speed
+	call	getnum		; get I/O wait states
+	jp	c,err_parm	; if overflow, show usage and abort
+	ld	(ws_io),a	; save memory wait states
+;
+	call	nonblank	; skip whitespace
+	jp	nz,err_parm	; invalid format, show usage and abort
+	;
+;
+set_spd:
+	ld	a,(tmpstr)
+	cp	'H'
 	jr	z,set_half
-	jr	usage
+	cp	'F'
+	jr	z,set_full
+	cp	'D'
+	jr	z,set_dbl
+	jp	err_parm
+	ret
 ;
 set_half:
 	ld	l,0
@@ -75,8 +120,13 @@ set_dbl:
 	jr	new_spd
 ;
 new_spd:
+	call	delay
 	ld	b,BF_SYSSET
 	ld	c,BF_SYSSET_CPUSPD
+	ld	a,(ws_mem)
+	ld	d,a
+	ld	a,(ws_io)
+	ld	e,a
 	rst	08
 	jp	nz,err_not_sup
 	call	show_spd
@@ -129,6 +179,16 @@ show_spd2:
 show_spd3:
 	ret
 ;
+; Handle special options
+;
+option:
+;
+	inc	ix		; next char
+	ld	a,(ix)		; get it
+	cp	'?'		; is it a '?' as expected?
+	jp	z,usage		; yes, display usage
+	jp	err_parm	; anything else is an error
+
 usage:
 	call	crlf2
 	ld	de,str_usage
@@ -138,6 +198,9 @@ usage:
 ;
 ; Error Handlers
 ;
+err_parm:
+	ld	de,str_err_parm
+	jr	err_ret
 err_not_sup:
 	ld	de,str_err_not_sup
 	jr	err_ret
@@ -327,6 +390,99 @@ prtdec2:
 	call	prtchr
 	ret
 ;
+; Get the next non-blank character from (HL).
+;
+nonblank:
+	ld	a,(ix)		; load next character
+	or	a		; string ends with a null
+	ret	z		; if null, return pointing to null
+	cp	' '		; check for blank
+	ret	nz		; return if not blank
+	inc	ix		; if blank, increment character pointer
+	jr	nonblank	; and loop
+;
+; Get alpha chars and save in tmpstr
+; Length of string returned in A
+;
+getalpha:
+;
+	ld	hl,tmpstr	; location to save chars
+	ld	b,8		; length counter (tmpstr max chars)
+	ld	c,0		; init character counter
+;
+getalpha1:
+	ld	a,(ix)		; get active char
+	call	ucase		; lower case -> uppper case, if needed
+	cp	'A'		; check for start of alpha range
+	jr	c,getalpha2	; not alpha, get out
+	cp	'Z' + 1		; check for end of alpha range
+	jr	nc,getalpha2	; not alpha, get out
+	; handle alpha char
+	ld	(hl),a		; save it
+	inc	c		; bump char count
+	inc	hl		; inc string pointer
+	inc	ix		; increment buffer ptr
+	djnz	getalpha1	; if space, loop for more chars
+;
+getalpha2:	; non-alpha, clean up and return
+	ld	(hl),0		; terminate string
+	ld	a,c		; string length to A
+	or	a		; set flags
+	ret			; and return
+;
+; Determine if byte in A is a numeric '0'-'9'
+; Return with CF clear if it is numeric
+;
+isnum:
+	cp	'0'
+	jr	c,isnum1	; too low
+	cp	'9' + 1
+	jr	nc,isnum1	; too high
+	or	a		; clear CF
+	ret
+isnum1:
+	or	a		; clear CF
+	ccf			; set CF
+	ret
+	
+;
+; Get numeric chars and convert to number returned in A
+; Carry flag set on overflow
+;
+getnum:
+	ld	c,0		; C is working register
+getnum1:
+	ld	a,(ix)		; get the active char
+	cp	'0'		; compare to ascii '0'
+	jr	c,getnum2	; abort if below
+	cp	'9' + 1		; compare to ascii '9'
+	jr	nc,getnum2	; abort if above
+;
+	; valid digit, add new digit to C
+	ld	a,c		; get working value to A
+	rlca			; multiply by 10
+	ret	c		; overflow, return with carry set
+	rlca			; ...
+	ret	c		; overflow, return with carry set
+	add	a,c		; ...
+	ret	c		; overflow, return with carry set
+	rlca			; ...
+	ret	c		; overflow, return with carry set
+	ld	c,a		; back to C
+	ld	a,(ix)		; get new digit
+	sub	'0'		; make binary
+	add	a,c		; add in working value
+	ret	c		; overflow, return with carry set
+	ld	c,a		; back to C
+;
+	inc	ix		; bump to next char
+	jr	getnum1		; loop
+;
+getnum2:	; return result
+	ld	a,c		; return result in A
+	or	a		; with flags set, CF is cleared
+	ret
+;
 ; Start a new line
 ;
 crlf2:
@@ -340,6 +496,16 @@ crlf:
 	pop	af		; restore AF
 	ret
 ;
+; Convert character in A to uppercase
+;
+ucase:
+	cp	'a'		; if below 'a'
+	ret	c		; ... do nothing and return
+	cp	'z' + 1		; if above 'z'
+	ret	nc		; ... do nothing and return
+	res	5,a		; clear bit 5 to make lower case -> upper case
+	ret			; and return
+;
 ; Add hl,a
 ;
 ;   A register is destroyed!
@@ -351,21 +517,41 @@ addhla:
 	inc	h
 	ret
 ;
+; Delay ~10ms
+;
+delay:
+	push	af
+	push	de
+	ld	de,625			; 10000us/16us
+delay0:
+	ld	a,cpumhz - 2
+delay1:
+	dec	a
+	jr	nz,delay1
+	dec	de
+	ld	a,d
+	or	e
+	jp	nz,delay0
+	pop	de
+	pop	af
+	ret
+;
 ;
 ;=======================================================================
 ; Constants
 ;=======================================================================
 ;
-str_banner		.db	"RomWBW CPU Speed Selector v0.2, 26-Jan-2022",0
+str_banner		.db	"RomWBW CPU Speed Selector v0.4, 31-Jan-2022",0
 str_spacer		.db	"  ",0
 str_slow		.db	"  CPU speed is HALF",0
 str_full		.db	"  CPU speed is FULL",0
 str_dbl			.db	"  CPU speed is DOUBLE",0
 str_memws		.db	" Memory Wait State(s)",0
 str_iows		.db	" I/O Wait State(s)",0
+str_err_parm		.db	"  Parameter error (CPUSPD /? for usage)",0
 str_err_not_sup		.db	"  ERROR: Platform or configuration not supported!",0
 str_err_invalid		.db	"  ERROR: Invalid configuration!",0
-str_usage		.db	"  Usage: CPUSPD [Half|Full|Double]",0
+str_usage		.db	"  Usage: CPUSPD [(Half|Full|Double)[,<Memory Waits>[,<I/O Waits>]]]",0
 ;
 ;=======================================================================
 ; Working data
@@ -374,6 +560,13 @@ str_usage		.db	"  Usage: CPUSPD [Half|Full|Double]",0
 stksav		.dw	0		; stack pointer saved at start
 		.fill	stksiz,0	; stack
 stack		.equ	$		; stack top
+;
+;
+tmpstr		.fill	9,0		; temp string (8 chars, 0 term)
+ws_mem		.db	$FF		; memory wait states
+ws_io		.db	$FF		; I/O wait states
+
+
 ;
 ;=======================================================================
 ;

Source/Doc/Applications.md

@@ -47,7 +47,8 @@ found:
 | TALK        | Yes      | Yes        | Yes      |
 | RTC         | Yes      | Yes        | Yes      |
 | TIMER       | Yes      | Yes        | Yes      |
-| INTTEST     | Yes      | Yes        | Yes      |
+| CPUSPD      | Yes      | Yes        | Yes      |
+| INTTEST     | No       | Yes        | Yes      |
 | FAT         | No       | Yes        | Yes      |
 | TUNE        | No       | Yes        | Yes      |
 
@@ -955,3 +956,70 @@ player code is from MYMPLAY 0.4 by Lieves!Tuore and the PT player code
 is (c)2004-2007 S.V.Bulba <vorobey@mail.khstu.ru>.
 
 The source code is provided in the RomWBW distribution.
+
+# CPUSPD
+
+The `CPUSPD` application is used to change the running speed and wait
+states of a RomWBW system.
+
+  The functionality is highly dependent on
+the capabilities of your system.
+
+At present, all Z180 systems can change their CPU speed and their
+wait states.  SBC and MBC systems may be able to change their CPU
+speed if the hardware supports it and it is enabled in the HBIOS
+configuration.
+
+## Syntax
+
+| `CPUSPD [`*`<speed>`*`[,[`*`<memws>`*`][,[`*`<iows>`*`]]]`
+
+*`<speed>`* is one of HALF, FULL, or DOUBLE.  
+*`<memws>`* is a number specifying the desired memory wait states.  
+*`<iows>`* is a number specifying the desired I/O wait states.
+
+## Usage
+
+Entering `CPUSPD` with no parameters will display the current CPU speed
+and wait state information of the running system.  Wait state
+information is not available for all systems.
+
+To modify the running speed of a system, you can specify the
+`*`<speed>`*` parameter.  To modify either or both of the wait
+states, you can enter the desired number.  Either or both of the wait
+state parameters may be omitted and the current wait state settings
+will remain in effect.
+
+## Notes
+
+The ability to modify the running speed and wait states of a system
+varies widely depending on the hardware capabilities and the HBIOS
+configuration settings.
+
+Note that it is frequently impossible to tell if a system is capable
+of dynamic speed changes.  This function makes the changes blindly.
+If an attempt is made to change the speed of a system
+that is definitely incapable of doing so, then an error result is
+returned.
+
+The `CPUSPD` command makes no attempt to ensure that the new CPU
+speed will actually work on the current hardware.  Setting a CPU
+speed that exceeds the capabilities of the system will result in
+unstable operation or a system stall.
+
+Some peripherals are dependant on the CPU speed.  For example, the Z180
+ASCI baud rate and system timer are derived from the CPU speed.  The
+CPUSPD applicastion will attempt to adjust these peripherals for
+correct operation after modifying the CPU speed.  However, in some
+cases this may not be possible.  The baud rate of ASCI ports have a
+limited set of divisors.  If there is no satisfactory divisor to
+retain the existing baud rate under the new CPU speed, then the baud
+rate of the ASCI port(s) will be affected.
+
+## Etymology
+
+The `CPUSPD` application was custom written for RomWBW. All of the
+hardware interface code is specific to RomWBW and the application will
+not operate correctly on non-RomWBW systems.
+
+The source code is provided in the RomWBW distribution.

Source/Doc/Architecture.md

@@ -2034,10 +2034,18 @@ This function will modify the running CPU speed attributes of a system.
 Note that it is frequently impossible to tell if a system is capable
 of dynamic speed changes.  This function makes the changes blindly.
 You can specify 0xFF for either of the wait state settings to have them
-left alone.
-
-In the case of the Z180, the SIO port buad rate is derived from the CPU
-speed.  So, when the speed is changed the baud rate will change.
+left alone.  If an attempt is made to change the speed of a system
+that is definitely incapable of doing so, then an error result is
+returned.
+
+Some peripherals are dependant on the CPU speed.  For example, the Z180
+ASCI baud rate and system timer are derived from the CPU speed.  The
+Set CPU Speed function will attempt to adjust these peripherals for
+correct operation after modifying the CPU speed.  However, in some
+cases this may not be possible.  The baud rate of ASCI ports have a
+limited set of divisors.  If there is no satisfactory divisor to
+retain the existing baud rate under the new CPU speed, then the baud
+rate of the ASCI port(s) will be affected.
 
 ### Function 0xFA -- System Peek (SYSPEEK)
 

Source/Doc/GettingStarted.md

@@ -424,7 +424,7 @@ therefore, globally available.
 | TALK        | Direct console I/O to a specified character device.                                                  |
 | RTC         | Manage and test the Real Time Clock hardware.                                                        |
 | TIMER       | Display value of running periodic system timer.                                                      |
-| INTTEST     | Test interrupt vector hooking.                                                                       |
+| CPUSPD      | Change the running CPU speed and wait states of the system.    |
 
 Some custom applications do not fit on the ROM disk. They are found on the
 disk image files or the individual files can be found in the Binary\\Apps
@@ -434,6 +434,7 @@ directory of the distribution.
 | ----------- | -------------------------------------------------------------- |
 | TUNE        | Play .PT2, .PT3, .MYM audio files.                             |
 | FAT         | Access MS-DOS FAT filesystems from RomWBW (based on FatFs).    |
+| INTTEST     | Test interrupt vector hooking.                                                                       |
 
 Additional documentation on all of these applications can be found in
 "RomWBW Applications.pdf" in the Doc directory of the distribution.

Source/HBIOS/hbios.asm

@@ -70,8 +70,6 @@
 ;
 #DEFINE	HBIOS
 ;
-;;;#DEFINE TESTING
-;
 ; MAKE SURE EXACTLY ONE OF ROMBOOT, APPBOOT, IMGBOOT IS DEFINED.
 ;
 MODCNT	.EQU	0
@@ -188,19 +186,11 @@ RTCDEF		.SET	RTCDEF | %00000001	; SC128 I2C SCL BIT
 #ENDIF
 ;
 #IF ((CPUSPDCAP==SPD_HILO) & (PLATFORM==PLT_MBC))
-  #IF (CPUSPDDEF==SPD_HIGH)
-RTCDEF		.SET	RTCDEF | %00001000	; DEFAULT SPEED HIGH
-  #ELSE
-RTCDEF		.SET	RTCDEF & ~%00001000	; DEFAULT SPEED LOW
-  #ENDIF
+RTCDEF		.SET	RTCDEF & ~%00001000	; INITIAL SPEED LOW
 #ENDIF
 ;
 #IF ((CPUSPDCAP==SPD_HILO) & (PLATFORM==PLT_SBC))
-  #IF (CPUSPDDEF==SPD_HIGH)
-RTCDEF		.SET	RTCDEF & ~%00001000	; DEFAULT SPEED HIGH
-  #ELSE
-RTCDEF		.SET	RTCDEF | %00001000	; DEFAULT SPEED LOW
-  #ENDIF
+RTCDEF		.SET	RTCDEF | %00001000	; INITIAL SPEED LOW
 #ENDIF
 ;
 ;
@@ -1775,56 +1765,119 @@ HB_CPU1:
 	OUT	($6D),A		; IMPLEMENT IT
 ;
 #ENDIF
+;
+	DIAG(%00011111)
+;
+; INIT OSCILLATOR SPEED FROM CONFIG
+;
+	LD	HL,CPUOSC / 1000
+	LD	(HB_CPUOSC),HL
+;
+; ATTEMPT DYNAMIC CPU SPEED DERIVATION
+; NOTE THAT FOR PLATFORMS WITH SOFTWARE SELECTABLE CPU SPEED,
+; THIS IS BEING DONE WITH THE CPU SPEED SET TO THE LOWEST
+; POSSIBLE SETTING.  THE FINAL CPU SPEED WILL BE ADJUSTED
+; LATER.
+;
+	CALL	HB_CPUSPD		; CPU SPEED DETECTION
+	JR	NZ,HB_CPUSPD2		; SKIP IF FAILED
+;
+; RECORD THE UPDATED CPU OSCILLATOR SPEED
+;
+#IF ((CPUFAM == CPU_Z180) | (CPUSPDCAP == SPD_HILO))
+	; SPEED MEASURED WILL BE HALF OSCILLATOR SPEED
+	; SO RECORD DOUBLE THE MEASURED VALUE
+	SLA	L
+	RL	H
+	LD	(HB_CPUOSC),HL
+#ENDIF
+;
+HB_CPUSPD2:
+;
+; INIT CPUKHZ BASED ON OSCILLATOR SPEED
+;
+	LD	HL,(HB_CPUOSC)
+;
+; TRANSITION TO FINAL DESIRED CPU SPEED FOR THOSE PLATFORMS
+; THAT SUPPORT SOFTWARE SELECTABLE CPU SPEED.  UPDATE CB_CPUKHZ
+; IN HCB AS WE DO THIS.
+;
+#IF ((CPUSPDCAP==SPD_HILO) & (PLATFORM==PLT_MBC) & (CPUSPDDEF==SPD_HIGH))
+	; SET HIGH SPEED VIA RTC LATCH
+	LD	A,(HB_RTCVAL)
+	OR	%00001000		; SET HI SPEED BIT
+	LD	(HB_RTCVAL),A		; SAVE SHADOW
+	OUT	(RTCIO),A		; IMPLEMENT
+	; HL IS ALREADY CORRECT FOR FULL SPEED OPERATION
+#ELSE
+	; ADJUST HL TO REFLECT HALF SPEED OPERATION
+	SRL	H		; ADJUST HL ASSUMING
+	RR	L		; HALF SPEED OPERATION
+#ENDIF
+;
+#IF ((CPUSPDCAP==SPD_HILO) & (PLATFORM==PLT_SBC) & (CPUSPDDEF==SPD_HIGH))
+	; SET HIGH SPEED VIA RTC LATCH
+	LD	A,(HB_RTCVAL)
+	AND	~%00001000		; CLEAR HI SPEED BIT
+	LD	(HB_RTCVAL),A		; SAVE SHADOW
+	OUT	(RTCIO),A		; IMPLEMENT
+	; HL IS ALREADY CORRECT FOR FULL SPEED OPERATION
+#ELSE
+	; ADJUST HL TO REFLECT HALF SPEED OPERATION
+	SRL	H		; ADJUST HL ASSUMING
+	RR	L		; HALF SPEED OPERATION
+#ENDIF
 ;
 #IF (CPUFAM == CPU_Z180)
 ;
-	; AT BOOT, Z180 PHI IS OSC / 2
-	LD	C,(CPUOSC / 2) / 1000000
-	LD	DE,(CPUOSC / 2) / 1000
+	LD	HL,(HB_CPUOSC)	; INIT HL TO CPU OSC FREQ (KHZ)
 ;
-  #IF (Z180_CLKDIV >= 1)
+  #IF (Z180_CLKDIV == 0)
+	; ADJUST HL TO REFLECT HALF SPEED OPERATION
+	SRL	H		; ADJUST HL ASSUMING
+	RR	L		; HALF SPEED OPERATION
+  #ENDIF
+;	
+  #IF (Z180_CLKDIV == 1)
 	LD	A,(HB_CPUTYPE)	; GET CPU TYPE
 	CP	2		; Z8S180 REV K OR BETTER?
-	JR	C,HB_CPU2	; IF NOT, NOT POSSIBLE!
+	JR	C,HB_CPU3	; IF NOT, NOT POSSIBLE!
 	; SET CLOCK DIVIDE TO 1 RESULTING IN FULL XTAL SPEED
 	LD	A,$80
 	OUT0	(Z180_CCR),A
-	; REFLECT SPEED CHANGE
-	LD	C,CPUOSC / 1000000
-	LD	DE,CPUOSC / 1000
+	; HL ALREADY REFLECTS FULL SPEED OPERATION
   #ENDIF
-
+;
   #IF (Z180_CLKDIV >= 2)
 	LD	A,(HB_CPUTYPE)	; GET CPU TYPE
 	CP	3		; Z8S180 REV N OR BETTER?
-	JR	C,HB_CPU2	; IF NOT, NOT POSSIBLE!
+	JR	C,HB_CPU3	; IF NOT, NOT POSSIBLE!
 	; SET CPU MULTIPLIER TO 1 RESULTING IN XTAL * 2 SPEED
 	; ALSO SET CCR AGAIN BECAUSE OF REPORTS THAT CCR
 	; *MUST* BE SET AFTER CMR.
 	LD	A,$80
 	OUT0	(Z180_CMR),A	; CPU MULTIPLIER
 	OUT0	(Z180_CCR),A	; CLOCK DIVIDE
-	; REFLECT SPEED CHANGE
-	LD	C,(CPUOSC * 2) / 1000000
-	LD	DE,(CPUOSC * 2) / 1000
+	; ADJUST HL TO REFLECT DOUBLE SPEED OPERATION
+	SLA	L
+	RL	H
   #ENDIF
 ;
-HB_CPU2:
-	; SAVE CPU SPEED IN CONFIG BLOCK
-	LD	A,C
-	LD	(CB_CPUMHZ),A
-	LD	(CB_CPUKHZ),DE
-;
+HB_CPU3:
 #ENDIF
 ;
-	DIAG(%00011111)
-;
-; PERFORM DYNAMIC CPU SPEED DERIVATION
+; HL SHOULD NOW HAVE FINAL CPU RUNNING SPEED IN KHZ.
+; UPDATE CB_CPUMHZ/CB_CPUKHZ WITH THIS VALUE.
 ;
-	CALL	HB_CPUSPD		; CPU SPEED DETECTION
-;
-	LD	A,(CB_CPUMHZ)		; CPU SPEED TO ACCUM AND INIT
-	CALL	DELAY_INIT		; .. SPEED COMPENSATED DELAY
+	LD	(CB_CPUKHZ),HL		; UPDATE CPUKHZ
+	LD	DE,1000			; SET UP TO DIV BY 1000 FOR MHZ
+	CALL	DIV16			; BC=CPU MHZ, HL=REMAINDER
+	LD	DE,500			; SET UP TO ROUND UP
+	XOR	A			; IF WITHIN 500 KHZ
+	SBC	HL,DE			; REMAINDER - 500
+	CCF				; COMPLEMENT CF
+	ADC	A,C			; C -> A; ADD CF FOR ROUNDING
+	LD	(CB_CPUMHZ),A		; SAVE IT
 ;
 #IF (CPUFAM == CPU_Z180)
 ;
@@ -1855,6 +1908,9 @@ HB_CPU2:
 	LDCTL	(C),HL
 ;
 #ENDIF
+;
+	LD	A,(CB_CPUMHZ)		; CPU SPEED TO ACCUM AND INIT
+	CALL	DELAY_INIT		; .. SPEED COMPENSATED DELAY
 ;
 #IF (INTMODE == 2)
 	; SETUP Z80 IVT AND INT MODE 2
@@ -1931,6 +1987,8 @@ HB_CPU2:
 	; NOW IF DIVIDE BOTH SIDES BY 1000, WE CAN USE
 	; CPUKHZ VALUE AND SIMPLIFY TO
 	; RLDR = CPUKHZ
+	XOR	A			; ALL BITS ZERO
+	OUT0	(Z180_TCR),A		; ... INHIBITS TIMER OPERATION
 	LD	HL,(CB_CPUKHZ)		; 50HZ = 18432000 / 20 / 50 / X, SO X = CPU KHZ
 	OUT0	(Z180_TMDR0L),L		; INITIALIZE TIMER 0 DATA REGISTER
 	OUT0	(Z180_TMDR0H),H
@@ -1997,6 +2055,7 @@ Z280_TC	.EQU	CPUOSC / 4 / 50 / 2	; TIME CONSTANT
 	CALL	FILL			; DO IT
 ;
 	DIAG(%00111111)
+;
 #IF FALSE
 ;
 ; TEST DEBUG ***************************************************************************************
@@ -2025,8 +2084,6 @@ NOT_REC_M0:
 	CALL	CALLLIST							; PROCESS THE PRE-INIT CALL TABLE
 ;
 #IF (DSKYENABLE)
-	;CALL	DSKY_PREINIT
-
 	LD	HL,MSG_HBVER +  5
 	LD	A,(DSKY_HEXMAP + RMJ)
 	OR	$80
@@ -3812,14 +3869,18 @@ SYS_GETBNKINFO:
 ;
 SYS_GETCPUSPD:
 ;
-#IF ((PLATFORM == PLT_SBC) | (PLATFORM == PLT_MBC))
+#IF (((PLATFORM == PLT_SBC) | (PLATFORM == PLT_MBC)) & (CPUSPDCAP==SPD_HILO))
 	LD	A,(HB_RTCVAL)
 	BIT	3,A
+#IF (PLATFORM == PLT_SBC)
+	XOR	%00001000		; SBC SPEED BIT IS INVERTED
+#ENDIF
 	LD	L,0			; ASSUME HALF SPEED
 	JR	Z,SYS_GETCPUSPD1
 	LD	L,1
 SYS_GETCPUSPD1:
 	LD	DE,$FFFF		; UNKNOWN WAIT STATES
+;
 	XOR	A
 	RET
 #ENDIF
@@ -4040,9 +4101,9 @@ SYS_SETSECS:
 ;
 SYS_SETCPUSPD:
 ;
-#IF ((PLATFORM == PLT_SBC) | (PLATFORM == PLT_MBC))
+#IF (((PLATFORM == PLT_SBC) | (PLATFORM == PLT_MBC)) & (CPUSPDCAP==SPD_HILO))
 ;
-; WAIT STATE SETTINGS ARE IGNORED FOR Z80
+; NOTE: WAIT STATE SETTINGS ARE IGNORED FOR Z80
 ;
 	LD	A,L			; CLK SPD TO ACCUM
 	LD	C,%00000000		; HALF SPEED
@@ -4056,24 +4117,69 @@ SYS_SETCPUSPD1:
 	LD	A,(HB_RTCVAL)
 	AND	~%00001000		; CLEAR SPEED BIT
 	OR	C			; IMPLEMENT NEW SPEED BIT
+#IF (PLATFORM == PLT_SBC)
+	; SBC SPEED BIT IS INVERTED, ADJUST IT
+	LD	A,C
+	XOR	%00001000
+	LD	C,A
+#ENDIF
 	LD	(HB_RTCVAL),A		; SAVE IN SHADOW REGISTER
 	OUT	(RTCIO),A		; UPDATE HARDWARE REGISTER
+;
+	; UPDATE THE CURRENT CPU SPEED IN HCB!
+	LD	A,L
+	LD	HL,(HB_CPUOSC)		; ASSUME FULL SPEED
+	CP	1			; CHECK FOR 1 (FULL SPEED)
+	JR	Z,SYS_SETCPUSPD2	; IF SO, ALL DONE
+	; ADJUST HL TO REFLECT HALF SPEED OPERATION
+	SRL	H		; ADJUST HL ASSUMING
+	RR	L		; HALF SPEED OPERATION
+;
+SYS_SETCPUSPD2:
+;
+; HL SHOULD NOW HAVE FINAL CPU RUNNING SPEED IN KHZ.
+; UPDATE CB_CPUMHZ/CB_CPUKHZ WITH THIS VALUE.
+;
+	LD	(CB_CPUKHZ),HL		; UPDATE CPUKHZ
+	LD	DE,1000			; SET UP TO DIV BY 1000 FOR MHZ
+	CALL	DIV16			; BC=CPU MHZ, HL=REMAINDER
+	LD	DE,500			; SET UP TO ROUND UP
+	XOR	A			; IF WITHIN 500 KHZ
+	SBC	HL,DE			; REMAINDER - 500
+	CCF				; COMPLEMENT CF
+	ADC	A,C			; C -> A; ADD CF FOR ROUNDING
+	LD	(CB_CPUMHZ),A		; SAVE IT
+;
+	;  REINIT DELAY ROUTINE
+	LD	A,(CB_CPUMHZ)		; CPU SPEED TO ACCUM AND INIT
+	CALL	DELAY_INIT		; .. SPEED COMPENSATED DELAY
+;
 	XOR	A
 	RET
 #ENDIF
 ;
 #IF (CPUFAM == CPU_Z180)
+	PUSH	DE			; SAVE WAIT STATES FOR NOW
 	LD	A,L			; CLK SPD TO ACCUM
 	LD	B,0			; B HAS BIT FOR CMR
 	LD	C,0			; C HAS BIT FOR CCR
 	CP	2			; DOUBLE SPEED?
-	JR	C,SYS_SETCPUSPD1
-	LD	B,%10000000
+	JR	C,SYS_SETCPUSPD1	; <2?, SKIP AHEAD
+	LD	B,%10000000		; SET CMR BIT
 SYS_SETCPUSPD1:
-	CP	1
-	JR	C,SYS_SETCPUSPD2
-	LD	C,%10000000
+	CP	1			; FULL SPEED?
+	JR	C,SYS_SETCPUSPD2	; <1?, SKIP AHEAD
+	LD	C,%10000000		; SET CCR BIT
 SYS_SETCPUSPD2:
+	; BEFORE IMPLEMENTING THE NEW CPU SPEED, WE SWITCH THE
+	; WAIT STATES TO MAXIMUM BECAUSE WE MAY BE IMPLEMENTING
+	; SLOWER WAIT STATES REQUIRED BY THE NEW SPEED.  WE SAVE
+	; THE ORIGINAL WAIT STATES REGISTER VALUE ON STACK
+	IN0	A,(Z180_DCNTL)		; GET CURRENT REGISTER VALUE
+	LD	E,A			; PUT IN L
+	PUSH	DE			; SAVE FOR LATER
+	OR	%11110000		; MAX WAIT STATES
+	OUT0	(Z180_DCNTL),A		; DO IT
 ;
 	IN0	A,(Z180_CMR)
 	AND	~%10000000
@@ -4084,6 +4190,105 @@ SYS_SETCPUSPD2:
 	AND	~%10000000
 	OR	C
 	OUT0	(Z180_CCR),A
+;
+	; UPDATE THE CURRENT CPU SPEED IN HCB!
+	LD	A,L			; SETTING TO A
+	LD	HL,(HB_CPUOSC)		; START WITH CPU OSC VALUE
+	; ADJUST HL TO REFLECT HALF SPEED OPERATION
+	SRL	H			; ADJUST HL ASSUMING
+	RR	L			; HALF SPEED OPERATION
+	OR	A			; CHECK FOR HALF SPEED
+	JR	Z,SETCPUSPD2A		; IF SO, DONE
+	; ADJUST HL TO REFLECT FULL SPEED OPERATION
+	SLA	L
+	RL	H
+	CP	1			; CHECK FOR FULL SPEED
+	JR	Z,SETCPUSPD2A		; IF SO DONE
+	; ADJUST HL TO REFLECT DOUBLE SPEED OPERATION
+	SLA	L
+	RL	H
+;
+SETCPUSPD2A:
+;
+; HL SHOULD NOW HAVE FINAL CPU RUNNING SPEED IN KHZ.
+; UPDATE CB_CPUMHZ/CB_CPUKHZ WITH THIS VALUE.
+;
+	LD	(CB_CPUKHZ),HL		; UPDATE CPUKHZ
+	LD	DE,1000			; SET UP TO DIV BY 1000 FOR MHZ
+	CALL	DIV16			; BC=CPU MHZ, HL=REMAINDER
+	LD	DE,500			; SET UP TO ROUND UP
+	XOR	A			; IF WITHIN 500 KHZ
+	SBC	HL,DE			; REMAINDER - 500
+	CCF				; COMPLEMENT CF
+	ADC	A,C			; C -> A; ADD CF FOR ROUNDING
+	LD	(CB_CPUMHZ),A		; SAVE IT
+;
+	; NOW IMPLEMENT ANY WAIT STATE CHANGES.
+	POP	HL			; INIT L WITH ORIG VALUE
+	POP	DE			; RECOVER WAIT STATES
+	LD	A,D			; GET MEM WS
+	CP	$FF			; SKIP?
+	JR	Z,SYS_SETCPUSPD3	; IF SO, GO AHEAD
+	AND	%00000011		; JUST TWO BITS
+	RRCA				; MEM WS IS TOP TWO BITS
+	RRCA
+	LD	H,A			; MOVE WS BITS TO H
+	LD	A,L			; CUR VALUE TO A
+	AND	%00111111		; MASK OFF MEM WS BITS
+	OR	H			; SET NEW MEM WS BITS
+	LD	L,A			; BACK TO L
+;
+SYS_SETCPUSPD3:
+;
+	LD	A,E			; GET I/O WS
+	CP	$FF			; SKIP?
+	JR	Z,SYS_SETCPUSPD4	; IF SO, GO AHEAD
+	DEC	A			; ADJUST FOR BUILT-IN I/O WS
+	AND	%00000011		; JUST TWO BITS
+	RRCA				; I/O WS IS BITS 5-4
+	RRCA
+	RRCA
+	RRCA
+	LD	H,A			; MOVE WS BITS TO H
+	LD	A,L			; CUR VALUE TO A
+	AND	%11001111		; MASK OFF I/O WS BITS
+	OR	H			; SET NEW I/O WS BITS
+	LD	L,A			; BACK TO L
+;
+SYS_SETCPUSPD4:
+	LD	A,L			; WORKING VALUE TO A
+	OUT0	(Z180_DCNTL),A		; IMPLEMENT NEW VALUE
+;
+	;  REINIT DELAY ROUTINE
+	LD	A,(CB_CPUMHZ)		; CPU SPEED TO ACCUM AND INIT
+	CALL	DELAY_INIT		; .. SPEED COMPENSATED DELAY
+;
+  #IF ((INTMODE == 2) & (Z180_TIMER))
+	; THE Z180 TIMER IS BASED ON CPU SPEED.  SO HERE
+	; WE RECOMPUTE THE TIMER CONSTANTS BASED ON THE NEW SPEED.
+	XOR	A			; ALL BITS ZERO
+	OUT0	(Z180_TCR),A		; ... INHIBITS TIMER OPERATION
+	LD	HL,(CB_CPUKHZ)		; 50HZ = 18432000 / 20 / 50 / X, SO X = CPU KHZ
+	OUT0	(Z180_TMDR0L),L		; INITIALIZE TIMER 0 DATA REGISTER
+	OUT0	(Z180_TMDR0H),H
+	DEC	HL			; RELOAD OCCURS *AFTER* ZERO
+	OUT0	(Z180_RLDR0L),L		; INITIALIZE TIMER 0 RELOAD REGISTER
+	OUT0	(Z180_RLDR0H),H
+	LD	A,%00010001		; ENABLE TIMER0 INT AND DOWN COUNTING
+	OUT0	(Z180_TCR),A
+  #ENDIF
+;
+  #IF (ASCIENABLE)
+	; RESET THE ASCI PORTS IN CASE SPEED CHANGED!
+	; N.B., THIS WILL FAIL IF THE CURRENT BAUD RATE
+	; IS IMPOSSIBLE TO IMPLEMENT AT THE NEW CPU SPEED!!!
+	LD	DE,-1
+	LD	IY,ASCI0_CFG
+	CALL	ASCI_INITDEV
+	LD	DE,-1
+	LD	IY,ASCI1_CFG
+	CALL	ASCI_INITDEV
+  #ENDIF
 ;
 	XOR	A
 	RET
@@ -5595,16 +5800,8 @@ HB_CPUSPD1:
 	SLA	L
 	RL	H
 ;
-	LD	(CB_CPUKHZ),HL		; HL=CPU SPEED IN KHZ
-	LD	DE,1000			; SET UP TO DIV BY 1000 FOR MHZ
-	CALL	DIV16			; BC=CPU MHZ, HL=REMAINDER
-	LD	DE,500			; SET UP TO ROUND UP
-	XOR	A			; IF WITHIN 500 KHZ
-	SBC	HL,DE			; REMAINDER - 500
-	CCF				; COMPLEMENT CF
-	ADC	A,C			; C -> A; ADD CF FOR ROUNDING
-	LD	(CB_CPUMHZ),A		; SAVE IT
-;
+	; RETURN CURRENT CPU SPD (KHZ) IN HL
+	XOR	A			; SIGNAL SUCCESS
 	RET
 ;
 HB_WAITSEC:
@@ -5657,6 +5854,7 @@ HB_RDSEC:
 ;
   #ELSE
 ;
+	OR	$FF			; SIGNAL ERROR
 	RET				; NO RTC, ABORT
 ;
 #ENDIF
@@ -6536,6 +6734,7 @@ HB_SECTCK	.DB	TICKFREQ	; TICK COUNTER FOR FRACTIONAL SECONDS
 HB_SECS		.FILL	4,0		; 32 BIT SECONDS COUNTER
 ;
 HB_CPUTYPE	.DB	0		; 0=Z80, 1=80180, 2=SL1960, 3=ASCI BRG
+HB_CPUOSC	.DW	CPUOSC		; ACTUAL CPU HARDWARE OSC FREQ IN KHZ
 ;
 IOPRVAL		.DW	0		; TEMP STORAGE FOR IOPR
 ;

Source/Images/fd_bp.txt

@@ -11,6 +11,7 @@
 #
 #../../Binary/Apps/*.com 15:
 ../../Binary/Apps/assign.com 15:
+../../Binary/Apps/cpuspd.com 15:
 ../../Binary/Apps/fat.com 15:
 ../../Binary/Apps/fdu.com 15:
 ../../Binary/Apps/fdu.doc 15:

Source/Images/fd_cpm22.txt

@@ -7,6 +7,7 @@ d_cpm22/ReadMe.txt 0:
 #
 #../../Binary/Apps/*.com 0:
 ../../Binary/Apps/assign.com 0:
+../../Binary/Apps/cpuspd.com 0:
 ../../Binary/Apps/fat.com 0:
 ../../Binary/Apps/fdu.com 0:
 ../../Binary/Apps/fdu.doc 0:

Source/Images/fd_cpm3.txt

@@ -23,6 +23,7 @@
 #
 #../../Binary/Apps/*.com 0:
 ../../Binary/Apps/assign.com 0:
+../../Binary/Apps/cpuspd.com 0:
 ../../Binary/Apps/fat.com 0:
 ../../Binary/Apps/fdu.com 0:
 ../../Binary/Apps/fdu.doc 0:

Source/Images/fd_nzcom.txt

@@ -7,6 +7,7 @@ d_nzcom/ReadMe.txt 0:
 #
 #../../Binary/Apps/*.com 0:
 ../../Binary/Apps/assign.com 0:
+../../Binary/Apps/cpuspd.com 0:
 ../../Binary/Apps/fat.com 0:
 ../../Binary/Apps/fdu.com 0:
 ../../Binary/Apps/rtc.com 0:

Source/Images/fd_zpm3.txt

@@ -22,6 +22,7 @@
 #
 #../../Binary/Apps/*.com 15:
 ../../Binary/Apps/assign.com 15:
+../../Binary/Apps/cpuspd.com 15:
 ../../Binary/Apps/fat.com 15:
 ../../Binary/Apps/fdu.com 15:
 ../../Binary/Apps/fdu.doc 15:

Source/Images/fd_zsdos.txt

@@ -20,6 +20,7 @@ d_cpm22/u0/XSUB.COM 0:
 #
 #../../Binary/Apps/*.com 0:
 ../../Binary/Apps/assign.com 0:
+../../Binary/Apps/cpuspd.com 0:
 ../../Binary/Apps/fat.com 0:
 ../../Binary/Apps/fdu.com 0:
 ../../Binary/Apps/fdu.doc 0:

Source/Images/hd_bp.txt

@@ -11,6 +11,7 @@
 #
 #../../Binary/Apps/*.com 15:
 ../../Binary/Apps/assign.com 15:
+../../Binary/Apps/cpuspd.com 15:
 ../../Binary/Apps/fat.com 15:
 ../../Binary/Apps/fdu.com 15:
 ../../Binary/Apps/fdu.doc 15:

Source/Images/hd_cpm22.txt

@@ -7,6 +7,7 @@ d_cpm22/ReadMe.txt 0:
 #
 #../../Binary/Apps/*.com 0:
 ../../Binary/Apps/assign.com 0:
+../../Binary/Apps/cpuspd.com 0:
 ../../Binary/Apps/fat.com 0:
 ../../Binary/Apps/fdu.com 0:
 ../../Binary/Apps/fdu.doc 0:

Source/Images/hd_cpm3.txt

@@ -23,6 +23,7 @@
 #
 #../../Binary/Apps/*.com 0:
 ../../Binary/Apps/assign.com 0:
+../../Binary/Apps/cpuspd.com 0:
 ../../Binary/Apps/fat.com 0:
 ../../Binary/Apps/fdu.com 0:
 ../../Binary/Apps/fdu.doc 0:

Source/Images/hd_nzcom.txt

@@ -24,6 +24,7 @@ d_zsdos/u0/*.* 0:
 #
 #../../Binary/Apps/*.com 0:
 ../../Binary/Apps/assign.com 0:
+../../Binary/Apps/cpuspd.com 0:
 ../../Binary/Apps/fat.com 0:
 ../../Binary/Apps/fdu.com 0:
 ../../Binary/Apps/fdu.doc 0:

Source/Images/hd_zpm3.txt

@@ -22,6 +22,7 @@
 #
 #../../Binary/Apps/*.com 15:
 ../../Binary/Apps/assign.com 15:
+../../Binary/Apps/cpuspd.com 15:
 ../../Binary/Apps/fat.com 15:
 ../../Binary/Apps/fdu.com 15:
 ../../Binary/Apps/fdu.doc 15:

Source/Images/hd_zsdos.txt

@@ -20,6 +20,7 @@ d_cpm22/u0/XSUB.COM 0:
 #
 #../../Binary/Apps/*.com 0:
 ../../Binary/Apps/assign.com 0:
+../../Binary/Apps/cpuspd.com 0:
 ../../Binary/Apps/fat.com 0:
 ../../Binary/Apps/fdu.com 0:
 ../../Binary/Apps/fdu.doc 0:

Source/RomDsk/Build.cmd

@@ -12,7 +12,7 @@ set ZXLIBDIR=%TOOLS%/cpm/lib/
 set ZXINCDIR=%TOOLS%/cpm/include/
 
 set RomApps1=assign mode rtc syscopy xm
-set RomApps2=fdu format survey sysgen talk timer
+set RomApps2=fdu format survey sysgen talk timer cpuspd
 
 ::
 :: Make all variants of the ROM Disk contents image.  Three sizes are

Source/RomDsk/Makefile

@@ -7,7 +7,7 @@ include $(TOOLS)/Makefile.inc
 .SHELLFLAGS = -ce
 
 ROMAPPS1 := assign mode rtc syscopy xm
-ROMAPPS2 := fdu format survey sysgen talk timer
+ROMAPPS2 := fdu format survey sysgen talk timer cpuspd
 
 rom256_%.dat: ROMSIZ=256
 rom512_%.dat: ROMSIZ=512

Source/ver.inc

@@ -2,4 +2,4 @@
 #DEFINE	RMN	1
 #DEFINE	RUP	1
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"3.1.1-pre.151"
+#DEFINE BIOSVER	"3.1.1-pre.152"

Source/ver.lib

@@ -3,5 +3,5 @@ rmn	equ	1
 rup	equ	1
 rtp	equ	0
 biosver	macro
-	db	"3.1.1-pre.151"
+	db	"3.1.1-pre.152"
 	endm