jwaymire
/
Pegasys-RomWBW
forked from MirrorRepos/RomWBW
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity
Browse Source

Support Secondary SPI on SC126

patch
Wayne Warthen 6 years ago
parent
af2a9a7110
commit
bd2fc6dbfe
16 changed files with 41 additions and 6 deletions
Whitespace
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
Split View
Diff Options
Show Stats Download Patch File Download Diff File
  1. 1
      Doc/ChangeLog.txt
  2. 2
      ReadMe.txt
  3. 2
      Source/CBIOS/ver.inc
  4. 2
      Source/HBIOS/Config/SCZ180_126.asm
  5. 1
      Source/HBIOS/cfg_ezz80.asm
  6. 1
      Source/HBIOS/cfg_master.asm
  7. 1
      Source/HBIOS/cfg_mk4.asm
  8. 1
      Source/HBIOS/cfg_n8.asm
  9. 1
      Source/HBIOS/cfg_rcz180.asm
  10. 1
      Source/HBIOS/cfg_rcz80.asm
  11. 1
      Source/HBIOS/cfg_sbc.asm
  12. 1
      Source/HBIOS/cfg_scz180.asm
  13. 1
      Source/HBIOS/cfg_zeta.asm
  14. 1
      Source/HBIOS/cfg_zeta2.asm
  15. 28
      Source/HBIOS/sd.asm
  16. 2
      Source/HBIOS/ver.inc

1
Doc/ChangeLog.txt
View File

@ -23,6 +23,7 @@ Version 2.9.2
- WBW: DSRTC now detects DS-1302 presence dynamically
- WBW: SC126 platform renamed to SCZ180 w/ configs for SC126, SC130
- WBW: Add status LED support
- WBW: Add support for secondry SPI (SD Card) on SC126
Version 2.9.1
-------------

2
ReadMe.txt
View File

@ -7,7 +7,7 @@
***********************************************************************
Wayne Warthen (wwarthen@gmail.com)
Version 2.9.2-pre.15, 2019-10-08
Version 2.9.2-pre.16, 2019-10-09
https://www.retrobrewcomputers.org/
RomWBW is a ROM-based implementation of CP/M-80 2.2 and Z-System for

2
Source/CBIOS/ver.inc
View File

@ -2,4 +2,4 @@
#DEFINE RMN 9
#DEFINE RUP 2
#DEFINE RTP 0
#DEFINE BIOSVER "2.9.2-pre.15 "
#DEFINE BIOSVER "2.9.2-pre.16"

2
Source/HBIOS/Config/SCZ180_126.asm
View File

@ -48,3 +48,5 @@ IDEMODE .SET IDEMODE_RC ; IDE: DRIVER MODE: IDEMODE_[DIO|DIDE]
PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
;
SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDCNT .SET 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY

1
Source/HBIOS/cfg_ezz80.asm
View File

@ -125,6 +125,7 @@ PPIDE8BIT .EQU FALSE ; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
;
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC]
SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
;

1
Source/HBIOS/cfg_master.asm
View File

@ -167,6 +167,7 @@ PPIDE8BIT .EQU FALSE ; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
;
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_NONE ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC]
SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
;

1
Source/HBIOS/cfg_mk4.asm
View File

@ -125,6 +125,7 @@ PPIDE8BIT .EQU FALSE ; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
;
SDENABLE .EQU TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_MK4 ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC]
SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
SDCSIOFAST .EQU TRUE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
;

1
Source/HBIOS/cfg_n8.asm
View File

@ -128,6 +128,7 @@ PPIDE8BIT .EQU FALSE ; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
;
SDENABLE .EQU TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_CSIO ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC]
SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
;

1
Source/HBIOS/cfg_rcz180.asm
View File

@ -131,6 +131,7 @@ PPIDE8BIT .EQU FALSE ; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
;
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC]
SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
;

1
Source/HBIOS/cfg_rcz80.asm
View File

@ -134,6 +134,7 @@ PPIDE8BIT .EQU FALSE ; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
;
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC]
SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
;

1
Source/HBIOS/cfg_sbc.asm
View File

@ -125,6 +125,7 @@ PPIDE8BIT .EQU FALSE ; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
;
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_JUHA ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC]
SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
;

1
Source/HBIOS/cfg_scz180.asm
View File

@ -126,6 +126,7 @@ PPIDE8BIT .EQU FALSE ; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
;
SDENABLE .EQU TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_SC ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC]
SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
;

1
Source/HBIOS/cfg_zeta.asm
View File

@ -104,6 +104,7 @@ PPIDE8BIT .EQU FALSE ; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
;
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC]
SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
;

1
Source/HBIOS/cfg_zeta2.asm
View File

@ -108,6 +108,7 @@ PPIDE8BIT .EQU FALSE ; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
;
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC]
SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
;

28
Source/HBIOS/sd.asm
View File

@ -173,7 +173,7 @@ SD_DO .EQU %00100000 ; UART MSR:5 IS DATA OUT (CARD -> CPU)
#ENDIF
;
#IF (SDMODE == SDMODE_DSD) ; DUAL SD
SD_DEVCNT .EQU 2 ; NUMBER OF PHYSICAL UNITS (SOCKETS)
SD_DEVCNT .EQU SDCNT ; NUMBER OF PHYSICAL UNITS (SOCKETS)
SD_OPRREG .EQU $08 ; DEDICATED OPERATIONS REGISTER
SD_OPRDEF .EQU %00000001 ; QUIESCENT STATE
SD_INPREG .EQU SD_OPRREG ; INPUT REGISTER IS OPRREG
@ -195,10 +195,11 @@ SD_TRDR .EQU Z180_TRDR
#ENDIF
;
#IF (SDMODE == SDMODE_SC) ; SC
SD_DEVCNT .EQU 1 ; NUMBER OF PHYSICAL UNITS (SOCKETS)
SD_DEVCNT .EQU SDCNT ; NUMBER OF PHYSICAL UNITS (SOCKETS)
SD_OPRREG .EQU RTCIO ; USES RTC LATCHES FOR OPERATION
SD_OPRDEF .EQU %00001100 ; QUIESCENT STATE (/CS1 & /CS2 DEASSERTED)
SD_CS .EQU %00000100 ; RTC:2 IS SELECT FOR PRIMARY SPI CARD
SD_CS0 .EQU %00000100 ; RTC:2 IS SELECT FOR PRIMARY SPI CARD
SD_CS1 .EQU %00001000 ; RTC:3 IS SELECT FOR SECONDARY SPI CARD
SD_CNTR .EQU Z180_CNTR
SD_TRDR .EQU Z180_TRDR
#ENDIF
@ -1464,7 +1465,23 @@ SD_CHKWP:
SD_SELECT:
LD A,(SD_OPRVAL)
#IF ((SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_UART) | (SDMODE == SDMODE_SC))
#IF (SDMODE == SDMODE_SC)
LD A,(IY+SD_DEV) ; GET CURRENT DEVICE
OR A ; SET FLAGS
LD A,(SD_OPRVAL) ; GET CURRENT OPRVAL BACK
JR NZ,SD_SELECT1 ; IF NOT ZERO, DO SECONDARY
; ASSERT PRIMARY CS, DEASSERT SECONDARY
AND ~SD_CS0
OR SD_CS1
JR SD_SELECT2
SD_SELECT1:
; DEASSERT PRIMARY CS, ASSERT SECONDARY
OR SD_CS0
AND ~SD_CS1
SD_SELECT2:
#ELSE
AND ~SD_CS ; SET SD_CS (CHIP SELECT)
#ENDIF
#ELSE
OR SD_CS ; SET SD_CS (CHIP SELECT)
#ENDIF
@ -1477,7 +1494,12 @@ SD_SELECT:
SD_DESELECT:
LD A,(SD_OPRVAL)
#IF ((SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_UART) | (SDMODE == SDMODE_SC))
#IF (SDMODE == SDMODE_SC)
OR SD_CS0 ; RESET PRIMARY CHIP SELECT
OR SD_CS1 ; RESET SECONDARY CHIP SELECT
#ELSE
OR SD_CS ; RESET SD_CS (CHIP SELECT)
#ENDIF
#ELSE
AND ~SD_CS ; RESET SD_CS (CHIP SELECT)
#ENDIF

2
Source/HBIOS/ver.inc
View File

@ -2,4 +2,4 @@
#DEFINE RMN 9
#DEFINE RUP 2
#DEFINE RTP 0
#DEFINE BIOSVER "2.9.2-pre.15"
#DEFINE BIOSVER "2.9.2-pre.16"

Write Preview
Loading…
Cancel
Save