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Minor Z280 Fixes 

- Fixed the ROM VERIFY functionality on Z280.  It was indicating errors incorrectly.
- Revised the way that ZZRCC is built to remove a bunch of complexity that was causing issues.  An implication of this is that ZZRCC now treats the data loaded from the CF Card as a ROM disk instead of a RAM disk.
- Updated the assemblers to handle some more Z280 instructions used in HBIOS.
- When building ZZRCC, checks have been added to ensure the ROM image is exactly 256K.  The build defaults to 512K and that causes the ZZRCC disk image to be corrupted.  This will stop the build if the user fails to specify a 256K ROM size.
patch v3.1.1-pre.157
Wayne Warthen 4 years ago
parent
e6b9d2dcfd
commit
bf965c2604
21 changed files with 111 additions and 69 deletions
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  1. 11
      Source/HBIOS/Config/RCZ280_nat_zzr.asm
  2. 3
      Source/HBIOS/cfg_dyno.asm
  3. 3
      Source/HBIOS/cfg_ezz80.asm
  4. 3
      Source/HBIOS/cfg_master.asm
  5. 3
      Source/HBIOS/cfg_mbc.asm
  6. 3
      Source/HBIOS/cfg_mk4.asm
  7. 3
      Source/HBIOS/cfg_n8.asm
  8. 3
      Source/HBIOS/cfg_rcz180.asm
  9. 3
      Source/HBIOS/cfg_rcz280.asm
  10. 3
      Source/HBIOS/cfg_rcz80.asm
  11. 3
      Source/HBIOS/cfg_sbc.asm
  12. 3
      Source/HBIOS/cfg_scz180.asm
  13. 2
      Source/HBIOS/cfg_una.asm
  14. 3
      Source/HBIOS/cfg_zeta.asm
  15. 3
      Source/HBIOS/cfg_zeta2.asm
  16. 73
      Source/HBIOS/hbios.asm
  17. 34
      Source/HBIOS/std.asm
  18. 2
      Source/ver.inc
  19. 2
      Source/ver.lib
  20. 10
      Tools/tasm32/TASM280.TAB
  21. 7
      Tools/unix/uz80as/z80.c

11
Source/HBIOS/Config/RCZ280_nat_zzr.asm
View File

@ -30,14 +30,13 @@
;
CPUOSC .SET 29491200 ; CPU OSC FREQ IN MHZ
;
RAMSIZE .SET 384 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
PLT_RAM_R .SET 128 ; RESERVE FIRST N KB OF RAM (USUALLY 0)
PLT_ROM_R .SET 0 ; RESERVE FIRST N KB OR ROM (USUALLY 0)
RAMSIZE .SET 256 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
ROMSIZE_CHK .SET 256 ; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
;
RAMLOC .SET 23 ; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
RAMLOC .SET 18 ; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
RAMBIAS .SET (1 << (RAMLOC - 10)) ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
;
MDROM .SET FALSE ; MD: ENABLE ROM DISK
MDRAM .SET TRUE ; MD: ENABLE RAM DISK
MDROM .SET TRUE ; MD: ENABLE ROM DISK
MDRAM .SET FALSE ; MD: ENABLE RAM DISK
;
Z2U0HFC .SET TRUE ; Z2U 0: ENABLE HARDWARE FLOW CONTROL

3
Source/HBIOS/cfg_dyno.asm
View File

@ -32,8 +32,7 @@ INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
PLT_RAM_R .EQU 0 ; RESERVE FIRST N KB OF RAM (USUALLY 0)
PLT_ROM_R .EQU 0 ; RESERVE FIRST N KB OR ROM (USUALLY 0)
ROMSIZE_CHK .EQU 0 ; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
MEMMGR .EQU MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
RAMLOC .EQU 19 ; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
RAMBIAS .EQU (1 << (RAMLOC - 10)) ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE

3
Source/HBIOS/cfg_ezz80.asm
View File

@ -32,8 +32,7 @@ INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
DEFSERCFG .EQU SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
PLT_RAM_R .EQU 0 ; RESERVE FIRST N KB OF RAM (USUALLY 0)
PLT_ROM_R .EQU 0 ; RESERVE FIRST N KB OR ROM (USUALLY 0)
ROMSIZE_CHK .EQU 0 ; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
MEMMGR .EQU MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
MPGSEL_1 .EQU $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)

3
Source/HBIOS/cfg_master.asm
View File

@ -29,8 +29,7 @@ INTMODE .EQU 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
PLT_RAM_R .EQU 0 ; RESERVE FIRST N KB OF RAM (USUALLY 0)
PLT_ROM_R .EQU 0 ; RESERVE FIRST N KB OR ROM (USUALLY 0)
ROMSIZE_CHK .EQU 0 ; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
MEMMGR .EQU MM_NONE ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
RAMLOC .EQU 19 ; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
RAMBIAS .EQU (1 << (RAMLOC - 10)) ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE

3
Source/HBIOS/cfg_mbc.asm
View File

@ -32,8 +32,7 @@ INTMODE .EQU 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
PLT_RAM_R .EQU 0 ; RESERVE FIRST N KB OF RAM (USUALLY 0)
PLT_ROM_R .EQU 0 ; RESERVE FIRST N KB OR ROM (USUALLY 0)
ROMSIZE_CHK .EQU 0 ; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
MEMMGR .EQU MM_MBC ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
MPCL_RAM .EQU $78 ; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
MPCL_ROM .EQU $7C ; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)

3
Source/HBIOS/cfg_mk4.asm
View File

@ -32,8 +32,7 @@ INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
PLT_RAM_R .EQU 0 ; RESERVE FIRST N KB OF RAM (USUALLY 0)
PLT_ROM_R .EQU 0 ; RESERVE FIRST N KB OR ROM (USUALLY 0)
ROMSIZE_CHK .EQU 0 ; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
MEMMGR .EQU MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
RAMLOC .EQU 19 ; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
RAMBIAS .EQU (1 << (RAMLOC - 10)) ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE

3
Source/HBIOS/cfg_n8.asm
View File

@ -32,8 +32,7 @@ INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
PLT_RAM_R .EQU 0 ; RESERVE FIRST N KB OF RAM (USUALLY 0)
PLT_ROM_R .EQU 0 ; RESERVE FIRST N KB OR ROM (USUALLY 0)
ROMSIZE_CHK .EQU 0 ; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
MEMMGR .EQU MM_N8 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
RAMBIAS .EQU 0 ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
RAMLOC .EQU 0 ; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE

3
Source/HBIOS/cfg_rcz180.asm
View File

@ -32,8 +32,7 @@ INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
DEFSERCFG .EQU SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
PLT_RAM_R .EQU 0 ; RESERVE FIRST N KB OF RAM (USUALLY 0)
PLT_ROM_R .EQU 0 ; RESERVE FIRST N KB OR ROM (USUALLY 0)
ROMSIZE_CHK .EQU 0 ; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
MEMMGR .EQU MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
RAMLOC .EQU 19 ; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
RAMBIAS .EQU (1 << (RAMLOC - 10)) ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE

3
Source/HBIOS/cfg_rcz280.asm
View File

@ -32,8 +32,7 @@ INTMODE .EQU 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
DEFSERCFG .EQU SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
PLT_RAM_R .EQU 0 ; RESERVE FIRST N KB OF RAM (USUALLY 0)
PLT_ROM_R .EQU 0 ; RESERVE FIRST N KB OR ROM (USUALLY 0)
ROMSIZE_CHK .EQU 0 ; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
MEMMGR .EQU MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
RAMLOC .EQU 19 ; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
RAMBIAS .EQU (1 << (RAMLOC - 10)) ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE

3
Source/HBIOS/cfg_rcz80.asm
View File

@ -32,8 +32,7 @@ INTMODE .EQU 1 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
DEFSERCFG .EQU SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
PLT_RAM_R .EQU 0 ; RESERVE FIRST N KB OF RAM (USUALLY 0)
PLT_ROM_R .EQU 0 ; RESERVE FIRST N KB OR ROM (USUALLY 0)
ROMSIZE_CHK .EQU 0 ; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
MEMMGR .EQU MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
MPGSEL_1 .EQU $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)

3
Source/HBIOS/cfg_sbc.asm
View File

@ -32,8 +32,7 @@ INTMODE .EQU 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
PLT_RAM_R .EQU 0 ; RESERVE FIRST N KB OF RAM (USUALLY 0)
PLT_ROM_R .EQU 0 ; RESERVE FIRST N KB OR ROM (USUALLY 0)
ROMSIZE_CHK .EQU 0 ; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
MEMMGR .EQU MM_SBC ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
MPCL_RAM .EQU $78 ; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
MPCL_ROM .EQU $7C ; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)

3
Source/HBIOS/cfg_scz180.asm
View File

@ -32,8 +32,7 @@ INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
DEFSERCFG .EQU SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
PLT_RAM_R .EQU 0 ; RESERVE FIRST N KB OF RAM (USUALLY 0)
PLT_ROM_R .EQU 0 ; RESERVE FIRST N KB OR ROM (USUALLY 0)
ROMSIZE_CHK .EQU 0 ; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
MEMMGR .EQU MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
RAMLOC .EQU 19 ; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
RAMBIAS .EQU (1 << (RAMLOC - 10)) ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE

2
Source/HBIOS/cfg_una.asm
View File

@ -26,8 +26,6 @@ CPUOSC .EQU 18432000 ; CPU OSC FREQ IN MHZ
INTMODE .EQU 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
PLT_RAM_R .EQU 0 ; RESERVE FIRST N KB OF RAM (USUALLY 0)
PLT_ROM_R .EQU 0 ; RESERVE FIRST N KB OR ROM (USUALLY 0)
;
RTCIO .EQU $70 ; RTC LATCH REGISTER ADR
;

3
Source/HBIOS/cfg_zeta.asm
View File

@ -32,8 +32,7 @@ INTMODE .EQU 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
PLT_RAM_R .EQU 0 ; RESERVE FIRST N KB OF RAM (USUALLY 0)
PLT_ROM_R .EQU 0 ; RESERVE FIRST N KB OR ROM (USUALLY 0)
ROMSIZE_CHK .EQU 0 ; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
MEMMGR .EQU MM_SBC ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
MPCL_RAM .EQU $78 ; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
MPCL_ROM .EQU $7C ; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)

3
Source/HBIOS/cfg_zeta2.asm
View File

@ -32,8 +32,7 @@ INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
PLT_RAM_R .EQU 0 ; RESERVE FIRST N KB OF RAM (USUALLY 0)
PLT_ROM_R .EQU 0 ; RESERVE FIRST N KB OR ROM (USUALLY 0)
ROMSIZE_CHK .EQU 0 ; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
MEMMGR .EQU MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
MPGSEL_1 .EQU $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)

73
Source/HBIOS/hbios.asm
View File

@ -87,6 +87,20 @@ MODCNT .SET MODCNT + 1
!!! ; FORCE AN ASSEMBLY ERROR
#ENDIF
;
; SOME HARDWARE REQUIRES A SPECIFIC ROMSIZE (NOTABLY ZZRCC) OR THE
; RESULTING BUILD IMAGES WILL BE CORRUPT. ROMSIZE_CHK IS SPECIFIED
; IN THE CONFIG FILE AND IS VERIFIED AGAINST THE ROMSIZE BEING USED
; BY THE BUILD. A ROMSIZE_CHK VALUE OF 0 INDICATES THE VERFICATION
; IS DISABLED (WHICH IT USUALLY IS).
;
#IF (ROMSIZE_CHK != 0) & (ROMSIZE != ROMSIZE_CHK)
.ECHO "*** ERROR: ROMSIZE VALUE VERIFICATION FAILURE.\n"
.ECHO "THIS CONFIGURATION REQUIRES A ROMSIZE OF " \ .ECHO ROMSIZE_CHK \ .ECHO ".\n"
.ECHO "BUILD IS USING A ROMSIZE OF " \ .ECHO ROMSIZE \ .ECHO ".\n"
.ECHO "SEE COMMENTS IN HBIOS.ASM.\n"
!!! ; FORCE AN ASSEMBLY ERROR
#ENDIF
;
;
;
#IF (DIAGENABLE)
@ -129,7 +143,7 @@ MODCNT .SET MODCNT + 1
#IF (INTMODE == 3)
; Z280 MODE 3 INTERRUPT HANDLING (INTA, C/T 0, & UART RCVR ENABLED)
#DEFINE HB_DI DI
#DEFINE HB_EI .DB $ED,$7F,$0B
#DEFINE HB_EI EI $0B
#ELSE
; Z280 MODE 1/2 INTERRUPT HANDLING
#DEFINE HB_DI DI
@ -352,8 +366,7 @@ HBX_INVOKE:
LD A,BID_BIOS ; HBIOS BANK
LD (HB_CURBNK),A ; SET AS CURRENT BANK
;
.DB $ED,$71 ; SC
.DW HB_DISPATCH ; SC PARAMETER
SC HB_DISPATCH
;
PUSH AF
LD A,(HB_INVBNK)
@ -490,8 +503,7 @@ HBX_BNKSEL1:
PUSH BC ; SAVE BC
PUSH HL ; SAVE HL
LD B,$00 ; FIRST USER PDR
.DB $ED,$71 ; SC
.DW Z280_BNKSEL ; SC PARAMETER
SC Z280_BNKSEL ; SYSCALL
POP HL ; RESTORE HL
POP BC ; RESTORE BC
RET ; DONE
@ -560,9 +572,11 @@ HBX_MMA .DB 0 ; TEMPORARY STORAGE FOR REG A
;
HBX_BNKCPY:
#IF (MEMMGR == MM_Z280)
.DB $ED,$71 ; SC
.DW Z280_BNKCPYX ; SC PARAMETER
SC Z280_BNKCPYX ; SYSCALL TO BNKCPYX
RET
;
IOPRVAL .DW 0 ; TEMP STORAGE FOR IOPR
;
#ELSE
#IF (CPUFAM == CPU_Z280)
PUSH HL
@ -651,8 +665,7 @@ HBX_BNKCALL:
#IF (MEMMGR == MM_Z280)
CP BID_BIOS ; CALLING HBIOS?
JR NZ,HBX_BNKCALL3 ; NOPE, DO NORMAL PROCESSING
.DB $ED,$71 ; SC
.DW HBX_BNKCALL2 ; CALL HERE IN SYSTEM MODE
SC HBX_BNKCALL2 ; SYSCALL TO BNKCALL2
RET ; THEN RETURN
;
HBX_BNKCALL2:
@ -1127,7 +1140,7 @@ Z280_BOOTERR .TEXT "\r\n\r\n*** Application mode boot not supported under Z280 n
LD HL,Z280_BOOTPDRTBL ; START OF PDR VALUES TABLE
LD C,Z280_MMUBLKMOV ; PDR BLOCK MOVE PORT
LD B,16 ; PROGRAM 16 PDRS
.DB $ED,$93 ; OTIRW
OTIRW ; OTIRW
;
; INITIALIZE ALL OF THE USER PAGE DESCRIPTORS WITH BLOCK MOVE
LD A,$10 ; FIRST SYSTEM PDR
@ -1135,7 +1148,7 @@ Z280_BOOTERR .TEXT "\r\n\r\n*** Application mode boot not supported under Z280 n
LD HL,Z280_BOOTPDRTBL ; START OF PDR VALUES TABLE
LD C,Z280_MMUBLKMOV ; PDR BLOCK MOVE PORT
LD B,16 ; PROGRAM 16 PDRS
.DB $ED,$93 ; OTIRW
OTIRW ; OTIRW
;
; ENABLE MMU (SYSTEM AND USER TRANSLATION)
LD C,Z280_MMUMCR ; MMU MASTER CONTROL REGISTER
@ -1532,7 +1545,11 @@ MBC_SINGLE:
LD HL,0
LD DE,0
LD BC,$8000
#IF (MEMMGR == MM_Z280)
CALL Z280_BNKCPY
#ELSE
CALL HBX_BNKCPY
#ENDIF
;
; TRANSITION TO HBIOS IN RAM BANK
;
@ -1621,9 +1638,9 @@ HB_START1: ; BNKCALL ARRIVES HERE, BUT NOW RUNNING IN RAM BANK
; ASSUME THAT CB_RAMBANKS IS THE NUMBER OF 32K RAM BANKS THAT HAS BEEN SET EITHER
; AT ASSEMBLY TIME OR BY PROBING THE ACTUAL AVAILABLE MEMORY (NOT IMPLEMENTED YET).
;
LD A,(CB_RAMBANKS) ; CALCULATE START
DEC A ; RAMBANK AFTER
ADD A,($80 + (PLT_RAM_R / 32)) ; RESERVED BANKS
LD A,(CB_RAMBANKS) ; CALCULATE TOP RAMBANK
ADD A,BID_RAM0 ; AS FIRST RAMBANK +
DEC A ; #RAMBANKS - 1
;
LD HL,CB_BIDCOM
LD B,4
@ -1631,12 +1648,12 @@ CB_IDS: LD (HL),A ; POPULATE CB_BIDCOM
INC HL ; POPULATE CB_BIDUSR
DEC A ; POPULATE CB_BIDBIOS
DJNZ CB_IDS ; POPULATE CB_BIDAUX
;
LD A,(CB_BIDUSR)
LD (HB_SRCBNK),A ; POPULATE HB_SRCBNK
LD (HB_DSTBNK),A ; POPULATE HB_DSTBNK
;
LD A,+($80 + (PLT_RAM_R / 32)) ; POPULATE CB_BIDRAMD0 ; START RAMBANK
LD A,BID_RAM0 ; POPULATE CB_BIDRAMD0 ; START RAMBANK
LD (HL),A
INC HL
;
@ -2471,7 +2488,13 @@ HB_CKBNK:
LD BC,1 ; DECREMENT VALUE
XOR A ; ZERO ACCUM
HB_CKBNK1:
#IF (MEMMGR == MM_Z280)
LD D,A ; WORKING VALUE TO D
LDUD A,(HL) ; GRAB NEXT BYTE FROM USER SPACE
ADD A,D ; ADD NEXT BYTE
#ELSE
ADD A,(HL) ; ADD NEXT BYTE
#ENDIF
OR A ; CLEAR CARRY
SBC HL,BC ; DECREMENT
JR NC,HB_CKBNK1 ; LOOP TILL DONE
@ -4782,7 +4805,7 @@ Z280_BADINT:
CALL PRTHEXWORDHL ; DUMP MSR
EX (SP),HL ; MSR TO STK, RECOVER HL
;
.DB $ED,$55 ; RETIL
RETIL ; RETURN FROM INT
;
Z280_SSTEP:
; SAVE HL AND MSR FOR POSSIBLE RETURN VIA RETIL
@ -4876,7 +4899,7 @@ Z280_PRIVINST:
PUSH BC
PUSH DE
;
.DB $ED,$96 ; LDUP A,(HL)
LDUP A,(HL) ; BYTE FROM USER SPACE
;
; HANDLE DI
CP $F3 ; DI?
@ -4904,7 +4927,7 @@ Z280_PRIVINST3:
CALL PC_LBKT
LD B,$10
Z280_PRIVINST4:
.DB $ED,$96 ; LDUP A,(HL)
LDUP A,(HL) ; BYTE FROM USER SPACE
CALL PRTHEXBYTE
INC HL
DJNZ Z280_PRIVINST4
@ -4925,7 +4948,7 @@ Z280_PRIVINSTX:
PUSH HL ; SAVE HL
LD HL,(HB_MSRSAV) ; GET SAVED MSR
EX (SP),HL ; MSR TO STK, RECOVER HL
.DB $ED,$55 ; RETIL
RETIL ; RETURN FROM INT
;
HB_MSRSAV .DW 0 ; SAVED MSR
HB_RCSAV .DW 0 ; SAVED REASON CODE
@ -5230,7 +5253,7 @@ Z280_BNKSEL2:
;
; SET LOW NIBBLE
LD A,$0A ; VALUE FOR LOW NIBBLE
.DB $ED,$6D ; ADD HL,A ; HL=0000 RBBB B000 1010
ADD HL,A ; ADD HL,A ; HL=0000 RBBB B000 1010
;
; POINT TO FIRST PDR TO PROGRAM
LD A,B ; INITIAL PDR TO PROG
@ -5427,7 +5450,7 @@ Z280_BNKCPY:
;
; WAIT FOR XFER TO COMPLETE
Z2DMALOOP:
.DB $ED,$B7 ; INW HL,(C)
INW HL,(C) ; WORD INPUT
BIT 7,H ; CHECK EN BIT OF TDR
JR NZ,Z2DMALOOP ; LOOP WHILE ACTIVE
;
@ -5510,7 +5533,7 @@ Z280_SYSCALL:
POP HL
Z280_SYSCALL_GO:
CALL $FFFF ; PARM SET ABOVE
.DB $ED,$55 ; RETIL
RETIL ; RETURN FROM INT
#ENDIF
;
;==================================================================================================
@ -6288,7 +6311,7 @@ PS_PRTDC:
RET ; DONE
;
PS_PRTDC1:
; PRINT ROM/ROM DISK CAPACITY IN KB
; PRINT ROM/RAM DISK CAPACITY IN KB
LD B,BF_DIOCAP ; HBIOS FUNC: GET CAPACTIY
RST 08 ; DE:HL := BLOCKS
JP NZ,PS_PRTNUL ; MEDIA PROBLEM
@ -6933,8 +6956,6 @@ HB_SECS .FILL 4,0 ; 32 BIT SECONDS COUNTER
HB_CPUTYPE .DB 0 ; 0=Z80, 1=80180, 2=SL1960, 3=ASCI BRG
HB_CPUOSC .DW CPUOSC ; ACTUAL CPU HARDWARE OSC FREQ IN KHZ
;
IOPRVAL .DW 0 ; TEMP STORAGE FOR IOPR
;
HB_BATCOND .DB 0 ; BATTERY CONDITION (0=LOW, 1=OK)
;
RTCDEFVAL .DB RTCDEF ; STORAGE FOR RTC DEFAULT VALUE

34
Source/HBIOS/std.asm
View File

@ -495,17 +495,17 @@ SYSTIM .SET TM_Z280
;
WBW_ROM_R .EQU 128 ; 128K ; RESERVED ROM REQUIRED FOR ROMWBW
WBW_RAM_R .EQU 256 ; 256K ; RESERVED RAM REQUIRED FOR ROMWBW
TOT_ROM_RB .EQU (PLT_ROM_R + WBW_ROM_R)/32 ; TOTAL ROM BANKS RESERVED
TOT_RAM_RB .EQU (PLT_RAM_R + WBW_RAM_R)/32 ; TOTAL RAM BANKS RESERVED
TOT_ROM_RB .EQU (WBW_ROM_R / 32) ; TOTAL ROM BANKS RESERVED
TOT_RAM_RB .EQU (WBW_RAM_R / 32) ; TOTAL RAM BANKS RESERVED
;
#IF (BIOS == BIOS_UNA)
BID_ROM0 .EQU $0000 + (PLT_ROM_R / 32)
BID_RAM0 .EQU $8000 + (PLT_RAM_R / 32)
BID_ROM0 .EQU $0000
BID_RAM0 .EQU $8000
#ENDIF
;
#IF (BIOS == BIOS_WBW)
BID_ROM0 .EQU $00 + (PLT_ROM_R / 32)
BID_RAM0 .EQU $80 + (PLT_RAM_R / 32)
BID_ROM0 .EQU $00
BID_RAM0 .EQU $80
#ENDIF
BID_ROMN .EQU (BID_ROM0 + ((ROMSIZE / 32) - 1))
@ -528,6 +528,28 @@ BID_IMG2 .EQU BID_ROM0 + 3 ; NETWORK BOOT -+ ROM BANKS
BID_ROMD0 .EQU BID_ROM0 + 4 ; FIRST ROM DRIVE BANK | ROM
BID_ROMDN .EQU BID_ROMN ; LAST ROM DRIVE BANK V DRIVE
;
#IF FALSE
.ECHO "BID_AUX: " \ .ECHO BID_AUX \ .ECHO "\n"
.ECHO "BID_BIOS: " \ .ECHO BID_BIOS \ .ECHO "\n"
.ECHO "BID_USR: " \ .ECHO BID_USR \ .ECHO "\n"
.ECHO "BID_COM: " \ .ECHO BID_COM \ .ECHO "\n"
.ECHO "BID_BOOT: " \ .ECHO BID_BOOT \ .ECHO "\n"
.ECHO "BID_IMG0: " \ .ECHO BID_IMG0 \ .ECHO "\n"
.ECHO "BID_IMG1: " \ .ECHO BID_IMG1 \ .ECHO "\n"
.ECHO "BID_IMG2: " \ .ECHO BID_IMG2 \ .ECHO "\n"
.ECHO "BID_ROMD0: " \ .ECHO BID_ROMD0 \ .ECHO "\n"
.ECHO "BID_ROMDN: " \ .ECHO BID_ROMDN \ .ECHO "\n"
.ECHO "BID_RAMD0: " \ .ECHO BID_RAMD0 \ .ECHO "\n"
.ECHO "BID_RAMDN: " \ .ECHO BID_RAMDN \ .ECHO "\n"
.ECHO "BID_ROM0: " \ .ECHO BID_ROM0 \ .ECHO "\n"
.ECHO "BID_ROMN: " \ .ECHO BID_ROMN \ .ECHO "\n"
.ECHO "BID_RAM0: " \ .ECHO BID_RAM0 \ .ECHO "\n"
.ECHO "BID_RAMN: " \ .ECHO BID_RAMN \ .ECHO "\n"
#ENDIF
;
; MEMORY LAYOUT
;
SYS_SIZ .EQU $3000 ; COMBINED SIZE OF SYSTEM AREA (OS + HBIOS PROXY)

2
Source/ver.inc
View File

@ -2,4 +2,4 @@
#DEFINE RMN 1
#DEFINE RUP 1
#DEFINE RTP 0
#DEFINE BIOSVER "3.1.1-pre.156"
#DEFINE BIOSVER "3.1.1-pre.157"

2
Source/ver.lib
View File

@ -3,5 +3,5 @@ rmn equ 1
rup equ 1
rtp equ 0
biosver macro
db "3.1.1-pre.156"
db "3.1.1-pre.157"
endm

10
Tools/tasm32/TASM280.TAB
View File

@ -127,8 +127,8 @@ DEC L 2D 1 NOP 1
DEC SP 3B 1 NOP 1
DI "" F3 1 NOP 1
DJNZ * 10 2 R1 1
EI "" FB 1 NOP 1
EI * 7FED 3 NOP 1 /* Z280 */
EX (SP),HL E3 1 NOP 1
EX (SP),IX E3DD 2 NOP 1
EX (SP),IY E3FD 2 NOP 1
@ -158,6 +158,8 @@ IN L,(C) 68ED 2 NOP 1
IN A,(*) DB 2 NOP 1
INW HL,(C) B7ED 2 NOP 1 /* Z280 */
IN0 A,(*) 38ED 3 NOP 2
IN0 B,(*) 00ED 3 NOP 2
IN0 C,(*) 08ED 3 NOP 2
@ -342,6 +344,8 @@ LD SP,HL F9 1 NOP 1
LD SP,IX F9DD 2 NOP 1
LD SP,IY F9FD 2 NOP 1
LD SP,* 31 3 NOP 1
LDUD A,(HL) 86ED 2 NOP 1 /* Z280 */
LDUP A,(HL) 96ED 2 NOP 1 /* Z280 */
LDCTL (C),HL 6EED 2 NOP 1 /* Z280 */
LDCTL HL,(C) 66ED 2 NOP 1 /* Z280 */
LDCTL USP,HL 8FED 2 NOP 1 /* Z280 */
@ -378,6 +382,7 @@ OTDR "" BBED 2 NOP 1
OTIM "" 83ED 2 NOP 2
OTIMR "" 93ED 2 NOP 2
OTIR "" B3ED 2 NOP 1
OTIRW "" 93ED 2 NOP 1 /* Z280 */
OUT (C),A 79ED 2 NOP 1
OUT (C),B 41ED 2 NOP 1
@ -524,6 +529,9 @@ SBC HL,DE 52ED 2 NOP 1
SBC HL,HL 62ED 2 NOP 1
SBC HL,SP 72ED 2 NOP 1
SBC A,* DE 2 NOP 1
SC * 71ED 4 NOP 1 /* Z280 */
SCF "" 37 1 NOP 1
SET *,(HL) C6CB 2 ZBIT 1

7
Tools/unix/uz80as/z80.c
View File

@ -210,6 +210,13 @@ static const struct matchtab s_matchtab_z80[] = {
{ "MULTU A,a", "FD.ED.F9.d0.", 4, 0 },
{ "OUTW (C),HL", "ED.BF.", 4, 0 },
{ "RETIL", "ED.55.", 4, 0 },
{ "EI a", "ED.7F.d0.", 4, 0 },
{ "SC a", "ED.71.e0", 4, 0 },
{ "OTIRW", "ED.93.", 4, 0 },
{ "LDUD A,(HL)", "ED.86.", 4, 0 },
{ "LDUP A,(HL)", "ED.96.", 4, 0 },
{ "ADD HL,A", "ED.6D.", 4, 0 },
{ "INW HL,(C)", "ED.B7.", 4, 0 },
{ NULL, NULL },
};

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