From ccda402b9b447991c35699bdada5feb2877a6a4d Mon Sep 17 00:00:00 2001
From: Wayne Warthen <wwarthen@gmail.com>
Date: Thu, 18 Mar 2021 10:37:08 -0700
Subject: [PATCH] Add Z180 & Z280 timer config settings

Allows Z180 & Z280 system periodic timer to be enabled/disabled via config.  Enabled by default.
---
 Readme.unix                 | 2 +-
 Source/HBIOS/cfg_dyno.asm   | 1 +
 Source/HBIOS/cfg_master.asm | 2 ++
 Source/HBIOS/cfg_mk4.asm    | 1 +
 Source/HBIOS/cfg_n8.asm     | 1 +
 Source/HBIOS/cfg_rcz180.asm | 1 +
 Source/HBIOS/cfg_rcz280.asm | 1 +
 Source/HBIOS/cfg_scz180.asm | 1 +
 Source/HBIOS/hbios.asm      | 8 ++++++++
 Source/HBIOS/std.asm        | 4 ++++
 Source/ver.inc              | 2 +-
 Source/ver.lib              | 2 +-
 12 files changed, 23 insertions(+), 3 deletions(-)

diff --git a/Readme.unix b/Readme.unix
index 5a7c3b94..0ba3de23 100644
--- a/Readme.unix
+++ b/Readme.unix
@@ -17,7 +17,7 @@ with respect to the .DS directive. it's usually a bad idea to mix
 	      output point.  It works a lot more like M80, SLR* .PHASE
 
 It assumes that you have some standard system tools and libraries 
-installed specifically: gcc, gnu make, libncurses
+installed specifically: gcc, gnu make, libncurses, srecord
 
 To build:
 	cd to the top directory and type "make".
diff --git a/Source/HBIOS/cfg_dyno.asm b/Source/HBIOS/cfg_dyno.asm
index 2ba312e0..a7d8b686 100644
--- a/Source/HBIOS/cfg_dyno.asm
+++ b/Source/HBIOS/cfg_dyno.asm
@@ -43,6 +43,7 @@ Z180_BASE	.EQU	$C0		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
 Z180_CLKDIV	.EQU	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
 Z180_MEMWAIT	.EQU	0		; Z180: MEMORY WAIT STATES (0-3)
 Z180_IOWAIT	.EQU	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
+Z180_TIMER	.EQU	TRUE		; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
 ;
 RTCIO		.EQU	$0C		; RTC LATCH REGISTER ADR
 ;
diff --git a/Source/HBIOS/cfg_master.asm b/Source/HBIOS/cfg_master.asm
index fa902178..e6114923 100644
--- a/Source/HBIOS/cfg_master.asm
+++ b/Source/HBIOS/cfg_master.asm
@@ -42,11 +42,13 @@ Z180_BASE	.EQU	$40		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
 Z180_CLKDIV	.EQU	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
 Z180_MEMWAIT	.EQU	0		; Z180: MEMORY WAIT STATES (0-3)
 Z180_IOWAIT	.EQU	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
+Z180_TIMER	.EQU	FALSE		; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
 ;
 Z280_MEMLOWAIT	.EQU	0		; Z280: LOW 8MB MEMORY WAIT STATES (0-3)
 Z280_MEMHIWAIT	.EQU	0		; Z280: HIGH 8MB MEMORY WAIT STATES (0-3)
 Z280_IOWAIT	.EQU	1		; Z280: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
 Z280_INTWAIT	.EQU	0		; Z280: INT ACK WAIT STATUS (0-3)
+Z280_TIMER	.EQU	FALSE		; Z280: ENABLE INTERNAL Z280 SYSTEM PERIODIC TIMER
 ;
 N8_PPI0		.EQU	$80		; N8: FIRST PARALLEL PORT REGISTERS BASE ADR
 N8_PPI1		.EQU	$84		; N8: SECOND PARALLEL PORT REGISTERS BASE ADR
diff --git a/Source/HBIOS/cfg_mk4.asm b/Source/HBIOS/cfg_mk4.asm
index 4a05026f..5a09e7d4 100644
--- a/Source/HBIOS/cfg_mk4.asm
+++ b/Source/HBIOS/cfg_mk4.asm
@@ -38,6 +38,7 @@ Z180_BASE	.EQU	$40		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
 Z180_CLKDIV	.EQU	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
 Z180_MEMWAIT	.EQU	0		; Z180: MEMORY WAIT STATES (0-3)
 Z180_IOWAIT	.EQU	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
+Z180_TIMER	.EQU	TRUE		; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
 ;
 MK4_IDE		.EQU	$80		; MK4: IDE REGISTERS BASE ADR
 MK4_XAR		.EQU	$88		; MK4: EXTERNAL ADDRESS REGISTER (XAR) ADR
diff --git a/Source/HBIOS/cfg_n8.asm b/Source/HBIOS/cfg_n8.asm
index aaf967a1..acf639ed 100644
--- a/Source/HBIOS/cfg_n8.asm
+++ b/Source/HBIOS/cfg_n8.asm
@@ -38,6 +38,7 @@ Z180_BASE	.EQU	$40		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
 Z180_CLKDIV	.EQU	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
 Z180_MEMWAIT	.EQU	0		; Z180: MEMORY WAIT STATES (0-3)
 Z180_IOWAIT	.EQU	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
+Z180_TIMER	.EQU	TRUE		; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
 ;
 N8_PPI0		.EQU	$80		; N8: FIRST PARALLEL PORT REGISTERS BASE ADR
 N8_PPI1		.EQU	$84		; N8: SECOND PARALLEL PORT REGISTERS BASE ADR
diff --git a/Source/HBIOS/cfg_rcz180.asm b/Source/HBIOS/cfg_rcz180.asm
index 5f9e9648..cc14b521 100644
--- a/Source/HBIOS/cfg_rcz180.asm
+++ b/Source/HBIOS/cfg_rcz180.asm
@@ -43,6 +43,7 @@ Z180_BASE	.EQU	$C0		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
 Z180_CLKDIV	.EQU	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
 Z180_MEMWAIT	.EQU	0		; Z180: MEMORY WAIT STATES (0-3)
 Z180_IOWAIT	.EQU	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
+Z180_TIMER	.EQU	TRUE		; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
 ;
 RTCIO		.EQU	$0C		; RTC LATCH REGISTER ADR
 ;
diff --git a/Source/HBIOS/cfg_rcz280.asm b/Source/HBIOS/cfg_rcz280.asm
index aa70891d..074ab343 100644
--- a/Source/HBIOS/cfg_rcz280.asm
+++ b/Source/HBIOS/cfg_rcz280.asm
@@ -43,6 +43,7 @@ Z280_MEMLOWAIT	.EQU	0		; Z280: LOW 8MB MEMORY WAIT STATES (0-3)
 Z280_MEMHIWAIT	.EQU	0		; Z280: HIGH 8MB MEMORY WAIT STATES (0-3)
 Z280_IOWAIT	.EQU	1		; Z280: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
 Z280_INTWAIT	.EQU	0		; Z280: INT ACK WAIT STATUS (0-3)
+Z280_TIMER	.EQU	TRUE		; Z280: ENABLE INTERNAL Z280 SYSTEM PERIODIC TIMER
 ;
 RTCIO		.EQU	$C0		; RTC LATCH REGISTER ADR
 ;
diff --git a/Source/HBIOS/cfg_scz180.asm b/Source/HBIOS/cfg_scz180.asm
index 653e1c15..ca64ca01 100644
--- a/Source/HBIOS/cfg_scz180.asm
+++ b/Source/HBIOS/cfg_scz180.asm
@@ -38,6 +38,7 @@ Z180_BASE	.EQU	$C0		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
 Z180_CLKDIV	.EQU	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
 Z180_MEMWAIT	.EQU	0		; Z180: MEMORY WAIT STATES (0-3)
 Z180_IOWAIT	.EQU	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
+Z180_TIMER	.EQU	TRUE		; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
 ;
 RTCIO		.EQU	$0C		; RTC LATCH REGISTER ADR
 ;
diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm
index c3e54fcd..717dcce5 100644
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@@ -1605,6 +1605,8 @@ HB_CPU2:
 	; MASK ALL EXTERNAL INTERRUPTS FOR NOW
 	LD	A,$01			; INT0 ENABLED, INT1-2 DISABLED
 	OUT0	(Z180_ITC),A		; WRITE TO INT/TRAP CONTROL REGISTER
+;
+    #IF (Z180_TIMER)
 ;
 	; SETUP Z180 TIMER0 INTERRUPT VECTOR IN IVT
 	LD	HL,HB_TIMINT
@@ -1633,6 +1635,8 @@ HB_CPU2:
 	OUT0	(Z180_RLDR0H),H
 	LD	A,%00010001		; ENABLE TIMER0 INT AND DOWN COUNTING
 	OUT0	(Z180_TCR),A
+;
+    #ENDIF
 ;
   #ENDIF
 ;
@@ -1641,6 +1645,8 @@ HB_CPU2:
 #IF (CPUFAM == CPU_Z280)
 ;
   #IF (MEMMGR == MM_Z280)
+;
+    #IF (Z280_TIMER)
 ;
 Z280_TC	.EQU	CPUOSC / 4 / 50 / 2	; TIME CONSTANT
 ;
@@ -1668,6 +1674,8 @@ Z280_TC	.EQU	CPUOSC / 4 / 50 / 2	; TIME CONSTANT
 	LD	C,Z280_IOPR		; I/O PAGE REGISTER
 	POP	HL			; RESTORE I/O PAGE
 	LDCTL	(C),HL
+;
+    #ENDIF
 ;
   #ENDIF
 ;
diff --git a/Source/HBIOS/std.asm b/Source/HBIOS/std.asm
index 25131225..47f8f986 100644
--- a/Source/HBIOS/std.asm
+++ b/Source/HBIOS/std.asm
@@ -434,13 +434,17 @@ SYSTIM	.SET	TM_SIMH
   #ENDIF
 ;
   #IF ((CPUFAM == CPU_Z180) & (INTMODE == 2))
+    #IF (Z180_TIMER)
 SYSTIM	.SET	TM_Z180
 	.ECHO	" Z180"
+    #ENDIF
   #ENDIF
 ;
   #IF ((CPUFAM == CPU_Z280) & (MEMMGR == MM_Z280))
+    #IF (Z280_TIMER)
 SYSTIM	.SET	TM_Z280
 	.ECHO	" Z280"
+    #ENDIF
   #ENDIF
 ;
   #IF SYSTIM == TM_NONE
diff --git a/Source/ver.inc b/Source/ver.inc
index ea3f72f1..255c6176 100644
--- a/Source/ver.inc
+++ b/Source/ver.inc
@@ -2,4 +2,4 @@
 #DEFINE	RMN	1
 #DEFINE	RUP	1
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"3.1.1-pre.64"
+#DEFINE BIOSVER	"3.1.1-pre.65"
diff --git a/Source/ver.lib b/Source/ver.lib
index da8ade19..5a04fb6a 100644
--- a/Source/ver.lib
+++ b/Source/ver.lib
@@ -3,5 +3,5 @@ rmn	equ	1
 rup	equ	1
 rtp	equ	0
 biosver	macro
-	db	"3.1.1-pre.64"
+	db	"3.1.1-pre.65"
 	endm