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eZ80: updated rp5rtc.asm to support eZ80 16 bit i/o operations

master
Dean Netherton 2 years ago
parent
commit
d834742337
  1. 4
      Source/HBIOS/Config/RCEZ80_std.asm
  2. 2
      Source/HBIOS/cfg_rcez80.asm
  3. 23
      Source/HBIOS/rp5rtc.asm

4
Source/HBIOS/Config/RCEZ80_std.asm

@ -34,7 +34,7 @@ FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS
FPSW_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL SWITCHES
;
DSRTCENABLE .SET FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
RP5RTCENABLE .SET TRUE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
;
UARTENABLE .SET FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
@ -59,7 +59,7 @@ SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER
FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
;
IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .SET SDMODE_PIO ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|USR]

2
Source/HBIOS/cfg_rcez80.asm

@ -218,7 +218,7 @@ FD1TYPE .EQU FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER
;
IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
IDETRACE .EQU 3 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
IDETRACE .EQU 4 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
IDECNT .EQU 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
IDE0MODE .EQU IDEMODE_RC ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
IDE0BASE .EQU $10 ; IDE 0: IO BASE ADDRESS

23
Source/HBIOS/rp5rtc.asm

@ -83,9 +83,11 @@ RP5RTC_INIT:
RP5RTC_INIT1:
; ENSURE DEVICE IS RESET AND NOT IN TEST MODE
LD A, REG_TEST ; SELECT TEST REGISTER
EZ80_IO
OUT (RP5RTC_REG), A
CALL DLY16
XOR A
EZ80_IO
OUT (RP5RTC_DAT), A ; TURN OFF ALL TEST MODE BITS
LD B, MODE_ALRMST
@ -94,8 +96,10 @@ RP5RTC_INIT1:
CALL RP5RTC_ENTIME
LD A, REG_12_24 ; SET TO 24 HOUR CLOCK
EZ80_IO
OUT (RP5RTC_REG), A
LD A, 1
EZ80_IO
OUT (RP5RTC_DAT), A
CALL RP5RTC_RDTIM
@ -179,7 +183,9 @@ RP5RTC_GETBYT:
LD B, MODE_RAM0
CALL RP5RTC_SETMD
LD A, C ; SELECT NVRAM INDEX
EZ80_IO
OUT (RP5RTC_REG), A
EZ80_IO
IN A, (RP5RTC_DAT)
AND $0F ; RETRIEVE UNIT NIBBLE
LD E, A
@ -187,7 +193,9 @@ RP5RTC_GETBYT:
LD B, MODE_RAM1
CALL RP5RTC_SETMD
LD A, C ; SELECT NVRAM INDEX
EZ80_IO
OUT (RP5RTC_REG), A
EZ80_IO
IN A, (RP5RTC_DAT)
AND $0F ; RETRIEVE UNIT NIBBLE
RLCA
@ -218,14 +226,17 @@ RP5RTC_SETBYT:
LD B, MODE_RAM0
CALL RP5RTC_SETMD
LD A, C ; SELECT NVRAM INDEX
EZ80_IO
OUT (RP5RTC_REG), A
LD A, E
AND $0F
EZ80_IO
OUT (RP5RTC_DAT), A
LD B, MODE_RAM1
CALL RP5RTC_SETMD
LD A, C ; SELECT NVRAM INDEX
EZ80_IO
OUT (RP5RTC_REG), A
LD A, E
AND $F0
@ -233,6 +244,7 @@ RP5RTC_SETBYT:
RRCA
RRCA
RRCA
EZ80_IO
OUT (RP5RTC_DAT), A
XOR A ; SIGNAL SUCCESS
@ -374,11 +386,14 @@ RP5RTC_RDTIM:
; MODE IN B (MODE_TIMEST, MODE_ALRMST, MODE_RAM0, MODE_RAM1)
RP5RTC_SETMD:
LD A, REG_MODE ; SELECT MODE REGISTER
EZ80_IO
OUT (RP5RTC_REG), A
EZ80_IO
IN A, (RP5RTC_DAT)
AND MD_TIME | MD_ALRM
OR B
EZ80_IO
OUT (RP5RTC_DAT), A ; ASSIGN MODE
RET
@ -391,14 +406,18 @@ RP5RTC_ENTIME:
; REGISTER IN B
RP5RTC_RDVL:
LD A, B ; SELECT UNIT REGISTER
EZ80_IO
OUT (RP5RTC_REG), A
EZ80_IO
IN A, (RP5RTC_DAT)
AND $0F ; RETRIEVE UNIT NIBBLE
LD L, A
INC B
LD A, B ; SELECT TENS REGISTER
EZ80_IO
OUT (RP5RTC_REG), A
EZ80_IO
IN A, (RP5RTC_DAT)
AND $0F
RLCA
@ -416,13 +435,16 @@ RP5RTC_RDVL:
RP5RTC_WRVL:
LD C, A
LD A, B ; SELECT UNIT REGISTER
EZ80_IO
OUT (RP5RTC_REG), A
LD A, C ; WRITE C (ONLY LOW NIBBLE WILL BE USED)
EZ80_IO
OUT (RP5RTC_DAT), A
INC B
LD A, B ; SELECT TENS REGISTER
EZ80_IO
OUT (RP5RTC_REG), A
LD A, C ; SHIFT TOP NIBBLE TO LOW NIBBLE
@ -430,6 +452,7 @@ RP5RTC_WRVL:
RRCA
RRCA
RRCA
EZ80_IO
OUT (RP5RTC_DAT), A ; WRITE IT
RET

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