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@ -11,7 +11,6 @@ MPGENA .EQU SBC_BASE + $1C ; PAGING ENABLE REGISTER - BIT 0 = 1 (WRITE ONLY) |
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; |
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RTC .EQU SBC_BASE + $10 ; ADDRESS OF RTC LATCH AND INPUT PORT |
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PPIBASE .EQU SBC_BASE + $00 ; PPI 82C55 I/O IS DECODED TO PORT 60-67 |
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SIOBASE .EQU SBC_BASE + $08 ; 16550 UART I/O BASE ADDRESS |
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; |
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Z180_BASE .EQU $C0 ; I/O BASE ADDRESS FOR INTERNAL Z180 REGISTERS |
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#INCLUDE "z180.inc" |
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