From f20addf39d468865b1206d06546a912cc5913b96 Mon Sep 17 00:00:00 2001
From: Wayne Warthen <wwarthen@gmail.com>
Date: Thu, 18 Feb 2021 17:29:08 -0800
Subject: [PATCH] Support ZZ80MB

---
 Source/HBIOS/Config/RCZ280_nat.asm    |   2 +-
 Source/HBIOS/Config/RCZ280_nat_zz.asm |  29 +++
 Source/HBIOS/Makefile                 |   1 +
 Source/HBIOS/cfg_dyno.asm             |   2 +-
 Source/HBIOS/cfg_ezz80.asm            |   2 +-
 Source/HBIOS/cfg_master.asm           |   2 +-
 Source/HBIOS/cfg_mk4.asm              |   2 +-
 Source/HBIOS/cfg_n8.asm               |   2 +-
 Source/HBIOS/cfg_rcz180.asm           |   2 +-
 Source/HBIOS/cfg_rcz280.asm           |   4 +-
 Source/HBIOS/cfg_rcz80.asm            |   2 +-
 Source/HBIOS/cfg_sbc.asm              |   2 +-
 Source/HBIOS/cfg_scz180.asm           |   2 +-
 Source/HBIOS/cfg_zeta.asm             |   2 +-
 Source/HBIOS/cfg_zeta2.asm            |   2 +-
 Source/HBIOS/hbios.asm                | 248 ++++++++++++++++----------
 Source/HBIOS/std.asm                  |   9 +-
 Source/ver.inc                        |   2 +-
 Source/ver.lib                        |   2 +-
 19 files changed, 207 insertions(+), 112 deletions(-)
 create mode 100644 Source/HBIOS/Config/RCZ280_nat_zz.asm

diff --git a/Source/HBIOS/Config/RCZ280_nat.asm b/Source/HBIOS/Config/RCZ280_nat.asm
index bcc119f4..36da6105 100644
--- a/Source/HBIOS/Config/RCZ280_nat.asm
+++ b/Source/HBIOS/Config/RCZ280_nat.asm
@@ -30,7 +30,7 @@ CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
 CPUOSC		.SET	24000000	; CPU OSC FREQ IN MHZ
 ;
-MEMMGR		.SET	MM_Z280		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
+MEMMGR		.SET	MM_Z280RC	; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280RC|Z280ZZ]
 ;
 INTMODE		.SET	3
 ;
diff --git a/Source/HBIOS/Config/RCZ280_nat_zz.asm b/Source/HBIOS/Config/RCZ280_nat_zz.asm
new file mode 100644
index 00000000..d9bb9534
--- /dev/null
+++ b/Source/HBIOS/Config/RCZ280_nat_zz.asm
@@ -0,0 +1,29 @@
+;
+;==================================================================================================
+;   RC2014 Z280 STANDARD CONFIGURATION (NATIVE Z280 MMU W/ LINEAR MEMORY ON ZZ80MB)
+;==================================================================================================
+;
+; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
+; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
+; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
+; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
+; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
+; YOUR FILE IN THE BUILD PROCESS.
+;
+; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
+; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
+; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
+; SETTINGS.
+;
+; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
+; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
+; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
+; DIRECTORIES ABOVE THIS ONE).
+;
+#DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
+;
+#include "Config/RCZ280_nat.asm"
+;
+MEMMGR		.SET	MM_Z280ZZ	; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280RC|Z280ZZ]
diff --git a/Source/HBIOS/Makefile b/Source/HBIOS/Makefile
index d4bc9501..117c4996 100644
--- a/Source/HBIOS/Makefile
+++ b/Source/HBIOS/Makefile
@@ -14,6 +14,7 @@ else
 	OBJECTS += RCZ180_nat.rom RCZ180_nat.com RCZ180_nat.upd
 	OBJECTS += RCZ280_ext.rom RCZ280_ext.com RCZ280_ext.upd
 	OBJECTS += RCZ280_nat.rom RCZ280_nat.com RCZ280_nat.upd
+	OBJECTS += RCZ280_nat_zz.rom RCZ280_nat_zz.com RCZ280_nat_zz.upd
 	OBJECTS += RCZ80_kio.rom RCZ80_kio.com RCZ80_kio.upd
 	OBJECTS += RCZ80_mt.rom RCZ80_mt.com RCZ80_mt.upd
 	OBJECTS += RCZ80_duart.rom RCZ80_duart.com RCZ80_duart.upd
diff --git a/Source/HBIOS/cfg_dyno.asm b/Source/HBIOS/cfg_dyno.asm
index 165735cd..ad5f4b4e 100644
--- a/Source/HBIOS/cfg_dyno.asm
+++ b/Source/HBIOS/cfg_dyno.asm
@@ -28,7 +28,7 @@ INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180]
+MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280RC|Z280ZZ]
 RAMBIAS		.EQU	512		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
diff --git a/Source/HBIOS/cfg_ezz80.asm b/Source/HBIOS/cfg_ezz80.asm
index 59fcc3d9..78cb75a6 100644
--- a/Source/HBIOS/cfg_ezz80.asm
+++ b/Source/HBIOS/cfg_ezz80.asm
@@ -28,7 +28,7 @@ INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_Z2		; MM_[SBC|Z2|N8|Z180|Z280|ZRC]: MEMORY MANAGER
+MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280RC|Z280ZZ]
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
diff --git a/Source/HBIOS/cfg_master.asm b/Source/HBIOS/cfg_master.asm
index 000aae57..2dff0c7c 100644
--- a/Source/HBIOS/cfg_master.asm
+++ b/Source/HBIOS/cfg_master.asm
@@ -25,7 +25,7 @@ INTMODE		.EQU	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_NONE		; MM_[SBC|Z2|N8|Z180|Z280|ZRC]: MEMORY MANAGER
+MEMMGR		.SET	MM_NONE		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280RC|Z280ZZ]
 RAMBIAS		.EQU	0		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 MPCL_RAM	.EQU	$78		; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
 MPCL_ROM	.EQU	$7C		; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
diff --git a/Source/HBIOS/cfg_mk4.asm b/Source/HBIOS/cfg_mk4.asm
index 98e8f43b..0ba2c819 100644
--- a/Source/HBIOS/cfg_mk4.asm
+++ b/Source/HBIOS/cfg_mk4.asm
@@ -28,7 +28,7 @@ INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_Z180		; MM_[SBC|Z2|N8|Z180|Z280|ZRC]: MEMORY MANAGER
+MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280RC|Z280ZZ]
 RAMBIAS		.EQU	512		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 ;
 Z180_BASE	.EQU	$40		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
diff --git a/Source/HBIOS/cfg_n8.asm b/Source/HBIOS/cfg_n8.asm
index cf4df4cb..b608d298 100644
--- a/Source/HBIOS/cfg_n8.asm
+++ b/Source/HBIOS/cfg_n8.asm
@@ -28,7 +28,7 @@ INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_N8		; MM_[SBC|Z2|N8|Z180|Z280|ZRC]: MEMORY MANAGER
+MEMMGR		.EQU	MM_N8		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280RC|Z280ZZ]
 RAMBIAS		.EQU	0		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 ;
 Z180_BASE	.EQU	$40		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
diff --git a/Source/HBIOS/cfg_rcz180.asm b/Source/HBIOS/cfg_rcz180.asm
index 71eb061f..27009182 100644
--- a/Source/HBIOS/cfg_rcz180.asm
+++ b/Source/HBIOS/cfg_rcz180.asm
@@ -28,7 +28,7 @@ INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_Z180		; MM_[SBC|Z2|N8|Z180|Z280|ZRC]: MEMORY MANAGER
+MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280RC|Z280ZZ]
 RAMBIAS		.EQU	512		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
diff --git a/Source/HBIOS/cfg_rcz280.asm b/Source/HBIOS/cfg_rcz280.asm
index 6e37b3e4..24426f23 100644
--- a/Source/HBIOS/cfg_rcz280.asm
+++ b/Source/HBIOS/cfg_rcz280.asm
@@ -13,7 +13,7 @@
 ;
 #DEFINE PLATFORM_NAME "RC2014"
 ;
-PLATFORM	.EQU	PLT_RCZ80	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO]
+PLATFORM	.EQU	PLT_RCZ280	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280]
 CPUFAM		.EQU	CPU_Z280	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -28,7 +28,7 @@ INTMODE		.EQU	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_Z2		; MM_[SBC|Z2|N8|Z180|Z280|ZRC]: MEMORY MANAGER
+MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280RC|Z280ZZ]
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
diff --git a/Source/HBIOS/cfg_rcz80.asm b/Source/HBIOS/cfg_rcz80.asm
index 5a7418d3..3ccce22e 100644
--- a/Source/HBIOS/cfg_rcz80.asm
+++ b/Source/HBIOS/cfg_rcz80.asm
@@ -28,7 +28,7 @@ INTMODE		.EQU	1		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_Z2		; MM_[SBC|Z2|N8|Z180|Z280|ZRC]: MEMORY MANAGER
+MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280RC|Z280ZZ]
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
diff --git a/Source/HBIOS/cfg_sbc.asm b/Source/HBIOS/cfg_sbc.asm
index f521de2b..48b1c3c1 100644
--- a/Source/HBIOS/cfg_sbc.asm
+++ b/Source/HBIOS/cfg_sbc.asm
@@ -28,7 +28,7 @@ INTMODE		.EQU	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_SBC		; MM_[SBC|Z2|N8|Z180|Z280|ZRC]: MEMORY MANAGER
+MEMMGR		.EQU	MM_SBC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280RC|Z280ZZ]
 MPCL_RAM	.EQU	$78		; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
 MPCL_ROM	.EQU	$7C		; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
 ;
diff --git a/Source/HBIOS/cfg_scz180.asm b/Source/HBIOS/cfg_scz180.asm
index c61505cb..96f93de4 100644
--- a/Source/HBIOS/cfg_scz180.asm
+++ b/Source/HBIOS/cfg_scz180.asm
@@ -28,7 +28,7 @@ INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_Z180		; MM_[SBC|Z2|N8|Z180|Z280|ZRC]: MEMORY MANAGER
+MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280RC|Z280ZZ]
 RAMBIAS		.EQU	512		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 ;
 Z180_BASE	.EQU	$C0		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
diff --git a/Source/HBIOS/cfg_zeta.asm b/Source/HBIOS/cfg_zeta.asm
index 3157c38c..77863aff 100644
--- a/Source/HBIOS/cfg_zeta.asm
+++ b/Source/HBIOS/cfg_zeta.asm
@@ -28,7 +28,7 @@ INTMODE		.EQU	0		; INTERRUPT MODE: 0=NONE, 1=MODE 1, 2=MODE 2
 DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_SBC		; MM_[SBC|Z2|N8|Z180|Z280|ZRC]: MEMORY MANAGER
+MEMMGR		.EQU	MM_SBC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280RC|Z280ZZ]
 MPCL_RAM	.EQU	$78		; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
 MPCL_ROM	.EQU	$7C		; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
 ;
diff --git a/Source/HBIOS/cfg_zeta2.asm b/Source/HBIOS/cfg_zeta2.asm
index 62363c33..801aeebb 100644
--- a/Source/HBIOS/cfg_zeta2.asm
+++ b/Source/HBIOS/cfg_zeta2.asm
@@ -28,7 +28,7 @@ INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180]
+MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280RC|Z280ZZ]
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm
index 5c7828f9..102c5a70 100644
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@@ -139,12 +139,12 @@ MODCNT	.SET	MODCNT + 1
 	.ECHO	"*** ERROR: INTMODE 3 REQUIRES Z280 FAMILY CPU!!!\n"
 	!!!	; FORCE AN ASSEMBLY ERROR
   #ENDIF
-  #IF (MEMMGR != MM_Z280)
+  #IF ((MEMMGR != MM_Z280RC) & (MEMMGR != MM_Z280ZZ))
 	.ECHO	"*** ERROR: INTMODE 3 REQUIRES Z280 MEMORY MANAGER!!!\n"
 	!!!	; FORCE AN ASSEMBLY ERROR
   #ENDIF
 #ENDIF
-#IF (MEMMGR == MM_Z280)
+  #IF ((MEMMGR == MM_Z280RC) | (MEMMGR == MM_Z280ZZ))
   #IF (INTMODE != 3)
 	.ECHO	"*** ERROR: Z280 MEMORY MANAGER REQUIRES INTMODE 3!!!\n"
 	!!!	; FORCE AN ASSEMBLY ERROR
@@ -321,7 +321,7 @@ HBX_INVOKE:
 	POP	HL			; RESTORE HL
 #ENDIF
 
-#IF (MEMMGR == MM_Z280)
+#IF ((MEMMGR == MM_Z280RC) | (MEMMGR == MM_Z280ZZ))
 
 	LD	A,(HB_CURBNK)		; GET CURRENT BANK
 	LD	(HB_INVBNK),A		; SAVE INVOCATION BANK
@@ -462,7 +462,7 @@ HBX_BNKSEL1:
 	RET				; DONE
 #ENDIF
 ;
-#IF (MEMMGR == MM_Z280)
+#IF ((MEMMGR == MM_Z280RC) | (MEMMGR == MM_Z280ZZ))
 	PUSH	BC			; SAVE BC
 	PUSH	HL			; SAVE HL
 	LD	B,$00			; FIRST USER PDR
@@ -499,7 +499,7 @@ HBX_ROM:
 ;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
 ;
 HBX_BNKCPY:
-#IF (MEMMGR == MM_Z280)
+#IF ((MEMMGR == MM_Z280RC) | (MEMMGR == MM_Z280ZZ))
 	.DB	$ED,$71			; SC
 	.DW	Z280_BNKCPY		; SC PARAMETER
 	RET
@@ -588,7 +588,7 @@ HBX_BC_ITER:
 ;
 HBX_BNKCALL:
 ;
-#IF (MEMMGR == MM_Z280)
+#IF ((MEMMGR == MM_Z280RC) | (MEMMGR == MM_Z280ZZ))
 	CP	BID_BIOS		; CALLING HBIOS?
 	JR	NZ,HBX_BNKCALL3		; NOPE, DO NORMAL PROCESSING
 	.DB	$ED,$71			; SC
@@ -656,7 +656,7 @@ HBX_POKE:
 ;
 HBX_PPRET:
 	POP	AF
-#IF (MEMMGR == MM_Z280)
+#IF ((MEMMGR == MM_Z280RC) | (MEMMGR == MM_Z280ZZ))
 	LD	A,(HB_INVBNK)		; SPECIAL CASE FOR Z280 MEM MGR
 #ENDIF
 	CALL	HBX_BNKSEL
@@ -753,7 +753,7 @@ INT_IM1:
 ;
 HBX_INT:	; COMMON INTERRUPT ROUTING CODE
 ;
-  #IF (MEMMGR == MM_Z280)
+  #IF ((MEMMGR == MM_Z280RC) | (MEMMGR == MM_Z280ZZ))
 ;
 	EX	(SP),HL			; SAVE HL AND GET INT JP TABLE OFFSET
 	
@@ -964,7 +964,7 @@ HB_IVT0F:	JP	HB_BADINT \ .DB 0
 ;
 HB_START:
 #IFDEF APPBOOT
-  #IF (MEMMGR == MM_Z280)
+  #IF ((MEMMGR == MM_Z280RC) | (MEMMGR == MM_Z280ZZ))
 	LD	A,%00000001
 	OUT	(DIAGPORT),A
 	LD	DE,Z280_BOOTERR
@@ -996,7 +996,7 @@ Z280_BOOTERR	.TEXT	"\r\n\r\n*** Application mode boot not supported under Z280 n
 	LD	HL,$0033		; 3 I/O WAIT STATES ADDED
 	.DB	$ED,$6E			; LDCTL	(C),HL
 
-  #IF (MEMMGR == MM_Z280)
+  #IF ((MEMMGR == MM_Z280RC) | (MEMMGR == MM_Z280ZZ))
   
 	; INITIALIZE MMU
 	; START BY SELECTING I/O PAGE $FF
@@ -1042,10 +1042,10 @@ Z280_BOOTERR	.TEXT	"\r\n\r\n*** Application mode boot not supported under Z280 n
 ;
 	JP	Z280_INITZ		; JUMP TO CODE CONTINUATION
 ;
-#IF (($ % 2) == 1)
+    #IF (($ % 2) == 1)
 	; BYTE ALIGN THE TABLE
 	.DB	0
-#ENDIF
+    #ENDIF
 ;
 Z280_BOOTPDRTBL:
 	; LOWER 32 K (BANKED)
@@ -1058,6 +1058,17 @@ Z280_BOOTPDRTBL:
 	.DW	($006 << 4) | $A
 	.DW	($007 << 4) | $A
 	; UPPER 32 K (COMMON)
+;
+    #IF (MEMMGR == MM_Z280ZZ)
+	.DW	($878 << 4) | $A
+	.DW	($879 << 4) | $A
+	.DW	($87A << 4) | $A
+	.DW	($87B << 4) | $A
+	.DW	($87C << 4) | $A
+	.DW	($87D << 4) | $A
+	.DW	($87E << 4) | $A
+	.DW	($87F << 4) | $A
+    #ELSE
 	.DW	($0F8 << 4) | $A
 	.DW	($0F9 << 4) | $A
 	.DW	($0FA << 4) | $A
@@ -1066,6 +1077,7 @@ Z280_BOOTPDRTBL:
 	.DW	($0FD << 4) | $A
 	.DW	($0FE << 4) | $A
 	.DW	($0FF << 4) | $A
+    #ENDIF
 ;
 Z280_INITZ:
 ;
@@ -1226,10 +1238,12 @@ Z280_INITZ:
 ;
 ; TRANSITION TO HBIOS IN RAM BANK
 ;
-#IF (MEMMGR == MM_Z280)
+#IF ((MEMMGR == MM_Z280RC) | (MEMMGR == MM_Z280ZZ))
 	LD	A,BID_BIOS
 	LD	B,$10			; FIRST SYSTEM PDR
 	CALL	Z280_BNKSEL
+;
+	JR	HB_START1
 #ELSE
 	LD	A,BID_BIOS		; BIOS BANK ID
 	LD	IX,HB_START1		; EXECUTION RESUMES HERE
@@ -1252,10 +1266,14 @@ HB_START1:				; BNKCALL ARRIVES HERE, BUT NOW RUNNING IN RAM BANK
 	LD	A,TRUE			; ACCUM := TRUE
 	LD	(HB_RAMFLAG),A		; SET RAMFLAG
 ;
-#IF (MEMMGR == MM_Z280)
+#IF ((MEMMGR == MM_Z280RC) | (MEMMGR == MM_Z280ZZ))
 	; NOW POINT TO RAM COPY OF Z280 INT/TRAP TABLE
 	LD	C,Z280_VPR
+  #IF (MEMMGR == MM_Z280ZZ)
+	LD	HL,$8680+(Z280_IVT >> 8)	; TOP 16 BITS OF PHYSICAL ADR OF IVT
+  #ELSE
 	LD	HL,$0E80+(Z280_IVT >> 8)	; TOP 16 BITS OF PHYSICAL ADR OF IVT
+  #ENDIF
 	.DB	$ED,$6E			; LDCTL	(C),HL
 #ENDIF
 ;
@@ -1441,7 +1459,7 @@ HB_CPU1:
 	LD	C,(CPUOSC / 2) / 1000000
 	LD	DE,(CPUOSC / 2) / 1000
 ;
-#IF (Z180_CLKDIV >= 1)
+  #IF (Z180_CLKDIV >= 1)
 	LD	A,(HB_CPUTYPE)	; GET CPU TYPE
 	CP	2		; Z8S180 REV K OR BETTER?
 	JR	C,HB_CPU2	; IF NOT, NOT POSSIBLE!
@@ -1451,9 +1469,9 @@ HB_CPU1:
 	; REFLECT SPEED CHANGE
 	LD	C,CPUOSC / 1000000
 	LD	DE,CPUOSC / 1000
-#ENDIF
+  #ENDIF
 
-#IF (Z180_CLKDIV >= 2)
+  #IF (Z180_CLKDIV >= 2)
 	LD	A,(HB_CPUTYPE)	; GET CPU TYPE
 	CP	3		; Z8S180 REV N OR BETTER?
 	JR	C,HB_CPU2	; IF NOT, NOT POSSIBLE!
@@ -1466,7 +1484,7 @@ HB_CPU1:
 	; REFLECT SPEED CHANGE
 	LD	C,(CPUOSC * 2) / 1000000
 	LD	DE,(CPUOSC * 2) / 1000
-#ENDIF
+  #ENDIF
 ;
 HB_CPU2:
 	; SAVE CPU SPEED IN CONFIG BLOCK
@@ -1610,9 +1628,11 @@ Z280_TC	.EQU	CPUOSC / 4 / 50 / 2	; TIME CONSTANT
 	LD	(Z280_IVT+$16),HL	; Z280 T/C VECTOR
 ;
 	; SELECT I/O PAGE $FE
-	LD	L,$FE			; COUNTER/TIMER I/O PAGE
-	LD	C,Z280_IOPR		; REG C POINTS TO I/O PAGE REGISTER
-	.DB	$ED,$6E			; LDCTL	(C),HL
+	LD	C,Z280_IOPR		; I/O PAGE REGISTER
+	.DB	$ED,$66			; LDCTL HL,(C) ; GET CURRENT I/O PAGE
+	PUSH	HL			; SAVE IT
+	LD	L,$FE			; I/O PAGE $FE
+	.DB	$ED,$6E			; LDCTL (C),HL
 ;
 	LD	A,%10100000		; CONFIG: C, RE, IE
 	OUT	(Z280_CT0_CFG),A	; SET C/T 0
@@ -1624,10 +1644,10 @@ Z280_TC	.EQU	CPUOSC / 4 / 50 / 2	; TIME CONSTANT
 	LD	A,%11100000		; CMD: EN, GT
 	OUT	(Z280_CT0_CMDST),A	; SET C/T 0
 ;
-	; RESTORE I/O PAGE TO $00
-	LD	L,$00			; NORMAL I/O REG IS $00
-	LD	C,Z280_IOPR		; REG C POINTS TO I/O PAGE REGISTER
-	.DB	$ED,$6E			; LDCTL	(C),HL
+	; RESTORE I/O PAGE
+	LD	C,Z280_IOPR		; I/O PAGE REGISTER
+	POP	HL			; RESTORE I/O PAGE
+	.DB	$ED,$6E			; LDCTL (C),HL
 ;
   #ENDIF
 ;
@@ -1898,11 +1918,14 @@ HB_Z280BUS1:
 #IF (MEMMGR == MM_Z180)
 	.TEXT	"Z180$"
 #ENDIF
-#IF (MEMMGR == MM_Z280)
-	.TEXT	"Z280$"
-#ENDIF
 #IF (MEMMGR == MM_ZRC)
 	.TEXT	"ZRC$"
+#ENDIF
+#IF (MEMMGR == MM_Z280RC)
+	.TEXT	"Z280RC$"
+#ENDIF
+#IF (MEMMGR == MM_Z280ZZ)
+	.TEXT	"Z280ZZ$"
 #ENDIF
 	CALL	PRTSTRD
 	.TEXT	" MMU$"
@@ -2057,7 +2080,7 @@ INITSYS3:
 ;
 INITSYS4:
 ;
-#IF (MEMMGR == MM_Z280)
+#IF ((MEMMGR == MM_Z280RC) | (MEMMGR == MM_Z280ZZ))
 	; LEAVE SYSTEM MODE STACK POINTING TO AN OK PLACE
 	LD	SP,HB_STACK		; NOW USE REAL SYSTEM STACK LOC
 	
@@ -2324,7 +2347,7 @@ IDLE:
 ;
 HB_DISPATCH:
 ;
-#IF (MEMMGR == MM_Z280)
+#IF ((MEMMGR == MM_Z280RC) | (MEMMGR == MM_Z280ZZ))
 	; FOR Z280 MEMMGR, WE DISPATCH VIA THE Z280 SYSCALL.
 	; THE SYSCALL MECHANISM WILL CLEAR INTERRUPTS.  IN
 	; GENERAL, INTERRUPTS ARE OK DURING API PROCESSING,
@@ -2907,7 +2930,7 @@ SYS_RESINT:
 SYS_RESWARM:
 	CALL	SYS_RESINT
 ;	
-#IF (MEMMGR == MM_Z280)
+#IF ((MEMMGR == MM_Z280RC) | (MEMMGR == MM_Z280ZZ))
 	JP	INITSYS4
 #ELSE
 	; PERFORM BANK CALL TO OS IMAGES BANK IN ROM
@@ -2946,7 +2969,7 @@ SYS_VER:
 ;   CALLER MUST ESTABLISH UPPER MEMORY STACK BEFORE INVOKING THIS FUNCTION!
 ;
 SYS_SETBNK:
-#IF (MEMMGR == MM_Z280)
+#IF ((MEMMGR == MM_Z280RC) | (MEMMGR == MM_Z280ZZ))
 	; FOR Z280 MEMMGR, WE ARE IN SYSTEM MODE HERE, SO WE CAN UPDATE
 	; THE USER MODE BANK WITHOUT IMPACTING THE RUNNING CODE.  IT
 	; TAKE EFFECT UPON RETURN TO USER MODE.
@@ -3549,7 +3572,7 @@ HB_IM1PTR	.DW	HB_IVT		; POINTER FOR NEXT IM1 ENTRY
 ;
 ;
 ;
-#IF (MEMMGR == MM_Z280)
+#IF ((MEMMGR == MM_Z280RC) | (MEMMGR == MM_Z280ZZ))
 
 Z280_TIMINT:
 	; DISCARD REASON CODE
@@ -3676,7 +3699,7 @@ HB_BADINTCNT	.DB	0
 ;
 ; Z280 BAD INT HANDLER
 ;
-#IF (MEMMGR == MM_Z280)
+#IF ((MEMMGR == MM_Z280RC) | (MEMMGR == MM_Z280ZZ))
 ;
 Z280_BADINT:
 	; SAVE REASON CODE FOR POSSIBLE RETURN VIA RETIL
@@ -3787,7 +3810,7 @@ Z280_ACCVIOSTR	.TEXT	"ACCESS VIOLATION $"
 ;
 ; Z280 PRIVILEGED INSTRUCTION HANDLER
 ;
-#IF (MEMMGR == MM_Z280)
+#IF ((MEMMGR == MM_Z280RC) | (MEMMGR == MM_Z280ZZ))
 ;
 Z280_PRIVINST:
 	; SAVE HL AND MSR FOR POSSIBLE RETURN VIA RETIL
@@ -4035,7 +4058,7 @@ HB_TMPREF	.DW	0
 ;   Z280 INTERRUPT VECTOR TABLE
 ;==================================================================================================
 ;
-#IF (MEMMGR == MM_Z280)
+#IF ((MEMMGR == MM_Z280RC) | (MEMMGR == MM_Z280ZZ))
 ;
 	; THE Z280 IVT MUST BE ON A 4K BOUNDARY.  IT HAS BEEN LOCATED
 	; HERE IN AN EFFORT TO MINIMIZE WASTED SPACE.  THERE SHOULD BE
@@ -4125,7 +4148,7 @@ Z280_IVT:
 ; SPEED OF THE BANK SWITCH.  BY USING THE TABLE, IT IS POSSIBLE
 ; EXECUTE THE CORE OF THE BANKSWITCH WITH A SINGLE OTIRW.
 ;
-#IF (MEMMGR == MM_Z280) & FALSE
+#IF ((MEMMGR == MM_Z280RC) | (MEMMGR == MM_Z280ZZ)) & FALSE
 ;
 ; REG A HAS BANK ID, REG B HAS INITIAL PDR TO PROGRAM
 ; REGISTERS AF, BC, HL DESTROYED
@@ -4474,36 +4497,55 @@ Z280_PDRTBL:
 ; THIS VERSION IS SLOWER, BUT AVOIDS THE USE OF THE 512+
 ; BYTE TABLE.
 ;
-#IF (MEMMGR == MM_Z280)
+#IF ((MEMMGR == MM_Z280RC) | (MEMMGR == MM_Z280ZZ))
 ;
 ; REG A HAS BANK ID, REG B HAS INITIAL PDR TO PROGRAM
 ; REGISTERS AF, BC, HL DESTROYED
 ;
 Z280_BNKSEL:
-	; SELECT I/O PAGE FOR MMU
-	LD	L,$FF			; MMU AT I/O PAGE $FF
-	LD	C,Z280_IOPR		; I/O PAGE REGISTER TO C
-	.DB	$ED,$6E			; LDCTL (C),HL
+	; SELECT I/O PAGE $FE (SAVING PREVIOUS VALUE)
+	LD	C,Z280_IOPR		; REG C POINTS TO I/O PAGE REGISTER
+	.DB	$ED,$66			; LDCTL HL,(C) ; GET CURRENT I/O PAGE
+	PUSH	HL			; SAVE IT
+	LD	L,$FF			; NEW I/O PAGE
+	.DB	$ED,$6E			; LDCTL	(C),HL
+;
+  #IF (MEMMGR == MM_Z280ZZ)
+;
+	; CONVERT BANK ID TO TOP 12 BITS OF PHYSICAL ADDRESS
+	; WITH $0A IN THE LOW ORDER NIBBLE:
+	; BANK ID: R000 BBBB
+	; PDR: R000 0BBB B000 1010	
+;
+	;MULTU	A,$80			; HL=0R00 0BBB B000 0000
+	.DB	$FD,$ED,$F9,$80		; MULTU A,$80
+	BIT	6,H			; RAM BIT SET?
+	JR	Z,Z280_BNKSEL2		; IF NOT, ALL DONE
+	RES	6,H			; OTHERWISE, MOVE RAM BIT
+	SET	7,H			; HL=R000 0BBB B000 0000
+;
+  #ELSE
 ;
 	; CONVERT BANK ID TO TOP 12 BITS OF PHYSICAL ADDRESS
 	; WITH $0A IN THE LOW ORDER NIBBLE:
 	; BANK ID: R000 BBBB
 	; PDR: 0000 RBBB B000 1010
-;	
-	; IF R BIT (RAM/ROM) IS SET, WE WANT TO CONVERT
-	; FROM R000 BBBB -> 000R BBBB
-	RLCA				; A=R 000B BBBR
-	JP	NC,Z280_BNKSEL1
-	XOR	%00100001		; A=00RB BBB0
 ;
-Z280_BNKSEL1:
-	;MULTU	A,$40			; HL=0000 RBBB B000 0000
-	.DB	$FD,$ED,$F9,$40		; MULTU A,$40
+	;MULTU	A,$80			; HL=0R00 0BBB B000 0000
+	.DB	$FD,$ED,$F9,$80		; MULTU A,$80
+	BIT	6,H			; RAM BIT SET?
+	JR	Z,Z280_BNKSEL2		; IF NOT, ALL DONE
+	RES	6,H			; OTHERWISE, MOVE RAM BIT
+	SET	3,H			; HL=0000 RBBB B000 0000
+;
+  #ENDIF
 ;	
+Z280_BNKSEL2:
+;
+	; SET LOW NIBBLE
 	LD	A,$0A			; VALUE FOR LOW NIBBLE
 	.DB	$ED,$6D			; ADD HL,A ; HL=0000 RBBB B000 1010
-;	
-Z280_BNKSEL2:
+;
 	; POINT TO FIRST PDR TO PROGRAM
 	LD	A,B			; INITIAL PDR TO PROG
 	OUT	(Z280_MMUPDRPTR),A	; SET THE PDR POINTER
@@ -4532,18 +4574,18 @@ Z280_BNKSEL3:
 	.DB	$ED,$BF			; OUTW (C),HL
 	.DB	$ED,$6D			; ADD HL, A ; BUMP VALUE
 	;DJNZ	Z280_BNKSEL3		; DO ALL PDRS
-;	
-	; RESTORE I/O PAGE TO $00
-	LD	L,$00			; NORMAL I/O PAGE $00
-	LD	C,Z280_IOPR		; I/O PAGE REGISTER TO C
-	.DB	$ED,$6E			; LDCTL (C),HL
+;
+	; RESTORE I/O PAGE
+	LD	C,Z280_IOPR		; REG C POINTS TO I/O PAGE REGISTER
+	POP	HL			; RECOVER ORIGINAL I/O PAGE
+	.DB	$ED,$6E			; LDCTL	(C),HL
 ;
 	RET
 #ENDIF
 ;
 ; Z280 BANK COPY (CALLED FROM PROXY)
 ;
-#IF (MEMMGR == MM_Z280)
+#IF ((MEMMGR == MM_Z280RC) | (MEMMGR == MM_Z280ZZ))
 ;
 Z280_BNKCPY:
 	; Z280 MEMORY TO MEMORY DMA
@@ -4555,46 +4597,49 @@ Z280_BNKCPY:
 	; - FLOWTHROUGH OPERATION
 	; - SINGLE TRANSACTION (CAN WE USE CONTINUOUS???)
 	; - 1 BYTE XFER SIZE
-
+;
+	; SAVE INCOMING REGISTERS
 	PUSH	HL
 	PUSH	DE
 	PUSH	BC
-
+;
 	PUSH	BC			; SAVE COUNT
 	PUSH	HL			; SAVE SOURCE ADDRESS
-	
+;	
 	; SELECT I/O PAGE $FF
-	LD	L,$FF			; I/O PAGE $FF
 	LD	C,Z280_IOPR		; I/O PAGE REGISTER
+	.DB	$ED,$66			; LDCTL HL,(C) ; GET CURRENT I/O PAGE
+	LD	(IOPRVAL),HL		; SAVE IT
+	LD	L,$FF			; I/O PAGE $FF
 	.DB	$ED,$6E			; LDCTL (C),HL
-	
+;	
 	LD	C,Z280_DMA0_DSTL	; START WITH DEST REG LO
-
+;
 	LD	A,(HB_DSTBNK)		; DEST BANK TO ACCUM
 	CALL	Z2DMAADR		; SETUP DEST ADR REGS
-	
+;	
 	POP	DE			; SRC ADR TO DE
 	LD	A,(HB_SRCBNK)		; DEST BANK TO ACCUM
 	CALL	Z2DMAADR		; SETUP SOURCE ADR REGS
-
+;
 	POP	HL			; COUNT TO HL
 	.DB	$ED,$BF			; OUTW (C),HL
 	INC	C			; BUMP TO TDR
-
+;
 	LD	HL,$8000		; ENABLE DMA0 TO RUN!
 	.DB	$ED,$BF			; OUTW (C),HL
-
+;
 	; WAIT FOR XFER TO COMPLETE
 Z2DMALOOP:
 	.DB	$ED,$B7			; INW HL,(C)
 	BIT	7,H			; CHECK EN BIT OF TDR
 	JR	NZ,Z2DMALOOP		; LOOP WHILE ACTIVE
-
-	; RETURN TO I/O PAGE $00
-	LD	L,$00                   ; RESTORE I/O PAGE REG TO 0
+;
+	; RESTORE I/O PAGE
 	LD	C,Z280_IOPR		; I/O PAGE REGISTER
+	LD	HL,(IOPRVAL)		; RESTORE I/O PAGE
 	.DB	$ED,$6E			; LDCTL (C),HL
-
+;
 	; SETUP RETURN VALUES
 	POP	BC			; RECOVER ORIGINAL BC
 	POP	DE			; RECOVER ORIGINAL DE
@@ -4604,38 +4649,55 @@ Z2DMALOOP:
 	ADD	HL,BC			; INCREMENT DST ADR BY COUNT
 	EX	DE,HL			; SWAP BACK
 	LD	BC,0			; COUNT IS NOW ZERO
-
+;
 	RET
-
+;
 Z2DMAADR:
 	; SET ADDRESS REGISTERS, BANK IN A, ADDRESS IN DE
 	; C POINTS TO FIRST DMA ADR PORT TO SET
+	; A=R000 BBBB, DE=0AAA AAAA AAAA AAAA
+	; RC: DMA HI=0000 RBBB BAAA 1111 LO=1111 AAAA AAAA AAAA
+	; ZZ: DMA HI=R000 0BBB BAAA 1111 LO=1111 AAAA AAAA AAAA
 	BIT	7,D			; HIGH RAM?
-	JR	Z,Z2DMAADR0		; NO, SKIP
-	LD	A,$8F			; SUBSTITUTE COMMON RAM BANK ID
-
-Z2DMAADR0:
-	BIT	7,A			; RAM?
 	JR	Z,Z2DMAADR1		; NO, SKIP
-	RES	7,A			; CLEAR RAM BIT
-	SET	4,A			; SET BIT FOR 512K OFFSET
-
+	LD	A,$8F			; SUBSTITUTE COMMON RAM BANK ID
+;
 Z2DMAADR1:
 	; ADR HI FROM A:DE
-	LD	L,D			; L=XAAA AAAA
-	LD	H,A			; H=BBBB BBBB
-	SLA	L			; L=AAAA AAA0
-	SRL	H			; H=0BBB BBBB B
-	RR	L			; L=BAAA AAAA
+	LD	L,D			; L=?AAA AAAA
+	LD	H,A			; H=R000 BBBB
+	SLA	L			; L=AAAA AAA0 ?
+	SRL	H			; H=0R00 0BBB B
+	RR	L			; L=BAAA AAAA 0
 	LD	A,$0F			; A=0000 1111
 	OR	L			; A=BAAA 1111
 	LD	L,A			; L=BAAA 1111
+	
+  #IF (MEMMGR == MM_Z280ZZ)
+	; IF ZZ80MB, THEN THE RAM/ROM SELECT BIT IS THE
+	; HIGH BIT.  MOVE THE RAM/ROM BIT.
+	; DMA HI=0000 RBBB BAAA 1111 LO=1111 AAAA AAAA AAAA
+	BIT	6,H
+	JR	Z,Z2DMAADR2
+	RES	6,H
+	SET	7,H
+  #ELSE
+	; IF NOT ZZ80MB, THEN THE RAM/ROM SELECT BIT IS BIT 3 OF
+	; HI WORD OF THE HI DMA ADDRESS.  MOVE THE RAM/ROM BIT.
+	; DMA HI=R000 0BBB BAAA 1111 LO=1111 AAAA AAAA AAAA
+	BIT	6,H
+	JR	Z,Z2DMAADR2
+	RES	6,H
+	SET	3,H
+  #ENDIF
+	
+Z2DMAADR2:
 	PUSH	HL			; SAVE IT FOR NOW
 
 	; ADR LO FROM DE:
-	LD	L,E			; L= AAAA AAAA
-	LD	A,$F0			; A= 1111 0000
-	OR	D			; A= 1111 AAAA
+	LD	L,E			; L=AAAA AAAA
+	LD	A,$F0			; A=1111 0000
+	OR	D			; A=1111 AAAA
 	LD	H,A			; HL=1111 AAAA AAAA AAAA
 
 	; SET ADR LO REG
@@ -4644,7 +4706,6 @@ Z2DMAADR1:
 
 	; SET ADR HI REG
 	POP	HL			; RECOVER THE HI VAL
-
 	.DB	$ED,$BF			; OUTW (C),HL
 	INC	C			; BUMP TO NEXT REG
 	
@@ -4655,7 +4716,7 @@ Z2DMAADR1:
 ; ADDRESS AND CALLS IT.  ALLOWS ANY USER MODE CODE TO CALL INTO AN
 ; ARBITRARY LOCATION OF SYSTEM MODE CODE.
 ;
-#IF (MEMMGR == MM_Z280)
+#IF ((MEMMGR == MM_Z280RC) | (MEMMGR == MM_Z280ZZ))
 Z280_SYSCALL:
 	EX	(SP),HL
 	LD	(Z280_SYSCALL_GO+1),HL
@@ -6018,6 +6079,7 @@ HB_SECS		.FILL	4,0		; 32 BIT SECONDS COUNTER
 HB_CPUTYPE	.DB	0		; 0=Z80, 1=80180, 2=SL1960, 3=ASCI BRG
 ;
 RTCVAL		.DB	RTCDEF		; SHADOW VALUE FOR RTC LATCH PORT
+IOPRVAL		.DW	0		; TEMP STORAGE FOR IOPR
 ;
 HB_BATCOND	.DB	0		; BATTERY CONDITION (0=LOW, 1=OK)
 ;
diff --git a/Source/HBIOS/std.asm b/Source/HBIOS/std.asm
index 9c625aad..1fdeb7e9 100644
--- a/Source/HBIOS/std.asm
+++ b/Source/HBIOS/std.asm
@@ -13,6 +13,7 @@
 ; 9.  EZZ80	Easy Z80, Z80 SBC w/ RC2014 bus and CTC
 ; 10. SCZ180	Steve Cousins Z180 based system
 ; 11. DYNO	Steve Garcia's Dyno Micro-ATX Motherboard
+; 12. RCZ280	Z280 CPU on RC2014 or ZZ80MB
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;
@@ -48,11 +49,12 @@ PLT_ZETA2	.EQU	3		; ZETA Z80 V2 SBC
 PLT_N8		.EQU	4		; N8 (HOME COMPUTER) Z180 SBC
 PLT_MK4		.EQU	5		; MARK IV
 PLT_UNA		.EQU	6		; UNA BIOS
-PLT_RCZ80	.EQU	7		; RC2014 W Z80
+PLT_RCZ80	.EQU	7		; RC2014 W/ Z80
 PLT_RCZ180	.EQU	8		; RC2014 W/ Z180
 PLT_EZZ80	.EQU	9		; EASY Z80
 PLT_SCZ180	.EQU	10		; SCZ180
 PLT_DYNO	.EQU	11		; DYNO MICRO-ATX MOTHERBOARD
+PLT_RCZ280	.EQU	12		; RC2014 W/ Z280
 ;
 ;
 ; CPU TYPES
@@ -80,8 +82,9 @@ MM_SBC		.EQU	1		; ORIGINAL N8VEM/RBC Z80 SBC BANKED MEMORY
 MM_Z2		.EQU	2		; 16K X 4 BANKED MEMORY INTRODUCED ON ZETA2
 MM_N8		.EQU	3		; Z180 CUSTOMIZED FOR N8 MEMORY EXTENSIONS
 MM_Z180		.EQU	4		; Z180 NATIVE MEMORY MANAGER
-MM_Z280		.EQU	5		; Z280 NATIVE MEMORY MANAGER
-MM_ZRC		.EQU	6		; ZRC BANK SWITCHING
+MM_Z280RC	.EQU	5		; Z280 NATIVE MEMORY MANAGER (RC STYLE)
+MM_Z280ZZ	.EQU	6		; Z280 NATIVE MEMORY MANAGER (ZZ80MB STYLE)
+MM_ZRC		.EQU	7		; ZRC BANK SWITCHING
 ;
 ; BOOT STYLE
 ;
diff --git a/Source/ver.inc b/Source/ver.inc
index cd26a4ba..8d8598cb 100644
--- a/Source/ver.inc
+++ b/Source/ver.inc
@@ -2,4 +2,4 @@
 #DEFINE	RMN	1
 #DEFINE	RUP	1
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"3.1.1-pre.46"
+#DEFINE BIOSVER	"3.1.1-pre.47"
diff --git a/Source/ver.lib b/Source/ver.lib
index 0d0daaa7..8c392042 100644
--- a/Source/ver.lib
+++ b/Source/ver.lib
@@ -3,5 +3,5 @@ rmn	equ	1
 rup	equ	1
 rtp	equ	0
 biosver	macro
-	db	"3.1.1-pre.46"
+	db	"3.1.1-pre.47"
 	endm