diff --git a/Source/HBIOS/Config/RCEZ80_std.asm b/Source/HBIOS/Config/RCEZ80_std.asm
index 93129cff..ecebca31 100644
--- a/Source/HBIOS/Config/RCEZ80_std.asm
+++ b/Source/HBIOS/Config/RCEZ80_std.asm
@@ -46,7 +46,7 @@
 ;
 #INCLUDE "cfg_RCEZ80.asm"
 ;
-CPUOSC		.SET	18432000	; CPU OSC FREQ IN MHZ
+CPUOSC		.SET	20000000	; CPU OSC FREQ IN MHZ
 ;
 FPLED_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL LEDS
 FPSW_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL SWITCHES
diff --git a/Source/HBIOS/cfg_RCEZ80.asm b/Source/HBIOS/cfg_RCEZ80.asm
index 21d4d82f..e91baa50 100644
--- a/Source/HBIOS/cfg_RCEZ80.asm
+++ b/Source/HBIOS/cfg_RCEZ80.asm
@@ -60,7 +60,7 @@ AUTOCON		.SET	TRUE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
 ;
 CPUSPDCAP	.SET	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.SET	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
-CPUOSC		.SET	18432000	; CPU OSC FREQ IN MHZ
+CPUOSC		.SET	20000000	; CPU OSC FREQ IN MHZ
 INTMODE		.SET	1		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
 DEFSERCFG	.SET	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
@@ -379,11 +379,11 @@ UFENABLE	.SET	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
 ;
 SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
 AUDIOTRACE	.SET	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
-SN7CLK		.SET	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
+SN7CLK		.SET	CPUOSC/4	; SN: PSG CLOCK FREQ, ASSUME MSX STD
 SNMODE		.SET	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO]
 ;
 AY38910ENABLE	.SET	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
-AY_CLK		.SET	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
+AY_CLK		.SET	CPUOSC/4	; AY: PSG CLOCK FREQ, ASSUME MSX STD
 AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
 ;
 SPKENABLE	.SET	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
@@ -414,9 +414,12 @@ EZ80_MEM_MIN_WS	.SET	0		; MINIMUM WAIT STATES TO APPLY, IF EZ80_WSMD_TYP = EZ80W
 ;
 ; BUS TIMING FOR EXTERNAL I/O ACCESS (CS2)
 EZ80_IO_CYCLES	.SET	4		; IO BUS CYCLES (1-15) TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_CYCLES
-EZ80_IO_WS	.SET	5		; IO WAIT STATES (0-7) TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_WAIT
-EZ80_IO_MIN_NS	.SET	320		; CALCULATE AT BOOT TIME THE REQUIRED W/S OR B/C, IF EZ80_WSMD_TYP = EZ80WSMD_CALC
-EZ80_IO_MIN_WS	.SET	6		; MINIMUM WAIT STATES TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_CALC
+EZ80_IO_WS	.SET	7		; IO WAIT STATES (0-7) TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_WAIT
+EZ80_IO_MIN_NS	.SET	250		; CALCULATE AT BOOT TIME THE REQUIRED W/S OR B/C, IF EZ80_WSMD_TYP = EZ80WSMD_CALC
+
+; THE MINMUM W/S SHOULD BE AT LEAST 1 GREATER THAN THE HOLD TRIGGER COUNT PROGRAMMED WITHIN THE PLD OF THE
+; EZ80 INTERFACE MODULE.  SEE THE EZ80-CPU.PLD FILE WITHIN THE EZ80 FIRMWARE CODE BASE
+EZ80_IO_MIN_WS	.SET	7		; MINIMUM WAIT STATES TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_CALC
 ;
 ; APPLY CYCLES, W/S OR CALCULATE CYCLES BASED ON DESIRED PERIOD
 EZ80_WSMD_TYP	.SET	EZ80WSMD_CALC	; BUS WAIT STATE CONFIG: EZ80WSMD_[CALC|CYCLES|WAIT]
diff --git a/Source/HBIOS/ez80cpudrv.asm b/Source/HBIOS/ez80cpudrv.asm
index b972e272..b82274af 100644
--- a/Source/HBIOS/ez80cpudrv.asm
+++ b/Source/HBIOS/ez80cpudrv.asm
@@ -12,9 +12,11 @@
 ; to communicate with the firmware to perform a number of initialisation tasks.
 ; See also the associated ez80 platform drivers (ez80rtc, ez80systmr, ez80uart).
 ;
-; The driver 'exports' two key functions:
+; The driver 'exports' the following:
 ; 1. EZ80_PREINIT - This function is called by the HBIOS boot code to initialise the eZ80 firmware.
 ; 2. EZ80_RPT_TIMINGS - This function is called by the HBIOS boot code to report the platform timings.
+; 3. DELAY - pause for approx 17us
+; 4. VDELAY - pause for approx 17us * DE
 ;
 ; EZ80_PREINIT performs the following:
 ; 1. Exchange platform version numbers
@@ -77,14 +79,12 @@ EZ80_PREINIT:
 
 
 #IF (EZ80_WSMD_TYP == EZ80WSMD_CYCLES)
-	LD	L, EZ80_MEM_CYCLES
-	OR	$80
+	LD	L, EZ80_MEM_CYCLES | $80
 	EZ80_UTIL_MEMTM_SET()
 	LD	A, L
 	LD	(EZ80_PLT_MEMWS), A
 
-	LD	L, EZ80_IO_CYCLES
-	OR	$80
+	LD	L, EZ80_IO_CYCLES | $80
 	EZ80_UTIL_IOTM_SET()
 	LD	A, L
 	LD	(EZ80_PLT_IOWS), A
@@ -126,7 +126,10 @@ EZ80_PREINIT:
 	EZ80_TMR_SET_FREQTICK
 
 	RET
-
+;
+; --------------------------------
+; eZ80 CPU DRIVER REPORT TIMINGS
+; --------------------------------
 EZ80_RPT_TIMINGS:
 	LD	A, (EZ80_PLT_MEMWS)
 	BIT	7, A
@@ -163,7 +166,79 @@ EZ80_RPT_FSH_TIMINGS:
 	LD	A, (EZ80_PLT_FLSHWS)
 	CALL	PRTDECB
 	CALL	PRTSTRD
-	.TEXT	" FSH W/S$"
+	.TEXT	" FSH W/S$";
+
+;--------------------------------------------------------------------------------------------------
+; DELAY LOOP TEST CALIBRATION
+;--------------------------------------------------------------------------------------------------
+;
+; IF ENABLED, THE GPIO PCBx PINS OF THE EZ80 WILL BE TOGGLED AT 'DELAY' RATE * 16 
+; CAN BE USED TO VERIFY DELAY WORKS SUFFICIENT FOR DIFFERENT EZ80 CLOCK SPEEDS
+; AND BUS CYCLES
+;
+#IF FALSE
+
+;   7.3728 MHZ -- 1 MEM W/S, 6 I/O W/S, 0 FSH W/S - 428 - 26.7us
+;  18.4320 MHZ -- 2 MEM W/S, 6 I/O W/S, 1 FSH W/S - 284 - 17.8us
+;  20.0000 MHZ -- 2 MEM W/S, 6 I/O W/S, 1 FSH W/S - 281 - 17.6us
+;  25.0000 MHZ -- 2 MEM W/S, 3 I/O B/C, 1 FSH W/S - 271 - 16.9us
+;  32.0000 MHZ -- 3 MEM W/S, 4 I/O B/C, 2 FSH W/S - 289 - 18.0us
+
+
+PC_DR:		.equ	$009E
+PC_DDR:		.equ	$009F
+	DI
+
+	; ENABLE PC5 GPIO AS OUTPUT
+	LD	BC, PC_DDR
+	XOR	A
+	OUT	(C), A
+	PUSH	AF
+
+	LD	BC, PC_DR
+LOOP:
+
+	POP	AF
+	OUT	(C), A
+	CPL
+	PUSH	AF
+
+	CALL	DELAY
+	CALL	DELAY
+	CALL	DELAY
+	CALL	DELAY
+
+	CALL	DELAY
+	CALL	DELAY
+	CALL	DELAY
+	CALL	DELAY
+
+	CALL	DELAY
+	CALL	DELAY
+	CALL	DELAY
+	CALL	DELAY
+
+	CALL	DELAY
+	CALL	DELAY
+	CALL	DELAY
+	CALL	DELAY
+
+	JR	LOOP
+#ENDIF
+	RET
+
+DELAY:
+	EZ80_DELAY
+	EZ80_DELAY
+	EZ80_DELAY
+	RET
+
+VDELAY:
+	EZ80_DELAY
+	DEC	DE
+	LD	A,D
+	OR	E
+	JR	NZ, VDELAY
 	RET
 
 EZ80_RPT_FIRMWARE:
diff --git a/Source/HBIOS/ez80instr.inc b/Source/HBIOS/ez80instr.inc
index d2ed3154..5da3db4d 100644
--- a/Source/HBIOS/ez80instr.inc
+++ b/Source/HBIOS/ez80instr.inc
@@ -11,8 +11,11 @@
   #DEFINE EZ80_IO	.DB 	$49, $CF
   ; RST.L $10
   #DEFINE EZ80_FN 	.DB	$49, $D7
+  ; RST.L $18
+  #DEFINE EZ80_DELAY	.DB	$49, $DF
 
   #DEFINE EZ80_UTIL_VER_EXCH		XOR A \ LD B, 0 \ EZ80_FN
+  #DEFINE EZ80_UTIL_DELAY 		XOR A \ LD B, 1 \ EZ80_FN
   #DEFINE EZ80_UTIL_SET_BUSTM 		XOR A \ LD B, 3 \ EZ80_FN
   #DEFINE EZ80_UTIL_SET_BUSFQ 		XOR A \ LD B, 4 \ EZ80_FN
   #DEFINE EZ80_UTIL_GET_CPU_FQ 		XOR A \ LD B, 5 \ EZ80_FN
diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm
index 425ed608..56168157 100644
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@@ -2574,8 +2574,10 @@ HB_CPU3:
 ;
 ;;; LOCATION OF THIS CODE???
 ;
+#IF (CPUFAM != CPU_EZ80)
 	LD	A,(CB_CPUMHZ)		; CPU SPEED TO ACCUM AND INIT
 	CALL	DELAY_INIT		; .. SPEED COMPENSATED DELAY
+#ENDIF
 ;
 ;--------------------------------------------------------------------------------------------------
 ; SYSTEM TIMER INITIALIZATION
@@ -2947,42 +2949,6 @@ PSCNX	.EQU	$ + 1
 	DJNZ	PSCN1
 ;
 #ENDIF
-
-#IF (CPUFAM == CPU_EZ80)
-;
-;--------------------------------------------------------------------------------------------------
-; DELAY LOOP TEST CALIBRATION
-;--------------------------------------------------------------------------------------------------
-;
-; IF ENABLED, THE GPIO PCBx PINS OF THE EZ80 WILL BE TOGGLED AT 'DELAY' RATE
-; CAN BE USED TO VERIFY DELAY WORKS SUFFICIENT FOR DIFFERENT EZ80 CLOCK SPEEDS
-; AND BUS CYCLES
-;
-#IF FALSE
-
-PC_DR:		.equ	$009E
-PC_DDR:		.equ	$009F
-
-	; ENABLE PC5 GPIO AS OUTPUT
-	LD	BC, PC_DDR
-	XOR	A
-	OUT	(C), A
-	PUSH	AF
-
-	LD	BC, PC_DR
-	LD	D, 0
-LOOP:
-	POP	AF
-	OUT	(C), A
-	CPL
-	PUSH	AF
-
-	LD	DE, 2
-	CALL	VDELAY
-	JR	LOOP
-#ENDIF
-#ENDIF
-
 ;
 ;--------------------------------------------------------------------------------------------------
 ; CPU SPEED DETECTION ALIGNMENT TEST
@@ -5703,9 +5669,11 @@ SYS_SETCPUSPD2:
 	ADC	A,C			; C -> A; ADD CF FOR ROUNDING
 	LD	(CB_CPUMHZ),A		; SAVE IT
 ;
+#IF (CPUFAM != CPU_EZ80)
 	;  REINIT DELAY ROUTINE
 	LD	A,(CB_CPUMHZ)		; CPU SPEED TO ACCUM AND INIT
 	CALL	DELAY_INIT		; .. SPEED COMPENSATED DELAY
+#ENDIF
 ;
 SYS_SETCPUSPD3:
 	XOR	A
@@ -5748,9 +5716,11 @@ SYS_SETCPUSPD2:
 	ADC	A,C			; C -> A; ADD CF FOR ROUNDING
 	LD	(CB_CPUMHZ),A		; SAVE IT
 ;
+#IF (CPUFAM != CPU_EZ80)
 	;  REINIT DELAY ROUTINE
 	LD	A,(CB_CPUMHZ)		; CPU SPEED TO ACCUM AND INIT
 	CALL	DELAY_INIT		; .. SPEED COMPENSATED DELAY
+#ENDIF
 ;
 	XOR	A			; SIGNAL SUCCESS
 	RET
@@ -5885,9 +5855,11 @@ SYS_SETCPUSPD4:
 	LD	A,L			; WORKING VALUE TO A
 	OUT0	(Z180_DCNTL),A		; IMPLEMENT NEW VALUE
 ;
+#IF (CPUFAM != CPU_EZ80)
 	;  REINIT DELAY ROUTINE
 	LD	A,(CB_CPUMHZ)		; CPU SPEED TO ACCUM AND INIT
 	CALL	DELAY_INIT		; .. SPEED COMPENSATED DELAY
+#ENDIF
 ;
   #IF ((INTMODE == 2) & (Z180_TIMER))
 	; THE Z180 TIMER IS BASED ON CPU SPEED.  SO HERE
diff --git a/Source/HBIOS/sn76489.asm b/Source/HBIOS/sn76489.asm
index 8a41fe7d..c6e8c42c 100644
--- a/Source/HBIOS/sn76489.asm
+++ b/Source/HBIOS/sn76489.asm
@@ -87,6 +87,7 @@ SN7_INIT:
 #IFDEF SBCV2004
 	LD	A,(HB_RTCVAL)
 	OR	%00001000		; SBC-V2-004+ CHANGE
+	EZ80_IO
 	OUT	(RTCIO),A		; TO HALF CLOCK SPEED
 #ENDIF
 ;
@@ -95,13 +96,16 @@ SN7_INIT:
 SN7_INIT1
 	LD	A,(HL)
 	INC	HL			; BUMP FOR NEXT TIME
+	EZ80_IO
 	OUT	(SN76489_PORT_LEFT), A	; WRITE LEFT PORT
+	EZ80_IO
 	OUT	(SN76489_PORT_RIGHT), A	; WRITE RIGHT PORT
 	DJNZ	SN7_INIT1		; LOOP TILL DONE
 ;
 #IFDEF SBCV2004
 	LD	A,(HB_RTCVAL)
 	AND	%11110111		; SBC-V2-004+ CHANGE TO
+	EZ80_IO
 	OUT	(RTCIO),A		; NORMAL CLOCK SPEED
 #ENDIF
 ;
@@ -288,16 +292,19 @@ SN7_APPLY_VOL:				; APPLY VOLUME TO BOTH LEFT AND RIGHT CHANNELS
 	PUSH	AF
 	LD	A,(HB_RTCVAL)
 	OR	%00001000		; SBC-V2-004+ CHANGE
+	EZ80_IO
 	OUT	(RTCIO),A		; TO HALF CLOCK SPEED
 	POP	AF
 #ENDIF
-
+	EZ80_IO
 	OUT	(SN76489_PORT_LEFT), A
+	EZ80_IO
 	OUT	(SN76489_PORT_RIGHT), A
 
 #IFDEF SBCV2004
 	LD	A,(HB_RTCVAL)
 	AND	%11110111		; SBC-V2-004+ CHANGE TO
+	EZ80_IO
 	OUT	(RTCIO),A		; NORMAL CLOCK SPEED
 #ENDIF
 
@@ -333,16 +340,19 @@ SN7_APPLY_PRD:
 	PUSH	AF
 	LD	A,(HB_RTCVAL)
 	OR	%00001000		; SBC-V2-004+ CHANGE
+	EZ80_IO
 	OUT	(RTCIO),A		; TO HALF CLOCK SPEED
 	POP	AF
 #ENDIF
-
+	EZ80_IO
 	OUT	(SN76489_PORT_LEFT), A
+	EZ80_IO
 	OUT	(SN76489_PORT_RIGHT), A
 
 #IFDEF SBCV2004
 	LD	A,(HB_RTCVAL)
 	AND	%11110111		; SBC-V2-004+ CHANGE TO
+	EZ80_IO
 	OUT	(RTCIO),A		; NORMAL CLOCK SPEED
 #ENDIF
 
@@ -370,16 +380,19 @@ SN7_APPLY_PRD:
 	PUSH	AF
 	LD	A,(HB_RTCVAL)
 	OR	%00001000		; SBC-V2-004+ CHANGE
+	EZ80_IO
 	OUT	(RTCIO),A		; TO HALF CLOCK SPEED
 	POP	AF
 #ENDIF
-
+	EZ80_IO
 	OUT	(SN76489_PORT_LEFT), A
+	EZ80_IO
 	OUT	(SN76489_PORT_RIGHT), A
 
 #IFDEF SBCV2004
 	LD	A,(HB_RTCVAL)
 	AND	%11110111		; SBC-V2-004+ CHANGE TO
+	EZ80_IO
 	OUT	(RTCIO),A		; NORMAL CLOCK SPEED
 #ENDIF
 
diff --git a/Source/HBIOS/util.asm b/Source/HBIOS/util.asm
index 1cf2fbd3..55c65f43 100644
--- a/Source/HBIOS/util.asm
+++ b/Source/HBIOS/util.asm
@@ -554,7 +554,7 @@ BYTE2BCD1:
 	RET
 
 #IFDEF USEDELAY
-
+#IF (CPUFAM != CPU_EZ80)
 ;
 ; DELAY 16US (CPU SPEED COMPENSATED) INCUDING CALL/RET INVOCATION
 ; REGISTER A AND FLAGS DESTROYED
@@ -632,6 +632,7 @@ VDELAY1:			;				|	|
 ;									|
 	RET			; 10TS (FINAL RETURN)			|
 	;---------------------------------------------------------------+
+#ENDIF
 ;
 ; DELAY ABOUT 0.5 SECONDS
 ; 500000US / 16US = 31250
@@ -644,6 +645,7 @@ LDELAY:
 	POP	DE
 	POP	AF
 	RET
+#IF (CPUFAM != CPU_EZ80)
 ;
 ; INITIALIZE DELAY SCALER BASED ON OPERATING CPU SPEED
 ; ENTER WITH A = CPU SPEED IN MHZ
@@ -666,6 +668,8 @@ CPUSCL	.DB	CPUMHZ - 2		; OTHERWISE 2 LESS THAN PHI MHZ
   #ENDIF
 ;
 #ENDIF
+#ENDIF
+
 ;
 ; SHORT DELAY FUNCTIONS.  NO CLOCK SPEED COMPENSATION, SO THEY
 ; WILL RUN LONGER ON SLOWER SYSTEMS.  THE NUMBER INDICATES THE