;
; Z280 CPU CONTROL REGISTERS (VIA LDCTL)
;
Z280_MSR	.EQU	$00	; MASTER STATUS REG
Z280_ISR	.EQU	$16	; INTERRUPT STATUS REG
Z280_VPR	.EQU	$06	; INT/TRAP VECT PTR REG
Z280_IOPR	.EQU	$08	; I/O PAGE REG
Z280_BTIR	.EQU	$FF	; BUS TIMING & INIT REG
Z280_BTCR	.EQU	$02	; BUS TIMING & CONTROL REG
Z280_SLR	.EQU	$04	; STACK LIMIT REG
Z280_TCR	.EQU	$10	; TRAP CONTROL REG
Z280_CCR	.EQU	$12	; CACHE CONTROL REG
Z280_LAR	.EQU	$14	; LOCAL ADDRESS REG
;
; Z280 PAGE $FF REGSISTER ADDRESSES
;
Z280_RRR	.EQU	$E8	; Z280 REFRESH RATE REG
;
Z280_MMUMCR	.EQU	$F0	; Z280 MMU MASTER CONTROL REG
Z280_MMUPDRPTR	.EQU	$F1	; Z280 MMU PDR POINTER REG
Z280_MMUINV	.EQU	$F2	; Z280 MMU INVALIDATION PORT
Z280_MMUBLKMOV	.EQU	$F4	; Z280 MMU BLOCK MOVE PORT
Z280_MMUPDR	.EQU	$F5	; Z280 MMU PDR PORT
;
Z280_DMA0_DSTL	.EQU	$00	; DMA0 DESTINATION ADDRESS LOW
Z280_DMA0_DSTH	.EQU	$01	; DMA0 DESTINATION ADDRESS HIGH
Z280_DMA0_SRCL	.EQU	$02	; DMA0 SOURCE ADDRESS LOW
Z280_DMA0_SRCH	.EQU	$03	; DMA0 SOURCE ADDRESS HIGH
Z280_DMA0_CNT	.EQU	$04	; DMA0 COUNT
Z280_DMA0_TDR	.EQU	$05	; DMA0 TRANSACTION DESCRIPTION REG
;
Z280_DMA1_DSTL	.EQU	$08	; DMA1 DESTINATION ADDRESS LOW
Z280_DMA1_DSTH	.EQU	$09	; DMA1 DESTINATION ADDRESS HIGH
Z280_DMA1_SRCL	.EQU	$0A	; DMA1 SOURCE ADDRESS LOW
Z280_DMA1_SRCH	.EQU	$0B	; DMA1 SOURCE ADDRESS HIGH
Z280_DMA1_CNT	.EQU	$0C	; DMA1 COUNT
Z280_DMA1_TDR	.EQU	$0D	; DMA1 TRANSACTION DESCRIPTION REG
;
Z280_DMA2_DSTL	.EQU	$10	; DMA2 DESTINATION ADDRESS LOW
Z280_DMA2_DSTH	.EQU	$11	; DMA2 DESTINATION ADDRESS HIGH
Z280_DMA2_SRCL	.EQU	$12	; DMA2 SOURCE ADDRESS LOW
Z280_DMA2_SRCH	.EQU	$13	; DMA2 SOURCE ADDRESS HIGH
Z280_DMA2_CNT	.EQU	$14	; DMA2 COUNT
Z280_DMA2_TDR	.EQU	$15	; DMA2 TRANSACTION DESCRIPTION REG
;
Z280_DMA3_DSTL	.EQU	$18	; DMA3 DESTINATION ADDRESS LOW
Z280_DMA3_DSTH	.EQU	$19	; DMA3 DESTINATION ADDRESS HIGH
Z280_DMA3_SRCL	.EQU	$1A	; DMA3 SOURCE ADDRESS LOW
Z280_DMA3_SRCH	.EQU	$1B	; DMA3 SOURCE ADDRESS HIGH
Z280_DMA3_CNT	.EQU	$1C	; DMA3 COUNT
Z280_DMA3_TDR	.EQU	$1D	; DMA3 TRANSACTION DESCRIPTION REG
;
; Z280 PAGE $FE REGSISTER ADDRESSES
;
Z280_UARTCFG	.EQU	$10	; UART CONFIG REG
Z280_UARTXCTL	.EQU	$12	; UART TRANSMIT CONTROL/STATUS REG
Z280_UARTRCTL	.EQU	$14	; UART RECEIVE CONTROL/STATUS REG
Z280_UARTRECV	.EQU	$16	; UART RECEIVE DATA REG
Z280_UARTXMIT	.EQU	$18	; UART TRANSMIT DATA REG
;
Z280_CT0_CFG	.EQU	$E0	; COUNTER/TIMER 0 CONFIG REG
Z280_CT0_CMDST	.EQU	$E1	; COUNTER/TIMER 0 COMMAND/STATUS REG
Z280_CT0_TC	.EQU	$E2	; COUNTER/TIMER 0 TIME CONSTANT
Z280_CT0_CT	.EQU	$E3	; COUNTER/TIMER 0 COUNT TIME
;
Z280_CT1_CFG	.EQU	$E8	; COUNTER/TIMER 1 CONFIG REG
Z280_CT1_CMDST	.EQU	$E9	; COUNTER/TIMER 1 COMMAND/STATUS REG
Z280_CT1_TC	.EQU	$EA	; COUNTER/TIMER 1 TIME CONSTANT
Z280_CT1_CT	.EQU	$EB	; COUNTER/TIMER 1 COUNT TIME
;
Z280_CT2_CFG	.EQU	$F8	; COUNTER/TIMER 2 CONFIG REG
Z280_CT2_CMDST	.EQU	$F9	; COUNTER/TIMER 2 COMMAND/STATUS REG
Z280_CT2_TC	.EQU	$FA	; COUNTER/TIMER 2 TIME CONSTANT
Z280_CT2_CT	.EQU	$FB	; COUNTER/TIMER 2 COUNT TIME
;
; Z280 INSTRUCTIONS (INCOMPLETE, JUST THE ONES USED)
;
.ADDINSTR	PCACHE	""	65ED	2 NOP 1
.ADDINSTR	LDCTL	(C),HL	6EED	2 NOP 1
.ADDINSTR	LDCTL	HL,(C)	66ED	2 NOP 1
.ADDINSTR	IM	3	4EED	2 NOP 1
.ADDINSTR	LDCTL	USP,HL	8FED	2 NOP 1
.ADDINSTR	LDCTL	IY,(C)	66EDFD	3 NOP 1
.ADDINSTR	LDCTL	(C),IY	6EEDFD	3 NOP 1
.ADDINSTR	MULTU	A,*	F9EDFD	4 NOP 1
.ADDINSTR	LD2	HL,(HL)	26ED	2 NOP 1
.ADDINSTR	LD2	(HL),DE	1EED	2 NOP 1