af2639ef42
Enhance CSIO to play nice(r) with other users of Z180 CSIO by restoring the CSIO speed to default upon function return.
567 lines
18 KiB
NASM
567 lines
18 KiB
NASM
; The purpose of this file is to define generic symbols and to include
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; the requested build configuraton file to bring in platform specifics.
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; There are several hardware platforms supported by SBC.
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; 1. SBC Z80 SBC (v1 or v2) w/ ECB interface
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; 2. ZETA Standalone Z80 SBC w/ SBC compatibility
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; 3. ZETA2 Second version of ZETA with enhanced memory bank switching
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; 4. N8 MSX-ish Z180 SBC w/ onboard video and sound
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; 5. MK4 Mark IV Z180 based SBC w/ ECB interface
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; 6. UNA Any Z80/Z180 computer with UNA BIOS
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; 7. RCZ80 RC2014 based system with 512K banked RAM/ROM card
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; 8. RCZ180 RC2014 based system with Z180 CPU
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; 9. EZZ80 Easy Z80, Z80 SBC w/ RC2014 bus and CTC
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; 10. SCZ180 Steve Cousins Z180 based system
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; 11. DYNO Steve Garcia's Dyno Micro-ATX Motherboard
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;
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; INCLUDE VERSION
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;
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#INCLUDE "../ver.inc" ; ADD BIOSVER
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;
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FALSE .EQU 0
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TRUE .EQU ~FALSE
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;
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; DEBUGGING OPTIONS
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;
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USENONE .EQU 0 ; NO DEBUG
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USEXIO .EQU 1 ; BASIC SERIAL DRIVER
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USEMIO .EQU 2 ; MEMORY BUFFER DRIVER
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WBWDEBUG .EQU USENONE
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;
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; DIAGNOSTIC LEVEL OPTIONS
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;
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DL_NONE .EQU 0 ; HBIOS DISPLAY NO MESSAGES
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DL_CRITICAL .EQU 4 ; HBIOS DISPLAY CRITICAL ERROR MESSAGES
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DL_ERROR .EQU 8 ; HBIOS DISPLAYS ALL ERROR MESSAGES
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DL_WARNING .EQU 12 ; HBIOS DISPLAYS WARNING MESSAGES
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DL_INFO .EQU 16 ; HBIOS DISPLAYS INFORMATIONAL MESSAGES
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DL_DETAIL .EQU 20 ; HBIOS DISPLAYS DETAILED DIAGNOSTIC MESSAGES
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DL_VERBOSE .EQU 24 ; HBIOS DISPLAYS ANYTHING IT KNOWS HOW TO
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;
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; PRIMARY HARDWARE PLATFORMS
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;
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PLT_SBC .EQU 1 ; SBC ECB Z80 SBC
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PLT_ZETA .EQU 2 ; ZETA Z80 SBC
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PLT_ZETA2 .EQU 3 ; ZETA Z80 V2 SBC
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PLT_N8 .EQU 4 ; N8 (HOME COMPUTER) Z180 SBC
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PLT_MK4 .EQU 5 ; MARK IV
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PLT_UNA .EQU 6 ; UNA BIOS
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PLT_RCZ80 .EQU 7 ; RC2014 W Z80
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PLT_RCZ180 .EQU 8 ; RC2014 W/ Z180
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PLT_EZZ80 .EQU 9 ; EASY Z80
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PLT_SCZ180 .EQU 10 ; SCZ180
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PLT_DYNO .EQU 11 ; DYNO MICRO-ATX MOTHERBOARD
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;
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;
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; CPU TYPES
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;
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CPU_NONE .EQU 0 ; NO CPU TYPE DEFINED
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CPU_Z80 .EQU 1 ; Z80 FAMILY
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CPU_Z180 .EQU 2 ; Z180 FAMILY
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CPU_Z280 .EQU 3 ; Z280 FAMILY
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;
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; BIOS MODE
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;
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BIOS_NONE .EQU 0 ; NO BIOS TYPE DEFINED
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BIOS_WBW .EQU 1 ; ROMWBW HBIOS
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BIOS_UNA .EQU 2 ; UNA UBIOS
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;
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; DEFAULT HBIOS DIAGNOSTIC LEVEL
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; WILL ULTIMATELY BE MOVED TO CONFIG FILE
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;
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DIAGLVL .EQU DL_CRITICAL
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;
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; MEMORY MANAGERS
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;
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MM_NONE .EQU 0
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MM_SBC .EQU 1 ; ORIGINAL N8VEM/RBC Z80 SBC BANKED MEMORY
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MM_Z2 .EQU 2 ; 16K X 4 BANKED MEMORY INTRODUCED ON ZETA2
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MM_N8 .EQU 3 ; Z180 CUSTOMIZED FOR N8 MEMORY EXTENSIONS
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MM_Z180 .EQU 4 ; Z180 NATIVE MEMORY MANAGER
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MM_Z280 .EQU 5 ; Z280 NATIVE MEMORY MANAGER
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MM_ZRC .EQU 6 ; ZRC BANK SWITCHING
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;
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; BOOT STYLE
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;
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BT_MENU .EQU 1 ; WAIT FOR MENU SELECTION AT LOADER PROMPT
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BT_AUTO .EQU 2 ; AUTO SELECT BOOT_DEFAULT AFTER BOOT_TIMEOUT
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;
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; BOOT RECOVERY METHODS
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;
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BT_REC_NONE .EQU 0 ; NO RECOVERY MODE
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BT_REC_FORCE .EQU 1 ; FORCE BOOT RECOVERY MODE
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BT_REC_SBC01 .EQU 2 ; ECB-SBCV2 - BIT 1 RTC HIGH
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BT_REC_SBC1B .EQU 3 ; ECB-SBCV2 - 1-BIT IO PORT
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BT_REC_SBCRI .EQU 4 ; ECB-SBCV2 - 16550 UART RING INDICATOR LINE
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;
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BT_REC_TYPE .EQU BT_REC_NONE ; BOOT RECOVERY METHOD TO USE
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;
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; FLOPPY DISK MEDIA SELECTIONS (ID'S MUST BE INDEX OF ENTRY IN FCD_TBL)
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;
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FDM720 .EQU 0 ; 3.5" FLOPPY, 720KB, 2 SIDES, 80 TRKS, 9 SECTORS
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FDM144 .EQU 1 ; 3.5" FLOPPY, 1.44MB, 2 SIDES, 80 TRKS, 18 SECTORS
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FDM360 .EQU 2 ; 5.25" FLOPPY, 360KB, 2 SIDES, 40 TRKS, 9 SECTORS
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FDM120 .EQU 3 ; 5.25" FLOPPY, 1.2MB, 2 SIDES, 80 TRKS, 15 SECTORS
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FDM111 .EQU 4 ; 8" FLOPPY, 1.11MB, 2 SIDES, 74 TRKS, 15 SECTORS
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;
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; ZILOG CTC MODE SELECTIONS
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;
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CTCMODE_NONE .EQU 0 ; NO CTC
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CTCMODE_CTR .EQU 1 ; CTC COUNTER
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CTCMODE_TIM16 .EQU 2 ; CTC TIMER W/ DIV 16
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CTCMODE_TIM256 .EQU 3 ; CTC TIMER W/ DIV 256
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;
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; DS RTC MODE SELECTIONS
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;
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DSRTCMODE_NONE .EQU 0 ; NO DSRTC
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DSRTCMODE_STD .EQU 1 ; ORIGINAL DSRTC CIRCUIT (SBC, ZETA, MK4)
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DSRTCMODE_MFPIC .EQU 2 ; MF/PIC VARIANT
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;
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; SIO MODE SELECTIONS
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;
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SIOMODE_NONE .EQU 0
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SIOMODE_STD .EQU 1 ; STD SIO REG CFG (EZZ80, KIO)
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SIOMODE_RC .EQU 2 ; RC2014 SIO MODULE (SPENCER OWEN)
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SIOMODE_SMB .EQU 3 ; RC2014 SIO MODULE (SCOTT BAKER)
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SIOMODE_ZP .EQU 4 ; ECB-ZILOG PERIPHERALS BOARD
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;
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; TYPE OF CONSOLE BELL TO USE
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;
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CONBELL_NONE .EQU 0
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CONBELL_PSG .EQU 1
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CONBELL_IOBIT .EQU 2
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;
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; FD MODE SELECTIONS
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;
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FDMODE_NONE .EQU 0
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FDMODE_DIO .EQU 1 ; DISKIO V1
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FDMODE_ZETA .EQU 2 ; ZETA
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FDMODE_ZETA2 .EQU 3 ; ZETA V2
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FDMODE_DIDE .EQU 4 ; DUAL IDE
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FDMODE_N8 .EQU 5 ; N8
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FDMODE_DIO3 .EQU 6 ; DISKIO V3
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FDMODE_RCSMC .EQU 7 ; RC2014 SMC 9266 @ $40 (SCOTT BAKER)
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FDMODE_RCWDC .EQU 8 ; RC2014 WDC 37C65 @ $40 (SCOTT BAKER)
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FDMODE_DYNO .EQU 9 ; DYNO WDC 37C65 @ $84
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FDMODE_EPFDC .EQU 10 ; RC2014 ETCHED PIXELS FDC
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;
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; IDE MODE SELECTIONS
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;
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IDEMODE_NONE .EQU 0
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IDEMODE_DIO .EQU 1 ; DISKIO V1
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IDEMODE_DIDE .EQU 2 ; DUAL IDE
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IDEMODE_MK4 .EQU 3 ; MARK IV ONBOARD IDE (8 BIT ONLY)
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IDEMODE_RC .EQU 4 ; RC2014 CF MODULE (8 BIT ONLY)
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;
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; PPIDE MODE SELECTIONS
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;
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PPIDEMODE_NONE .EQU 0
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PPIDEMODE_SBC .EQU 1 ; STANDARD SBC PARALLEL PORT
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PPIDEMODE_DIO3 .EQU 2 ; DISKIO V3 PARALLEL PORT
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PPIDEMODE_MFP .EQU 3 ; MULTIFUNCTION / PIC
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PPIDEMODE_N8 .EQU 4 ; MULTIFUNCTION / PIC
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PPIDEMODE_RC .EQU 5 ; RC2014 PPIDE MODULE @ $20 (ED BRINDLEY)
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PPIDEMODE_DYNO .EQU 6 ; DYNO PPIDE @ $4C
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;
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; SD MODE SELECTIONS
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;
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SDMODE_NONE .EQU 0
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SDMODE_JUHA .EQU 1 ; JUHA MINI BOARD
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SDMODE_N8 .EQU 2 ; N8-2511, UNMODIFIED
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SDMODE_CSIO .EQU 3 ; N8-2312 OR N8-2511 MODIFIED
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SDMODE_PPI .EQU 4 ; PPISD MINI BOARD
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SDMODE_UART .EQU 5 ; SD INTERFACE VIA UART
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SDMODE_DSD .EQU 6 ; DUAL SD
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SDMODE_MK4 .EQU 7 ; MARK IV
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SDMODE_SC .EQU 8 ; SC (Steve Cousins)
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SDMODE_MT .EQU 9 ; MT (Shift register SPI WIZNET for RC2014)
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;
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; SOUND CHIP MODE SELECTIONS
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;
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AYMODE_NONE .EQU 0
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AYMODE_N8 .EQU 1 ; N8 BUILT-IN SOUND
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AYMODE_SCG .EQU 2 ; SCG ECB BOARD
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AYMODE_RCZ80 .EQU 3 ; RC2014 SOUND MODULE BY ED BRINDLEY ON Z80
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AYMODE_RCZ180 .EQU 4 ; RC2014 SOUND MODULE BY ED BRINDLEY ON Z180
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AYMODE_MSX .EQU 5 ; RC2014 SOUND MODULE REV6 BY ED BRINDLEY ON Z80/Z180 AT MSX PORTS
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;
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; TMS VIDEO MODE SELECTIONS
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;
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TMSMODE_NONE .EQU 0
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TMSMODE_SCG .EQU 1 ; SCG ECB BOARD
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TMSMODE_N8 .EQU 2 ; N8 BUILT-IN VIDEO
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TMSMODE_RC .EQU 3 ; RC2014 BUILT-IN VIDEO
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;
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; SERIAL DEVICE CONFIGURATION CONSTANTS
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;
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SER_DATA5 .EQU 0 << 0
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SER_DATA6 .EQU 1 << 0
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SER_DATA7 .EQU 2 << 0
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SER_DATA8 .EQU 3 << 0
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;
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SER_PARNONE .EQU 0 << 3
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SER_PARODD .EQU 1 << 3
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SER_PAREVEN .EQU 3 << 3
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SER_PARMARK .EQU 5 << 3
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SER_PARSPACE .EQU 7 << 3
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;
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SER_STOP1 .EQU 0 << 2
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SER_STOP2 .EQU 1 << 2
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;
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; SERIAL BAUD RATES ENCODED AS V = 75 * 2^X * 3^Y
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; AND STORED AS 5 BITS: YXXXX
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;
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SER_BAUD75 .EQU $00 << 8
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SER_BAUD150 .EQU $01 << 8
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SER_BAUD300 .EQU $02 << 8
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SER_BAUD600 .EQU $03 << 8
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SER_BAUD1200 .EQU $04 << 8
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SER_BAUD2400 .EQU $05 << 8
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SER_BAUD4800 .EQU $06 << 8
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SER_BAUD9600 .EQU $07 << 8
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SER_BAUD19200 .EQU $08 << 8
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SER_BAUD38400 .EQU $09 << 8
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SER_BAUD76800 .EQU $0A << 8
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SER_BAUD153600 .EQU $0B << 8
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SER_BAUD307200 .EQU $0C << 8
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SER_BAUD614400 .EQU $0D << 8
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SER_BAUD1228800 .EQU $0E << 8
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SER_BAUD2457600 .EQU $0F << 8
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SER_BAUD225 .EQU $10 << 8
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SER_BAUD450 .EQU $11 << 8
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SER_BAUD900 .EQU $12 << 8
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SER_BAUD1800 .EQU $13 << 8
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SER_BAUD3600 .EQU $14 << 8
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SER_BAUD7200 .EQU $15 << 8
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SER_BAUD14400 .EQU $16 << 8
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SER_BAUD28800 .EQU $17 << 8
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SER_BAUD57600 .EQU $18 << 8
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SER_BAUD115200 .EQU $19 << 8
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SER_BAUD230400 .EQU $1A << 8
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SER_BAUD460800 .EQU $1B << 8
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SER_BAUD921600 .EQU $1C << 8
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SER_BAUD1843200 .EQU $1D << 8
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SER_BAUD3686400 .EQU $1E << 8
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SER_BAUD7372800 .EQU $1F << 8
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;
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SER_XON .EQU 1 << 6
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SER_DTR .EQU 1 << 7
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SER_RTS .EQU 1 << 13
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;
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SER_75_8N1 .EQU SER_BAUD75 | SER_DATA8 | SER_PARNONE | SER_STOP1
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SER_150_8N1 .EQU SER_BAUD150 | SER_DATA8 | SER_PARNONE | SER_STOP1
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SER_300_8N1 .EQU SER_BAUD300 | SER_DATA8 | SER_PARNONE | SER_STOP1
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SER_600_8N1 .EQU SER_BAUD600 | SER_DATA8 | SER_PARNONE | SER_STOP1
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SER_1200_8N1 .EQU SER_BAUD1200 | SER_DATA8 | SER_PARNONE | SER_STOP1
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SER_2400_8N1 .EQU SER_BAUD2400 | SER_DATA8 | SER_PARNONE | SER_STOP1
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SER_4800_8N1 .EQU SER_BAUD4800 | SER_DATA8 | SER_PARNONE | SER_STOP1
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SER_9600_8N1 .EQU SER_BAUD9600 | SER_DATA8 | SER_PARNONE | SER_STOP1
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SER_19200_8N1 .EQU SER_BAUD19200 | SER_DATA8 | SER_PARNONE | SER_STOP1
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SER_38400_8N1 .EQU SER_BAUD38400 | SER_DATA8 | SER_PARNONE | SER_STOP1
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SER_76800_8N1 .EQU SER_BAUD76800 | SER_DATA8 | SER_PARNONE | SER_STOP1
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SER_153600_8N1 .EQU SER_BAUD153600 | SER_DATA8 | SER_PARNONE | SER_STOP1
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SER_307200_8N1 .EQU SER_BAUD307200 | SER_DATA8 | SER_PARNONE | SER_STOP1
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SER_614400_8N1 .EQU SER_BAUD614400 | SER_DATA8 | SER_PARNONE | SER_STOP1
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SER_1228800_8N1 .EQU SER_BAUD1228800 | SER_DATA8 | SER_PARNONE | SER_STOP1
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SER_2457600_8N1 .EQU SER_BAUD2457600 | SER_DATA8 | SER_PARNONE | SER_STOP1
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SER_225_8N1 .EQU SER_BAUD225 | SER_DATA8 | SER_PARNONE | SER_STOP1
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SER_450_8N1 .EQU SER_BAUD450 | SER_DATA8 | SER_PARNONE | SER_STOP1
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SER_900_8N1 .EQU SER_BAUD900 | SER_DATA8 | SER_PARNONE | SER_STOP1
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SER_1800_8N1 .EQU SER_BAUD1800 | SER_DATA8 | SER_PARNONE | SER_STOP1
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SER_3600_8N1 .EQU SER_BAUD3600 | SER_DATA8 | SER_PARNONE | SER_STOP1
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SER_7200_8N1 .EQU SER_BAUD7200 | SER_DATA8 | SER_PARNONE | SER_STOP1
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SER_14400_8N1 .EQU SER_BAUD14400 | SER_DATA8 | SER_PARNONE | SER_STOP1
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SER_28800_8N1 .EQU SER_BAUD28800 | SER_DATA8 | SER_PARNONE | SER_STOP1
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SER_57600_8N1 .EQU SER_BAUD57600 | SER_DATA8 | SER_PARNONE | SER_STOP1
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SER_115200_8N1 .EQU SER_BAUD115200 | SER_DATA8 | SER_PARNONE | SER_STOP1
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SER_230400_8N1 .EQU SER_BAUD230400 | SER_DATA8 | SER_PARNONE | SER_STOP1
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SER_460800_8N1 .EQU SER_BAUD460800 | SER_DATA8 | SER_PARNONE | SER_STOP1
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SER_921600_8N1 .EQU SER_BAUD921600 | SER_DATA8 | SER_PARNONE | SER_STOP1
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SER_1843200_8N1 .EQU SER_BAUD1843200 | SER_DATA8 | SER_PARNONE | SER_STOP1
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SER_3686400_8N1 .EQU SER_BAUD3686400 | SER_DATA8 | SER_PARNONE | SER_STOP1
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SER_7372800_8N1 .EQU SER_BAUD7372800 | SER_DATA8 | SER_PARNONE | SER_STOP1
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;
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; TERMENABLE CONTROLS INCLUSION OF TERMINAL PSEUDO-DEVICE DRIVER
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; IT IS SET TO TRUE BY THE INCLUSION OF ANY VDA DRIVER.
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;
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TERMENABLE .EQU FALSE ; TERM PSEUDO DEVICE, WILL AUTO-ENABLE IF A VDA IS ENABLED
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;
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; VIDEO MODES
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;
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V80X24 .EQU 0 ; ECB-VDU
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V80X25 .EQU 1 ; ECB-VDU, ECB-VGA3
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V80X30 .EQU 2 ; ECB-VDU, ECB-VGA3
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V80X25B .EQU 3 ; ECB-VDU
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V80X24B .EQU 4 ; ECB-VDU
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V80X43 .EQU 5 ; ECB-VGA3
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V80X60 .EQU 6 ; ECB-VGA3
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;
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; KEYBOARD LAYOUTS
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;
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KBD_US .EQU 0 ; US ENGLISH
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KBD_DE .EQU 1 ; GERMAN
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;
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; EMULATION TYPES
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;
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EMUTYP_NONE .EQU 0 ; NONE
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EMUTYP_TTY .EQU 1 ; TTY
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EMUTYP_ANSI .EQU 2 ; ANSI
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;
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; DEVICE DRIVER TO BE INITIALIZED FIRST. FIRST CIO DRIVER, UNIT 0 INITIALIZED BECOMES PRIMARY CONSOLE.
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; IS AN INDEX INTO THE ENABLED INITIALIZATION DRIVER LIST i.e. ASCI, UART, SIO, ACIA, PIO, UF ETC.
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; EXAMPLE: IF ONLY UART, SIO AND PIO ARE ENABLE AND THE SIO IS DESIRED AS THE PRIMARY CONSOLE,
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; SET FORCECON TO 2 IN YOUR CUSTOM CONFIGURATION FILE i.e. "FORCECON: .SET 2"
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;
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FORCECON .EQU 0 ; DEFAULT IS TO FOLLOW NORMAL SEQUENCE
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;
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#INCLUDE "build.inc" ; INCLUDE USER CONFIG, ADD VARIANT, TIMESTAMP, & ROMSIZE
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;
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#IF (BIOS == BIOS_WBW)
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#INCLUDE "hbios.inc"
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#ENDIF
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;
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#IF (BIOS == BIOS_UNA)
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#INCLUDE "../UBIOS/ubios.inc"
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#ENDIF
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;
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;
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; INCLUDE Z180 REGISTER DEFINITIONS
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;
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#IF (BIOS == BIOS_WBW)
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#IF (CPUFAM == CPU_Z180)
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#INCLUDE "z180.inc"
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#ENDIF
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#IF (CPUFAM == CPU_Z280)
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#INCLUDE "z280.inc"
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#ENDIF
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#IF (EIPCENABLE)
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#INCLUDE "eipc.inc"
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#ENDIF
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#ENDIF
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;
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; SETUP DEFAULT CPU SPEED VALUES
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;
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CPUKHZ .EQU CPUOSC / 1000 ; CPU FREQ IN KHZ
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;
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#IF (BIOS == BIOS_WBW)
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#IF (CPUFAM == CPU_Z180)
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#IF (Z180_CLKDIV == 0)
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CPUKHZ .SET CPUKHZ / 2 ; ADJUST FOR HALF SPEED OPERATION
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#ENDIF
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#IF (Z180_CLKDIV == 2)
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CPUKHZ .SET CPUKHZ * 2 ; ADJUST FOR DOUBLE SPEED OPERATION
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#ENDIF
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#ENDIF
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#IF (CPUFAM == CPU_Z280)
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CPUKHZ .SET CPUKHZ / 2 ; Z180 PHI IS ALWAYS 1/2 OSC
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#ENDIF
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#ENDIF
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;
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CPUMHZ .EQU CPUKHZ / 1000 ; CPU FREQ IN MHZ
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;
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; SYSTEM PERIODIC TIMER MODE
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;
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#IF (BIOS == BIOS_WBW)
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;
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TM_NONE .EQU 0
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TM_CTC .EQU 1
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TM_TMS .EQU 2
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TM_SIMH .EQU 3
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TM_Z180 .EQU 4
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|
;
|
|
.ECHO "SYSTEM TIMER:"
|
|
SYSTIM .EQU TM_NONE
|
|
;
|
|
#IF (CTCENABLE & (INTMODE == 2))
|
|
#IF (CTCTIMER)
|
|
SYSTIM .SET TM_CTC
|
|
.ECHO " CTC"
|
|
#ENDIF
|
|
#ENDIF
|
|
;
|
|
#IF (TMSENABLE & (INTMODE == 1))
|
|
#IF (TMSTIMENABLE)
|
|
SYSTIM .SET TM_TMS
|
|
.ECHO " TMS9918"
|
|
#ENDIF
|
|
#ENDIF
|
|
;
|
|
#IF ((PLATFORM == PLT_SBC) & (INTMODE == 1))
|
|
#IF (HTIMENABLE)
|
|
SYSTIM .SET TM_SIMH
|
|
.ECHO " SIMH"
|
|
#ENDIF
|
|
#ENDIF
|
|
;
|
|
#IF ((CPUFAM == CPU_Z180) & (INTMODE == 2))
|
|
SYSTIM .SET TM_Z180
|
|
.ECHO " Z180"
|
|
#ENDIF
|
|
;
|
|
#IF SYSTIM == TM_NONE
|
|
.ECHO " NONE"
|
|
#ENDIF
|
|
;
|
|
.ECHO "\n"
|
|
;
|
|
#ENDIF
|
|
;
|
|
; MEMORY BANK CONFIGURATION
|
|
;
|
|
#IF (BIOS == BIOS_UNA)
|
|
BID_ROM0 .EQU $0000
|
|
BID_RAM0 .EQU $8000
|
|
#ENDIF
|
|
;
|
|
#IF (BIOS == BIOS_WBW)
|
|
BID_ROM0 .EQU $00
|
|
BID_RAM0 .EQU $80
|
|
#ENDIF
|
|
|
|
BID_ROMN .EQU (BID_ROM0 + ((ROMSIZE / 32) - 1))
|
|
BID_RAMN .EQU (BID_RAM0 + ((RAMSIZE / 32) - 1))
|
|
|
|
BID_BOOT .EQU BID_ROM0 ; BOOT BANK
|
|
;BID_BIOSIMG .EQU BID_ROM0 + 1 ; BIOS IMAGE BANK
|
|
;BID_OSIMG .EQU BID_ROM0 + 2 ; ROM LOADER AND IMAGES BANK
|
|
BID_IMG0 .EQU BID_ROM0 + 1 ; ROM LOADER AND FIRST IMAGES BANK
|
|
BID_IMG1 .EQU BID_ROM0 + 2 ; SECOND IMAGES BANK
|
|
BID_FSFAT .EQU BID_ROM0 + 3 ; FAT FILESYSTEM DRIVER BANK
|
|
BID_ROMD0 .EQU BID_ROM0 + 4 ; FIRST ROM DRIVE BANK
|
|
BID_ROMDN .EQU BID_ROMN ; LAST ROM DRIVE BANK
|
|
|
|
BID_RAMD0 .EQU BID_RAM0 ; FIRST RAM DRIVE BANK
|
|
BID_RAMDN .EQU BID_RAMN - 4 ; LAST RAM DRIVE BANK
|
|
BID_AUX .EQU BID_RAMN - 3 ; AUX BANK (BPBIOS, ETC.)
|
|
BID_BIOS .EQU BID_RAMN - 2 ; BIOS BANK
|
|
BID_USR .EQU BID_RAMN - 1 ; USER BANK (CP/M TPA, ETC.)
|
|
BID_COM .EQU BID_RAMN ; COMMON BANK, UPPER 32K
|
|
;
|
|
; MEMORY LAYOUT
|
|
;
|
|
SYS_SIZ .EQU $3000 ; COMBINED SIZE OF SYSTEM AREA (OS + HBIOS PROXY)
|
|
HBBUF_SIZ .EQU 1024 ; INVARIANT HBIOS PHYSICAL DISK BUFFER, 1K
|
|
HBX_SIZ .EQU $200 ; HBIOS PROXY SIZE (SUBJECT TO CHANGE)
|
|
CPM_SIZ .EQU SYS_SIZ - HBX_SIZ ; NET SIZE OF ALL OS COMPONENTS (EXCLUDING HBIOS PROXY)
|
|
CCP_SIZ .EQU $800 ; INVARIANT SIZE OF CCP
|
|
BDOS_SIZ .EQU $E00 ; INVARIANT SIZE OF BDOS
|
|
CBIOS_SIZ .EQU CPM_SIZ - CCP_SIZ - BDOS_SIZ ; CBIOS IS THE REMAINDER
|
|
|
|
MEMTOP .EQU $10000 ; INVARIANT TOP OF Z80 ADDRESSABLE MEMORY
|
|
BNKTOP .EQU $8000 ; BANK MEMORY BARRIER
|
|
|
|
HBX_IMG .EQU $200 ; LOC OF HBX IMAGE IN HBIOS IMAGE BANK
|
|
|
|
HBBUF_END .EQU BNKTOP ; END OF PHYSICAL DISK BUFFER IN HBIOS
|
|
HBBUF_LOC .EQU HBBUF_END - HBBUF_SIZ ; START OF PHYSICAL DISK BUFFER
|
|
HBX_END .EQU MEMTOP ; END OF HBIOS PROXY
|
|
HBX_LOC .EQU HBX_END - HBX_SIZ ; START OF HBIOS PROXY
|
|
CPM_END .EQU HBX_LOC ; END OF CPM COMPONENTS (INCLUDING CBIOS)
|
|
CPM_LOC .EQU CPM_END - CPM_SIZ ; START OF CPM COMPONENTS
|
|
CBIOS_END .EQU HBX_LOC ; END OF CBIOS
|
|
CBIOS_LOC .EQU CBIOS_END - CBIOS_SIZ ; START OF CBIOS
|
|
|
|
CPM_ENT .EQU CBIOS_LOC ; CPM ENTRY POINT (IN CBIOS)
|
|
|
|
LDR_SIZ .EQU $0E00
|
|
|
|
MON_LOC .EQU $F000 ; LOCATION OF MONITOR FOR RUNNING SYSTEM
|
|
MON_SIZ .EQU $0E00 ; SIZE OF MONITOR BINARY IMAGE
|
|
MON_END .EQU MON_LOC + MON_SIZ ; END OF MONITOR
|
|
|
|
BAS_LOC .EQU $0200 ; NASCOM BASIC
|
|
BAS_SIZ .EQU $2000
|
|
BAS_END .EQU BAS_LOC + BAS_SIZ
|
|
|
|
TBC_LOC .EQU $0A00 ; TASTYBASIC
|
|
TBC_SIZ .EQU $0900
|
|
TBC_END .EQU TBC_LOC + TBC_SIZ
|
|
|
|
EGG_LOC .EQU $F000 ; EASTER EGG
|
|
EGG_SIZ .EQU $0200
|
|
EGG_END .EQU EGG_LOC + EGG_SIZ
|
|
|
|
FTH_LOC .EQU $0200 ; CAMEL FORTH
|
|
FTH_SIZ .EQU $1700
|
|
FTH_END .EQU FTH_LOC + FTH_SIZ
|
|
|
|
GAM_LOC .EQU $0200 ; GAME 2048
|
|
GAM_SIZ .EQU $0900
|
|
GAM_END .EQU GAM_LOC + GAM_SIZ
|
|
|
|
USR_LOC .EQU $0200 ; USER
|
|
USR_SIZ .EQU $1000
|
|
USR_END .EQU USR_LOC + USR_SIZ
|
|
|
|
MON_DSKY .EQU MON_LOC + (0 * 3) ; MONITOR ENTRY (DSKY)
|
|
MON_SERIAL .EQU MON_LOC + (1 * 3) ; MONITOR ENTRY (SERIAL PORT)
|
|
;
|
|
; INTERRUPT MODE 2 SLOT ASSIGNMENTS
|
|
;
|
|
#IF (INTMODE == 2)
|
|
|
|
#IF (CPUFAM == CPU_Z180)
|
|
|
|
; Z180-BASED SYSTEMS
|
|
|
|
INT_INT1 .EQU 0 ; Z180 INT 1
|
|
INT_INT2 .EQU 1 ; Z180 INT 2
|
|
INT_TIM0 .EQU 2 ; Z180 TIMER 0
|
|
INT_TIM1 .EQU 3 ; Z180 TIMER 1
|
|
INT_DMA0 .EQU 4 ; Z180 DMA 0
|
|
INT_DMA1 .EQU 5 ; Z180 DMA 1
|
|
INT_CSIO .EQU 6 ; Z180 CSIO
|
|
INT_SER0 .EQU 7 ; Z180 SERIAL 0
|
|
INT_SER1 .EQU 8 ; Z180 SERIAL 0
|
|
INT_PIO0A .EQU 9 ; ZILOG PIO 0, CHANNEL A
|
|
INT_PIO0B .EQU 10 ; ZILOG PIO 0, CHANNEL B
|
|
INT_PIO1A .EQU 11 ; ZILOG PIO 1, CHANNEL A
|
|
INT_PIO1B .EQU 12 ; ZILOG PIO 1, CHANNEL B
|
|
INT_SIO0 .EQU 13 ; ZILOG SIO 0, CHANNEL A & B
|
|
INT_SIO1 .EQU 14 ; ZILOG SIO 1, CHANNEL A & B
|
|
|
|
#ELSE
|
|
|
|
; Z80-BASED SYSTEMS
|
|
|
|
INT_CTC0A .EQU 0 ; ZILOG CTC 0, CHANNEL A
|
|
INT_CTC0B .EQU 1 ; ZILOG CTC 0, CHANNEL B
|
|
INT_CTC0C .EQU 2 ; ZILOG CTC 0, CHANNEL C
|
|
INT_CTC0D .EQU 3 ; ZILOG CTC 0, CHANNEL D
|
|
INT_SIO0 .EQU 7 ; ZILOG SIO 0, CHANNEL A & B
|
|
INT_SIO1 .EQU 8 ; ZILOG SIO 1, CHANNEL A & B
|
|
INT_PIO0A .EQU 9 ; ZILOG PIO 0, CHANNEL A
|
|
INT_PIO0B .EQU 10 ; ZILOG PIO 0, CHANNEL B
|
|
INT_PIO1A .EQU 11 ; ZILOG PIO 1, CHANNEL A
|
|
INT_PIO1B .EQU 12 ; ZILOG PIO 1, CHANNEL B
|
|
|
|
#ENDIF
|
|
|
|
#DEFINE IVT(INTX) HB_IVT+(INTX * 4)+1
|
|
#DEFINE VEC(INTX) INTX*2
|
|
|
|
#ENDIF
|
|
|
|
; SET DEFAULT CSIO SPEED (INTERNAL CLOCK, SLOW AS POSSIBLE)
|
|
; DIV 1280, 14KHZ @ 18MHZ CLK
|
|
|
|
#IF (BIOS == BIOS_WBW)
|
|
#IF (CPUFAM == CPU_Z180)
|
|
Z180_CNTR_DEF .EQU $06 ; DEFAULT VALUE FOR Z180 CSIO CONFIG
|
|
#ENDIF
|
|
#ENDIF
|
|
|
|
;
|
|
; HELPER MACROS
|
|
;
|
|
#DEFINE PRTC(C) CALL PRTCH \ .DB C ; PRINT CHARACTER C TO CONSOLE - PRTC('X')
|
|
#DEFINE PRTS(S) CALL PRTSTRD \ .TEXT S ; PRINT STRING S TO CONSOLE - PRTD("HELLO")
|
|
#DEFINE PRTX(X) CALL PRTSTRI \ .DW X ; PRINT STRING AT ADDRESS X TO CONSOLE - PRTI(STR_HELLO)
|
|
#DEFINE DEBUG(S) CALL PRTSTRD \ .TEXT S \ .TEXT "$" ; $$$$$$ PRINT STRING S TO CONSOLE - PRTD("HELLO") - NO TRAILING $ REQUIRED
|
|
;
|
|
#DEFINE XIO_PRTC(C) CALL XIO_PRTCH \ .DB C ; PRINT CHARACTER C TO CONSOLE - PRTC('X')
|
|
#DEFINE XIO_PRTS(S) CALL XIO_PRTSTRD \ .DB S ; PRINT STRING S TO CONSOLE - PRTD("HELLO")
|
|
#DEFINE XIO_PRTX(X) CALL XIO_PRTSTRI \ .DW X ; PRINT STRING AT ADDRESS X TO CONSOLE - PRTI(STR_HELLO)
|