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89 lines
2.2 KiB
89 lines
2.2 KiB
;
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;=======================================================================
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; HDIAG ASCI Driver
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;=======================================================================
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;
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; ASCI0 is programmed with a fixed divisor of 480, resulting in a
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; baud rate of 38400 at the standard cpu frequency of 18.432 MHz
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;
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; The Z180 may relocate it's internal I/O to begin at different
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; starting port addresses. This driver relies upon an HDIAG global
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; variable to dynamically adjust to the right port address.
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;
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;
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asci_jptbl:
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jp asci_cinit ; Initialize serial port
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jp asci_cin ; Read byte
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jp asci_cout ; Write byte
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jp asci_cist ; Input status
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jp asci_cost ; Output Status
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;
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;
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;
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asci_cinit:
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; Detect ASCI
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ld a,(hd_cpu) ; get cpu type
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cp hd_cpu_z180
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jr c, asci_cinit1 ; less than Z180, abort
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cp hd_cpu_z280
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jr nc, asci_cinit1 ; greater than Z180, abort
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;
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; Initialize ASCI
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ld a,%01100100 ; rcv enable, xmit enable, no parity
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out0 (z180_cntla0),a ; set cntla
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ld a,%00100000 ; div 30, div 16, div 1 (38400 baud for 18.432mhz cpu)
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out0 (z180_cntlb0),a ; set cntlb
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ld a,%01100110 ; no cts, no dcd, no break detect
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out0 (z180_asext0),a ; set asext
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xor a ; no interrupts
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out0 (z180_stat0),a ; set stat0
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xor a ; signal success
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ret ; done
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;
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asci_cinit1:
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or $FF ; signal error
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ret ; done
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;
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;
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;
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asci_cin:
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call asci_cist ; check for char ready
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jr z,asci_cin ; if not, loop
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in0 a,(z180_rdr0) ; get char
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ret ; done
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;
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;
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;
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asci_cout:
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push af ; save incoming
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asci_cout1:
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call asci_cost ; ready for char?
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jr z,asci_cout1 ; loop if not
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pop af ; restore incoming
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out0 (z180_tdr0),a ; write byte
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ret ; and done
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;
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;
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;
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asci_cist:
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in0 a,(z180_stat0) ; get status
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push af ; save status
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and $70 ; line error?
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jr z,asci_cist1 ; continue if no errors
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;
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; clear line error(s) or nothing further can be received!!!
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in0 a,(z180_cntla0) ; read cntla
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res 3,a ; clear efr (error flag reset)
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out0 (z180_cntla0),a ; update cntla
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;
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asci_cist1:
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pop af ; recover original status
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and $80 ; data ready?
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ret
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;
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;
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;
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asci_cost:
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in0 a,(z180_stat0) ; get status
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and $02 ; isolate bit 5
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ret ; a != 0 if char ready, else 0
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