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311 lines
16 KiB
311 lines
16 KiB
;
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;==================================================================================================
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; ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: Z80RETRO
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;==================================================================================================
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;
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; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
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; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD,
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; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN
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; THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
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;
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; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. IT IS MAINTAINED BY THE
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; AUTHORS OF ROMWBW. TO OVERRIDE SETTINGS YOU SHOULD USE A
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; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
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;
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; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
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;
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; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
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; |
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; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
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; |
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; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
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; |
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; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
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;
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; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
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; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
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; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
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; OVERRIDE THESE SETTINGS AS DESIRED.
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;
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; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
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; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
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; MODIFIED. TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE
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; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
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; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
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; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
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;
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; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
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; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
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; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
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;
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; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
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; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
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; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
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;
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#DEFINE PLATFORM_NAME "Z80Retro", " [", CONFIG, "]"
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;
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#INCLUDE "cfg_MASTER.asm"
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;
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PLATFORM .SET PLT_Z80RETRO ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
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CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
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BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
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BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
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HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
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USELZSA2 .SET TRUE ; ENABLE FONT COMPRESSION
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TICKFREQ .SET 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
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;
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BOOT_TIMEOUT .SET -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
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BOOT_DELAY .SET 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
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AUTOCON .SET TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
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;
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CPUSPDCAP .SET SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
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CPUSPDDEF .SET SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
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CPUOSC .SET 14745600 ; CPU OSC FREQ IN MHZ
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INTMODE .SET 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
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DEFSERCFG .SET SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
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;
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RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
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ROMSIZE .SET 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
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APP_BNKS .SET $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
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MEMMGR .SET MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
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MPGSEL_0 .SET $60 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
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MPGSEL_1 .SET $61 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
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MPGSEL_2 .SET $62 ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
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MPGSEL_3 .SET $63 ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
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MPGENA .SET $64 ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
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;
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RTCIO .SET $70 ; RTC LATCH REGISTER ADR
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;
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KIOENABLE .SET FALSE ; ENABLE ZILOG KIO SUPPORT
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KIOBASE .SET $80 ; KIO BASE I/O ADDRESS
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;
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CTCENABLE .SET TRUE ; ENABLE ZILOG CTC SUPPORT
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CTCDEBUG .SET FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT
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CTCBASE .SET $40 ; CTC BASE I/O ADDRESS
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CTCTIMER .SET FALSE ; ENABLE CTC PERIODIC TIMER (too fast for RomWBW right now)
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CTCMODE .SET CTCMODE_CTR ; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
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CTCPRE .SET 256 ; PRESCALE CONSTANT (1-256)
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CTCPRECH .SET 0 ; PRESCALE CHANNEL (0-3)
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CTCTIMCH .SET 1 ; TIMER CHANNEL (0-3)
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CTCOSC .SET 7372800 ; CTC CLOCK FREQUENCY
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;
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PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER
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PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS
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;
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EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
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;
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SKZENABLE .SET FALSE ; ENABLE SERGEY'S Z80-512K FEATURES
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;
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WDOGMODE .SET WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
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;
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FPLED_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL LEDS
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FPLED_IO .SET $00 ; FP: PORT ADDRESS FOR FP LEDS
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FPLED_INV .SET FALSE ; FP: LED BITS ARE INVERTED
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FPLED_DSKACT .SET TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
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FPSW_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL SWITCHES
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FPSW_IO .SET $00 ; FP: PORT ADDRESS FOR FP SWITCHES
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FPSW_INV .SET FALSE ; FP: SWITCH BITS ARE INVERTED
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;
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DIAGLVL .SET DL_CRITICAL ; ERROR LEVEL REPORTING
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;
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LEDENABLE .SET FALSE ; ENABLES STATUS LED (SINGLE LED)
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LEDMODE .SET LEDMODE_RTC ; LEDMODE_[STD|SC|RTC|NABU]
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LEDPORT .SET $00 ; STATUS LED PORT ADDRESS
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LEDDISKIO .SET TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED
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;
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DSKYENABLE .SET FALSE ; ENABLES DSKY FUNCTIONALITY
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DSKYDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY
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ICMENABLE .SET FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
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ICMPPIBASE .SET $60 ; BASE I/O ADDRESS OF ICM PPI
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PKDENABLE .SET FALSE ; ENABLES DSKY NG PKD DRIVER (8259)
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PKDPPIBASE .SET $60 ; BASE I/O ADDRESS OF PKD PPI
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PKDOSC .SET 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ)
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H8PENABLE .SET FALSE ; ENABLES HEATH H8 FRONT PANEL
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LCDENABLE .SET FALSE ; ENABLE LCD DISPLAY
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LCDBASE .SET $DA ; BASE I/O ADDRESS OF LCD CONTROLLER
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GM7303ENABLE .SET FALSE ; ENABLES THE GM7303 BOARD WITH 16X2 LCD
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;
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BOOTCON .SET 0 ; BOOT CONSOLE DEVICE
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SECCON .SET $FF ; SECONDARY CONSOLE DEVICE
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CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
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VDAEMU .SET EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI]
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VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
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ANSITRACE .SET 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
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PPKTRACE .SET 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
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KBDTRACE .SET 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
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PPKKBLOUT .SET KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
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KBDKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
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MKYKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
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;
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DSRTCENABLE .SET FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
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DSRTCMODE .SET DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTCMODE_[STD|MFPIC|K80W]
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DSRTCCHG .SET FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
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;
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DS1501RTCENABLE .SET FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
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DS1501RTC_BASE .SET $50 ; DS1501RTC: I/O BASE ADDRESS
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;
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BQRTCENABLE .SET FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
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BQRTC_BASE .SET $50 ; BQRTC: I/O BASE ADDRESS
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;
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INTRTCENABLE .SET FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
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;
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RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
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;
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HTIMENABLE .SET FALSE ; ENABLE SIMH TIMER SUPPORT
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SIMRTCENABLE .SET FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
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;
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DS7RTCENABLE .SET FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
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DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
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;
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DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
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;
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SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
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SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
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SSERSTATUS .SET $FF ; SSER: STATUS PORT
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SSERDATA .SET $FF ; SSER: DATA PORT
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SSERIRDY .SET %00000001 ; SSER: INPUT READY BIT MASK
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SSERIINV .SET FALSE ; SSER: INPUT READY BIT INVERTED
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SSERORDY .SET %00000010 ; SSER: OUTPUT READY BIT MASK
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SSEROINV .SET FALSE ; SSER: OUTPUT READY BIT INVERTED
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;
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DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
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;
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UARTENABLE .SET FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
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UARTCNT .SET 1 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
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UARTOSC .SET 1843200 ; UART: OSC FREQUENCY IN MHZ
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UARTINTS .SET FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
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UART4UART .SET FALSE ; UART: SUPPORT 4UART ECB BOARD
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UART4UARTBASE .SET $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
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UART0BASE .SET $FF ; UART 0: REGISTERS BASE ADR
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UART0CFG .SET DEFSERCFG ; UART 0: SERIAL LINE CONFIG
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UART1BASE .SET $FF ; UART 1: REGISTERS BASE ADR
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UART1CFG .SET DEFSERCFG ; UART 1: SERIAL LINE CONFIG
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UART2BASE .SET $FF ; UART 2: REGISTERS BASE ADR
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UART2CFG .SET DEFSERCFG ; UART 2: SERIAL LINE CONFIG
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UART3BASE .SET $FF ; UART 3: REGISTERS BASE ADR
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UART3CFG .SET DEFSERCFG ; UART 3: SERIAL LINE CONFIG
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UART4BASE .SET $FF ; UART 4: REGISTERS BASE ADR
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UART4CFG .SET DEFSERCFG ; UART 4: SERIAL LINE CONFIG
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UART5BASE .SET $FF ; UART 5: REGISTERS BASE ADR
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UART5CFG .SET DEFSERCFG ; UART 5: SERIAL LINE CONFIG
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UART6BASE .SET $FF ; UART 6: REGISTERS BASE ADR
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UART6CFG .SET DEFSERCFG ; UART 6: SERIAL LINE CONFIG
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UART7BASE .SET $FF ; UART 7: REGISTERS BASE ADR
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UART7CFG .SET DEFSERCFG ; UART 7: SERIAL LINE CONFIG
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;
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ASCIENABLE .SET FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
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;
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Z2UENABLE .SET FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
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;
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ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
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;
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SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
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SIODEBUG .SET FALSE ; SIO: ENABLE DEBUG OUTPUT
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SIOBOOT .SET 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
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SIOCNT .SET 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
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SIOINTS .SET TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
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SIO0MODE .SET SIOMODE_Z80R ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
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SIO0BASE .SET $80 ; SIO 0: REGISTERS BASE ADR
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SIO0ACLK .SET CPUOSC/2 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
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SIO0ACFG .SET DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG
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SIO0ACTCC .SET -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
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SIO0BCLK .SET CPUOSC/2 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
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SIO0BCFG .SET DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG
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SIO0BCTCC .SET -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
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SIO1MODE .SET SIOMODE_Z80R ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
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SIO1BASE .SET $84 ; SIO 1: REGISTERS BASE ADR
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SIO1ACLK .SET CPUOSC/2 ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
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SIO1ACFG .SET DEFSERCFG ; SIO 1A: SERIAL LINE CONFIG
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SIO1ACTCC .SET -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
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SIO1BCLK .SET CPUOSC/2 ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
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SIO1BCFG .SET DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG
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SIO1BCTCC .SET -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
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;
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XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG
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;
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VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
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CVDUENABLE .SET FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
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GDCENABLE .SET FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
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TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
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TMSMODE .SET TMSMODE_NONE ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
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TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
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TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
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VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
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VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
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SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
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EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
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FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
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;
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MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
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MDROM .SET TRUE ; MD: ENABLE ROM DISK
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MDRAM .SET TRUE ; MD: ENABLE RAM DISK
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MDTRACE .SET 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
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MDFFENABLE .SET FALSE ; MD: ENABLE FLASH FILE SYSTEM
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;
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FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
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FDMODE .SET FDMODE_ZETA2 ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
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FDCNT .SET 1 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
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FDTRACE .SET 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
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FDMAUTO .SET TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
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FD0TYPE .SET FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
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FD1TYPE .SET FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
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;
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RFENABLE .SET FALSE ; RF: ENABLE RAM FLOPPY DRIVER
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;
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IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
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;
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PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
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PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
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PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
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PPIDE0BASE .SET $60 ; PPIDE 0: PPI REGISTERS BASE ADR
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PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
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PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
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;
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SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
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SDMODE .SET SDMODE_Z80R ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM]
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SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
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SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
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SDCSIOFAST .SET FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
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SDMTSWAP .SET FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
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;
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CHENABLE .SET FALSE ; CH: ENABLE CH375/376 USB SUPPORT
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;
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PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
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;
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PPPENABLE .SET FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
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PPPBASE .SET $60 ; PPP: PPI REGISTERS BASE ADDRESS
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PPPSDENABLE .SET TRUE ; PPP: ENABLE PPP DRIVER SD CARD SUPPORT
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PPPSDTRACE .SET 1 ; PPP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
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PPPCONENABLE .SET TRUE ; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT
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;
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ESPENABLE .SET FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
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;
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HDSKENABLE .SET FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
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;
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PIOENABLE .SET FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
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;
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LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
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;
|
|
PPAENABLE .SET FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
|
|
;
|
|
IMMENABLE .SET FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
|
|
;
|
|
SYQENABLE .SET FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
|
|
;
|
|
PIO_4P .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
|
|
PIO_ZP .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
|
|
PIO_SBC .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
|
|
PIOSBASE .SET $60 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI
|
|
;
|
|
UFENABLE .SET FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
|
|
;
|
|
SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER
|
|
AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
|
|
SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
|
|
;
|
|
DMAENABLE .SET FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
|
|
DMABASE .SET $E0 ; DMA: DMA BASE ADDRESS
|
|
DMAMODE .SET DMAMODE_NONE ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
|
|
;
|
|
YM2612ENABLE .SET FALSE ; YM2612: ENABLE YM2612 DRIVER
|
|
VGMBASE .SET $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
|
|
|