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131 lines
5.0 KiB
131 lines
5.0 KiB
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; N8 HARDWARE DEFINITIONS
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;
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#IF (Z180_CLKDIV == 0)
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CPUKHZ .EQU CPUOSC / 2 ; OSCILLATOR FREQ / 2
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#ENDIF
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#IF (Z180_CLKDIV == 1)
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CPUKHZ .EQU CPUOSC ; OSCILLATOR FREQ
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#ENDIF
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#IF (Z180_CLKDIV == 2)
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CPUKHZ .EQU CPUOSC * 2 ; OSCILLATOR FREQ * 2
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#ENDIF
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;
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CPUMHZ .EQU CPUKHZ / 1000 ; CPU FREQ IN KHZ
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;
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CPU_BASE .EQU $40 ; ONLY RELEVANT FOR Z180
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;
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RAMBIAS .EQU 0 ; RAM STARTS AT 0K
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;
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N8_BASE .EQU $80 ; CPU INTERNAL I/O REGISTER BASE (AFTER RELOCATION)
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;
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PPIBASE .EQU N8_BASE + $00
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PPIA .EQU PPIBASE + 0 ; PORT A
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PPIB .EQU PPIBASE + 1 ; PORT B
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PPIC .EQU PPIBASE + 2 ; PORT C
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PPIX .EQU PPIBASE + 3 ; PPI CONTROL PORT
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;
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PPI2BASE .EQU N8_BASE + $04
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PPI2A .EQU PPI2BASE + 0 ; PORT A
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PPI2B .EQU PPI2BASE + 1 ; PORT B
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PPI2C .EQU PPI2BASE + 2 ; PORT C
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PPI2X .EQU PPI2BASE + 3 ; PPI CONTROL PORT
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;
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RTC: .EQU N8_BASE + $08 ; RTC LATCH AND BUFFER
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;FDC: .EQU N8_BASE + $0C ; FLOPPY DISK CONTROLLER
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;UTIL: .EQU N8_BASE + $10 ; FLOPPY DISK UTILITY
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ACR: .EQU N8_BASE + $14 ; AUXILLARY CONTROL REGISTER
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RMAP: .EQU N8_BASE + $16 ; ROM PAGE REGISTER
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VDP: .EQU N8_BASE + $18 ; VIDEO DISPLAY PROCESSOR (TMS9918A)
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PSG: .EQU N8_BASE + $1C ; PROGRAMMABLE SOUND GENERATOR (AY-3-8910)
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;
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DEFACR .EQU $1B
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;
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; MEMORY BANK CONFIGURATION
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;
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BID_ROM0 .EQU $00
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BID_ROMN .EQU (BID_ROM0 + ((ROMSIZE / 32) - 1))
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BID_RAM0 .EQU $80
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BID_RAMN .EQU (BID_RAM0 + ((RAMSIZE / 32) - 1))
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BID_BOOT .EQU BID_ROM0 ; BOOT BANK
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BID_BIOSIMG .EQU BID_ROM0 + 1 ; BIOS IMAGE BANK
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BID_OSIMG .EQU BID_ROM0 + 2 ; ROM LOADER AND IMAGES BANK
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BID_FSFAT .EQU BID_ROM0 + 3 ; FAT FILESYSTEM DRIVER BANK
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BID_ROMD0 .EQU BID_ROM0 + 4 ; FIRST ROM DRIVE BANK
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BID_ROMDN .EQU BID_ROMN ; LAST ROM DRIVE BANK
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BID_RAMD0 .EQU BID_RAM0 ; FIRST RAM DRIVE BANK
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BID_RAMDN .EQU BID_RAMN - 4 ; LAST RAM DRIVE BANK
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BID_AUX .EQU BID_RAMN - 3 ; AUX BANK (BPBIOS, ETC.)
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BID_BIOS .EQU BID_RAMN - 2 ; BIOS BANK
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BID_USR .EQU BID_RAMN - 1 ; USER BANK (CP/M TPA, ETC.)
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BID_COM .EQU BID_RAMN ; COMMON BANK, UPPER 32K
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;
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; Z180 REGISTERS
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;
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CPU_CNTLA0 .EQU CPU_BASE + $00 ; ASCI0 CONTROL A
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CPU_CNTLA1 .EQU CPU_BASE + $01 ; ASCI1 CONTROL A
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CPU_CNTLB0 .EQU CPU_BASE + $02 ; ASCI0 CONTROL B
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CPU_CNTLB1 .EQU CPU_BASE + $03 ; ASCI1 CONTROL B
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CPU_STAT0 .EQU CPU_BASE + $04 ; ASCI0 STATUS
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CPU_STAT1 .EQU CPU_BASE + $05 ; ASCI1 STATUS
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CPU_TDR0 .EQU CPU_BASE + $06 ; ASCI0 TRANSMIT
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CPU_TDR1 .EQU CPU_BASE + $07 ; ASCI1 TRANSMIT
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CPU_RDR0 .EQU CPU_BASE + $08 ; ASCI0 RECEIVE
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CPU_RDR1 .EQU CPU_BASE + $09 ; ASCI1 RECEIVE
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CPU_CNTR .EQU CPU_BASE + $0A ; CSI/O CONTROL
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CPU_TRDR .EQU CPU_BASE + $0B ; CSI/O TRANSMIT/RECEIVE
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CPU_TMDR0L .EQU CPU_BASE + $0C ; TIMER 0 DATA LO
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CPU_TMDR0H .EQU CPU_BASE + $0D ; TIMER 0 DATA HI
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CPU_RLDR0L .EQU CPU_BASE + $0E ; TIMER 0 RELOAD LO
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CPU_RLDR0H .EQU CPU_BASE + $0F ; TIMER 0 RELOAD HI
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CPU_TCR .EQU CPU_BASE + $10 ; TIMER CONTROL
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;
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CPU_ASEXT0 .EQU CPU_BASE + $12 ; ASCI0 EXTENSION CONTROL (Z8S180)
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CPU_ASEXT1 .EQU CPU_BASE + $13 ; ASCI1 EXTENSION CONTROL (Z8S180)
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;
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CPU_TMDR1L .EQU CPU_BASE + $14 ; TIMER 1 DATA LO
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CPU_TMDR1H .EQU CPU_BASE + $15 ; TIMER 1 DATA HI
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CPU_RLDR1L .EQU CPU_BASE + $16 ; TIMER 1 RELOAD LO
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CPU_RLDR1H .EQU CPU_BASE + $17 ; TIMER 1 RELOAD HI
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CPU_FRC .EQU CPU_BASE + $18 ; FREE RUNNING COUNTER
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CPU_ASTC0L .EQU CPU_BASE + $1A ; ASCI0 TIME CONSTANT LO (Z8S180)
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CPU_ASTC0H .EQU CPU_BASE + $1B ; ASCI0 TIME CONSTANT HI (Z8S180)
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CPU_ASTC1L .EQU CPU_BASE + $1C ; ASCI1 TIME CONSTANT LO (Z8S180)
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CPU_ASTC1H .EQU CPU_BASE + $1D ; ASCI1 TIME CONSTANT HI (Z8S180)
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CPU_CMR .EQU CPU_BASE + $1E ; CLOCK MULTIPLIER (LATEST Z8S180)
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CPU_CCR .EQU CPU_BASE + $1F ; CPU CONTROL (Z8S180)
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;
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CPU_SAR0L .EQU CPU_BASE + $20 ; DMA0 SOURCE ADDR LO
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CPU_SAR0H .EQU CPU_BASE + $21 ; DMA0 SOURCE ADDR HI
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CPU_SAR0B .EQU CPU_BASE + $22 ; DMA0 SOURCE ADDR BANK
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CPU_DAR0L .EQU CPU_BASE + $23 ; DMA0 DEST ADDR LO
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CPU_DAR0H .EQU CPU_BASE + $24 ; DMA0 DEST ADDR HI
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CPU_DAR0B .EQU CPU_BASE + $25 ; DMA0 DEST ADDR BANK
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CPU_BCR0L .EQU CPU_BASE + $26 ; DMA0 BYTE COUNT LO
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CPU_BCR0H .EQU CPU_BASE + $27 ; DMA0 BYTE COUNT HI
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CPU_MAR1L .EQU CPU_BASE + $28 ; DMA1 MEMORY ADDR LO
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CPU_MAR1H .EQU CPU_BASE + $29 ; DMA1 MEMORY ADDR HI
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CPU_MAR1B .EQU CPU_BASE + $2A ; DMA1 MEMORY ADDR BANK
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CPU_IAR1L .EQU CPU_BASE + $2B ; DMA1 I/O ADDR LO
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CPU_IAR1H .EQU CPU_BASE + $2C ; DMA1 I/O ADDR HI
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CPU_IAR1B .EQU CPU_BASE + $2D ; DMA1 I/O ADDR BANK (Z8S180)
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CPU_BCR1L .EQU CPU_BASE + $2E ; DMA1 BYTE COUNT LO
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CPU_BCR1H .EQU CPU_BASE + $2F ; DMA1 BYTE COUNT HI
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CPU_DSTAT .EQU CPU_BASE + $30 ; DMA STATUS
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CPU_DMODE .EQU CPU_BASE + $31 ; DMA MODE
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CPU_DCNTL .EQU CPU_BASE + $32 ; DMA/WAIT CONTROL
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CPU_IL .EQU CPU_BASE + $33 ; INTERRUPT VECTOR LOAD
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CPU_ITC .EQU CPU_BASE + $34 ; INT/TRAP CONTROL
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;
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CPU_RCR .EQU CPU_BASE + $36 ; REFRESH CONTROL
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;
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CPU_CBR .EQU CPU_BASE + $38 ; MMU COMMON BASE REGISTER
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CPU_BBR .EQU CPU_BASE + $39 ; MMU BANK BASE REGISTER
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CPU_CBAR .EQU CPU_BASE + $3A ; MMU COMMON/BANK AREA REGISTER
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;
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CPU_OMCR .EQU CPU_BASE + $3E ; OPERATION MODE CONTROL
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CPU_ICR .EQU $3F ; I/O CONTROL REGISTER (NOT RELOCATED!!!)
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