forked from MirrorRepos/RomWBW
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77 lines
3.3 KiB
77 lines
3.3 KiB
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; Z180 REGISTERS
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Z180_CNTLA0 .EQU Z180_BASE + $00 ; ASCI0 CONTROL A
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Z180_CNTLA1 .EQU Z180_BASE + $01 ; ASCI1 CONTROL A
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Z180_CNTLB0 .EQU Z180_BASE + $02 ; ASCI0 CONTROL B
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Z180_CNTLB1 .EQU Z180_BASE + $03 ; ASCI1 CONTROL B
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Z180_STAT0 .EQU Z180_BASE + $04 ; ASCI0 STATUS
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Z180_STAT1 .EQU Z180_BASE + $05 ; ASCI1 STATUS
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Z180_TDR0 .EQU Z180_BASE + $06 ; ASCI0 TRANSMIT
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Z180_TDR1 .EQU Z180_BASE + $07 ; ASCI1 TRANSMIT
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Z180_RDR0 .EQU Z180_BASE + $08 ; ASCI0 RECEIVE
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Z180_RDR1 .EQU Z180_BASE + $09 ; ASCI1 RECEIVE
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Z180_CNTR .EQU Z180_BASE + $0A ; CSI/O CONTROL
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Z180_TRDR .EQU Z180_BASE + $0B ; CSI/O TRANSMIT/RECEIVE
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Z180_TMDR0L .EQU Z180_BASE + $0C ; TIMER 0 DATA LO
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Z180_TMDR0H .EQU Z180_BASE + $0D ; TIMER 0 DATA HI
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Z180_RLDR0L .EQU Z180_BASE + $0E ; TIMER 0 RELOAD LO
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Z180_RLDR0H .EQU Z180_BASE + $0F ; TIMER 0 RELOAD HI
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Z180_TCR .EQU Z180_BASE + $10 ; TIMER CONTROL
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;
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Z180_ASEXT0 .EQU Z180_BASE + $12 ; ASCI0 EXTENSION CONTROL (Z8S180)
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Z180_ASEXT1 .EQU Z180_BASE + $13 ; ASCI1 EXTENSION CONTROL (Z8S180)
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Z180_TMDR1L .EQU Z180_BASE + $14 ; TIMER 1 DATA LO
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Z180_TMDR1H .EQU Z180_BASE + $15 ; TIMER 1 DATA HI
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Z180_RLDR1L .EQU Z180_BASE + $16 ; TIMER 1 RELOAD LO
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Z180_RLDR1H .EQU Z180_BASE + $17 ; TIMER 1 RELOAD HI
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Z180_FRC .EQU Z180_BASE + $18 ; FREE RUNNING COUNTER
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Z180_ASTC0L .EQU Z180_BASE + $1A ; ASCI0 TIME CONSTANT LO (Z8S180)
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Z180_ASTC0H .EQU Z180_BASE + $1B ; ASCI0 TIME CONSTANT HI (Z8S180)
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Z180_ASTC1L .EQU Z180_BASE + $1C ; ASCI1 TIME CONSTANT LO (Z8S180)
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Z180_ASTC1H .EQU Z180_BASE + $1D ; ASCI1 TIME CONSTANT HI (Z8S180)
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Z180_CMR .EQU Z180_BASE + $1E ; CLOCK MULTIPLIER (LATEST Z8S180)
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Z180_CCR .EQU Z180_BASE + $1F ; CPU CONTROL (Z8S180)
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;
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Z180_SAR0L .EQU Z180_BASE + $20 ; DMA0 SOURCE ADDR LO
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Z180_SAR0H .EQU Z180_BASE + $21 ; DMA0 SOURCE ADDR HI
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Z180_SAR0B .EQU Z180_BASE + $22 ; DMA0 SOURCE ADDR BANK
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Z180_DAR0L .EQU Z180_BASE + $23 ; DMA0 DEST ADDR LO
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Z180_DAR0H .EQU Z180_BASE + $24 ; DMA0 DEST ADDR HI
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Z180_DAR0B .EQU Z180_BASE + $25 ; DMA0 DEST ADDR BANK
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Z180_BCR0L .EQU Z180_BASE + $26 ; DMA0 BYTE COUNT LO
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Z180_BCR0H .EQU Z180_BASE + $27 ; DMA0 BYTE COUNT HI
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Z180_MAR1L .EQU Z180_BASE + $28 ; DMA1 MEMORY ADDR LO
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Z180_MAR1H .EQU Z180_BASE + $29 ; DMA1 MEMORY ADDR HI
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Z180_MAR1B .EQU Z180_BASE + $2A ; DMA1 MEMORY ADDR BANK
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Z180_IAR1L .EQU Z180_BASE + $2B ; DMA1 I/O ADDR LO
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Z180_IAR1H .EQU Z180_BASE + $2C ; DMA1 I/O ADDR HI
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Z180_IAR1B .EQU Z180_BASE + $2D ; DMA1 I/O ADDR BANK (Z8S180)
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Z180_BCR1L .EQU Z180_BASE + $2E ; DMA1 BYTE COUNT LO
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Z180_BCR1H .EQU Z180_BASE + $2F ; DMA1 BYTE COUNT HI
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Z180_DSTAT .EQU Z180_BASE + $30 ; DMA STATUS
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Z180_DMODE .EQU Z180_BASE + $31 ; DMA MODE
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Z180_DCNTL .EQU Z180_BASE + $32 ; DMA/WAIT CONTROL
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Z180_IL .EQU Z180_BASE + $33 ; INTERRUPT VECTOR LOAD
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Z180_ITC .EQU Z180_BASE + $34 ; INT/TRAP CONTROL
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Z180_RCR .EQU Z180_BASE + $36 ; REFRESH CONTROL
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;
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Z180_CBR .EQU Z180_BASE + $38 ; MMU COMMON BASE REGISTER
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Z180_BBR .EQU Z180_BASE + $39 ; MMU BANK BASE REGISTER
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Z180_CBAR .EQU Z180_BASE + $3A ; MMU COMMON/BANK AREA REGISTER
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;
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Z180_OMCR .EQU Z180_BASE + $3E ; OPERATION MODE CONTROL
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Z180_ICR .EQU $3F ; I/O CONTROL REGISTER (NOT RELOCATED!!!)
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Z180_IVINT1 .EQU 0
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Z180_IVINT2 .EQU 2
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Z180_IVTIM0 .EQU 4
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Z180_IVTIM1 .EQU 6
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Z180_IVDMA0 .EQU 8
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Z180_IVDMA1 .EQU 10
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Z180_IVCSIO .EQU 12
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Z180_IVSER0 .EQU 14
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Z180_IVSER1 .EQU 16
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