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Z280 Work in Progress, SC140 Config

- Early support for native mode memory for Z280.
- Added support for SC140 as new standard build.
pull/199/head
Wayne Warthen 5 years ago
parent
commit
10d875ffbb
  1. 2
      Source/CBIOS/config.asm
  2. 49
      Source/HBIOS/Config/RCZ280_nat.asm
  3. 56
      Source/HBIOS/Config/SCZ180_140.asm
  4. 2
      Source/HBIOS/Makefile
  5. 8
      Source/HBIOS/dbgmon.asm
  6. 222
      Source/HBIOS/hbios.asm
  7. 5
      Source/HBIOS/std.asm
  8. 10
      Source/HBIOS/z280.inc
  9. 2
      Source/ver.inc
  10. 2
      Source/ver.lib

2
Source/CBIOS/config.asm

@ -8,7 +8,7 @@ DSKTRACE .EQU FALSE ; ENABLE TRACING OF CBIOS DISK FUNCTION CALLS
CPM_LOC .EQU $D000 ; LOCATION OF START OF CCP CPM_LOC .EQU $D000 ; LOCATION OF START OF CCP
; ;
#IFDEF PLTWBW #IFDEF PLTWBW
CPM_END .EQU $FE00 ; ROMWBW HBIOS PROXY OCCUPIES TOP 2 PAGES OF MEMORY
CPM_END .EQU $FD80 ; ROMWBW HBIOS PROXY OCCUPIES TOP $280 BYTES OF MEMORY
#ENDIF #ENDIF
; ;
#IFDEF PLTUNA #IFDEF PLTUNA

49
Source/HBIOS/Config/RCZ280_nat.asm

@ -0,0 +1,49 @@
;
;==================================================================================================
; RC2014 Z280 STANDARD CONFIGURATION (EXTERNAL 512K RAM/ROM BANKED MEMORY MODULE)
;==================================================================================================
;
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
; YOUR FILE IN THE BUILD PROCESS.
;
; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
; SETTINGS.
;
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
;
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
; DIRECTORIES ABOVE THIS ONE).
;
#define BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
;
#include "cfg_rcz280.asm"
;
CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
;
CPUOSC .SET 24000000 ; CPU OSC FREQ IN MHZ
;
MEMMGR .SET MM_Z280 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
;
INTMODE .SET 1
;
Z280_MEMWAIT .SET 0 ; Z280: MEMORY WAIT STATES (0-3)
Z280_IOWAIT .SET 1 ; Z280: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
Z280_INTWAIT .SET 0 ; Z280: INT ACK WAIT STATUS (0-3)
;
UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
ACIAENABLE .SET TRUE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
;
IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
;
PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
;
PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)

56
Source/HBIOS/Config/SCZ180_140.asm

@ -0,0 +1,56 @@
;
;==================================================================================================
; SC140 STANDARD CONFIGURATION
;==================================================================================================
;
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
; YOUR FILE IN THE BUILD PROCESS.
;
; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
; SETTINGS.
;
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
;
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
; DIRECTORIES ABOVE THIS ONE).
;
#DEFINE PLATFORM_NAME "SC140"
;
#include "cfg_scz180.asm"
;
CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ
;
Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3)
Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
;
HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
;
LEDENABLE .SET TRUE ; ENABLE STATUS LED (SINGLE LED)
;
DIAGENABLE .SET TRUE ; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
;
DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
;
ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
;
ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
;
SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
;
FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|DIDE|N8|DIO3]
;
IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
;
PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
;
SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)

2
Source/HBIOS/Makefile

@ -13,6 +13,7 @@ else
OBJECTS += RCZ180_ext.rom RCZ180_ext.com RCZ180_ext.upd OBJECTS += RCZ180_ext.rom RCZ180_ext.com RCZ180_ext.upd
OBJECTS += RCZ180_nat.rom RCZ180_nat.com RCZ180_nat.upd OBJECTS += RCZ180_nat.rom RCZ180_nat.com RCZ180_nat.upd
OBJECTS += RCZ280_ext.rom RCZ280_ext.com RCZ280_ext.upd OBJECTS += RCZ280_ext.rom RCZ280_ext.com RCZ280_ext.upd
OBJECTS += RCZ280_nat.rom RCZ280_nat.com RCZ280_nat.upd
OBJECTS += RCZ80_kio.rom RCZ80_kio.com RCZ80_kio.upd OBJECTS += RCZ80_kio.rom RCZ80_kio.com RCZ80_kio.upd
OBJECTS += RCZ80_mt.rom RCZ80_mt.com RCZ80_mt.upd OBJECTS += RCZ80_mt.rom RCZ80_mt.com RCZ80_mt.upd
OBJECTS += RCZ80_duart.rom RCZ80_duart.com RCZ80_duart.upd OBJECTS += RCZ80_duart.rom RCZ80_duart.com RCZ80_duart.upd
@ -23,6 +24,7 @@ else
OBJECTS += SCZ180_126.rom SCZ180_126.com SCZ180_126.upd OBJECTS += SCZ180_126.rom SCZ180_126.com SCZ180_126.upd
OBJECTS += SCZ180_130.rom SCZ180_130.com SCZ180_130.upd OBJECTS += SCZ180_130.rom SCZ180_130.com SCZ180_130.upd
OBJECTS += SCZ180_131.rom SCZ180_131.com SCZ180_131.upd OBJECTS += SCZ180_131.rom SCZ180_131.com SCZ180_131.upd
OBJECTS += SCZ180_140.rom SCZ180_140.com SCZ180_140.upd
OBJECTS += UNA_std.rom OBJECTS += UNA_std.rom
OBJECTS += ZETA_std.rom ZETA_std.com ZETA_std.upd OBJECTS += ZETA_std.rom ZETA_std.com ZETA_std.upd
OBJECTS += ZETA2_std.rom ZETA2_std.com ZETA2_std.upd OBJECTS += ZETA2_std.rom ZETA2_std.com ZETA2_std.upd

8
Source/HBIOS/dbgmon.asm

@ -1412,12 +1412,12 @@ MON_STACK .EQU $
.ECHO SLACK .ECHO SLACK
.ECHO " bytes.\n" .ECHO " bytes.\n"
; ;
; DBGMON CURRENTLY OCCUPIES $F000-$FDFF BECAUSE THE
; HBIOS PROXY OCCUPIES $FE00-$FFFF. HOWEVER THE DBGMON
; DBGMON CURRENTLY OCCUPIES $F000 TO START OF HBX PROXY BECAUSE THE
; HBIOS PROXY OCCUPIES THE TOP OF COMMON RAM. HOWEVER THE DBGMON
; IMAGE MUST OCCUPY A FULL $1000 BYTES IN THE ROM. ; IMAGE MUST OCCUPY A FULL $1000 BYTES IN THE ROM.
; BELOW WE JUST PAD OUT THE IMAGE BY $200 SO IT
; BELOW WE JUST PAD OUT THE IMAGE SO IT
; OCCUPIES THE FULL $1000 BYTES IN ROM. ; OCCUPIES THE FULL $1000 BYTES IN ROM.
; ;
.FILL $200,$00
.FILL HBX_SIZ ; PAD FOR HBX SIZE
; ;
.END .END

222
Source/HBIOS/hbios.asm

@ -247,6 +247,91 @@ CB_BIDROMDN .DB BID_ROMDN
; ;
.FILL (HBX_IMG - $) ; FILL TO START OF PROXY IMAGE START .FILL (HBX_IMG - $) ; FILL TO START OF PROXY IMAGE START
.ORG HBX_LOC ; ADJUST FOR RELOCATION .ORG HBX_LOC ; ADJUST FOR RELOCATION
;
; Z280 BANK SELECTION (CALLED FROM PROXY)
;
#IF (MEMMGR == MM_Z280)
;
Z280_BNKSEL:
PUSH HL
PUSH DE
PUSH BC
LD L,$FF ; MMU PAGE I/O REG IS $FF
LD C,8 ; REG C POINTS TO I/O PAGE REGISTER
.DB $ED,$6E ; OP CODE FOR LDCTL (C),HL
LD E,0 ; DE IS TEMPLATE
BIT 7,A
JR Z,MMU_ROM ; TO ROM ROUTINE IF BIT 7 IS ZERO
RES 7,A
RR A ; EXTRACT THE LSB
PUSH AF ; SAVE THE CONDITION FLAG
OR $08 ; RAM BASE IS $080000
LD D,A ; REG D CONTAINS THE HIGH BYTE TEMPLATE
POP AF
JR C,W_MMU1
JR W_MMU0
MMU_ROM:
OR A ; CLEAR THE CARRY FLAG
RR A ; EXTRACT THE LSB
LD D,A ; REG D CONTAINS THE HIGH BYTE TEMPLATE
JR C,W_MMU1
W_MMU0:
LD A,$10 ; SYSTEM PAGE
OUT (Z280_MMUPDRPTR),A
LD C,Z280_MMUBLKMOV ; ACCESS BLOCK MOVE PORT SO POINTER WILL AUTOINCREM
LD H,D ; GET TEMPLATE INTO HL
LD L,$0A ; LOWEST 4K OF MEMORY
.DB $ED,$BF ; OUTW (C),HL
LD L,$1A ; MODIFY THE TEMPLATE FOR NEXT 4K
.DB $ED,$BF ; OUTW (C),HL
LD L,$2A ; MODIFY THE TEMPLATE FOR NEXT 4K
.DB $ED,$BF ; OUTW (C),HL
LD L,$3A ; MODIFY THE TEMPLATE FOR NEXT 4K
.DB $ED,$BF ; OUTW (C),HL
LD L,$4A ; MODIFY THE TEMPLATE FOR NEXT 4K
.DB $ED,$BF ; OUTW (C),HL
LD L,$5A ; MODIFY THE TEMPLATE FOR NEXT 4K
.DB $ED,$BF ; OUTW (C),HL
LD L,$6A ; MODIFY THE TEMPLATE FOR NEXT 4K
.DB $ED,$BF ; OUTW (C),HL
LD L,$7A ; MODIFY THE TEMPLATE FOR NEXT 4K
.DB $ED,$BF ; OUTW (C),HL
JR W_MMU2
W_MMU1:
LD A,$10 ; SYSTEM PAGE
OUT (Z280_MMUPDRPTR),A
LD C,Z280_MMUBLKMOV ; ACCESS BLOCK MOVE PORT SO POINTER WILL AUTOINCREM
LD H,D ; GET TEMPLATE INTO HL
LD L,$8A ; LOWEST 4K OF MEMORY
.DB $ED,$BF ; OUTW (C),HL
LD L,$9A ; MODIFY THE TEMPLATE FOR NEXT 4K
.DB $ED,$BF ; OUTW (C),HL
LD L,$AA ; MODIFY THE TEMPLATE FOR NEXT 4K
.DB $ED,$BF ; OUTW (C),HL
LD L,$BA ; MODIFY THE TEMPLATE FOR NEXT 4K
.DB $ED,$BF ; OUTW (C),HL
LD L,$CA ; MODIFY THE TEMPLATE FOR NEXT 4K
.DB $ED,$BF ; OUTW (C),HL
LD L,$DA ; MODIFY THE TEMPLATE FOR NEXT 4K
.DB $ED,$BF ; OUTW (C),HL
LD L,$EA ; MODIFY THE TEMPLATE FOR NEXT 4K
.DB $ED,$BF ; OUTW (C),HL
LD L,$FA ; MODIFY THE TEMPLATE FOR NEXT 4K
.DB $ED,$BF ; OUTW (C),HL
W_MMU2:
.DB $ED,$65 ; PCACHE
LD L,0 ; RESTORE I/O PAGE REG TO 0
LD C,8
.DB $ED,$6E ; LDCTL (C),HL
POP BC
POP DE
POP HL
RET
;
#ENDIF
;
.FILL ($FE00 - $)
; ;
; MEMORY LAYOUT: ; MEMORY LAYOUT:
; ;
@ -373,8 +458,7 @@ HBX_ROM:
INC A ; INC A ;
OUT (MPGSEL_1),A ; BANK_1: 16K - 32K OUT (MPGSEL_1),A ; BANK_1: 16K - 32K
#IF (CPUFAM == CPU_Z280) #IF (CPUFAM == CPU_Z280)
;PCACHE ; PURGE CACHES
.DB $ED,$65
.DB $ED,$65 ; PCACHE
#ENDIF #ENDIF
RET ; DONE RET ; DONE
#ENDIF #ENDIF
@ -412,8 +496,7 @@ HBX_BNKSEL1:
RET ; DONE RET ; DONE
#ENDIF #ENDIF
#IF (MEMMGR == MM_Z280) #IF (MEMMGR == MM_Z280)
; TBD
RET ; DONE
JP Z280_BNKSEL ; DO THE REAL WORK
#ENDIF #ENDIF
#IF (MEMMGR == MM_ZRC) #IF (MEMMGR == MM_ZRC)
BIT 7,A ; BIT 7 SET REQUESTS RAM PAGE BIT 7,A ; BIT 7 SET REQUESTS RAM PAGE
@ -444,10 +527,8 @@ HBX_BNKCPY:
#IF (CPUFAM == CPU_Z280) #IF (CPUFAM == CPU_Z280)
PUSH IY PUSH IY
PUSH BC PUSH BC
;LD C,$00
LD C,Z280_MSR LD C,Z280_MSR
;LDCTL IY,(C)
.DB $FD,$ED,$66
.DB $FD,$ED,$66 ; LDCTL IY,(C)
POP BC POP BC
PUSH IY PUSH IY
DI DI
@ -489,8 +570,7 @@ HBX_BC_SP .EQU $ - 2 ; ... TO ORIGINAL VALUE
POP IY POP IY
PUSH BC PUSH BC
LD C,Z280_MSR LD C,Z280_MSR
;LDCTL (C),IY
.DB $FD,$ED,$6E
.DB $FD,$ED,$6E ; LDCTL (C),IY
POP BC POP BC
POP IY POP IY
#ELSE #ELSE
@ -769,7 +849,7 @@ HB_ENTRYTBL .EQU $
JP HB_START ; HBIOS INITIALIZATION JP HB_START ; HBIOS INITIALIZATION
JP HB_DISPATCH ; VECTOR TO DISPATCHER JP HB_DISPATCH ; VECTOR TO DISPATCHER
; ;
HB_STKSIZ .EQU HB_ENTRYTBL + 256 - $
HB_STKSIZ .EQU $100 - ($ & $FF)
; ;
.FILL HB_STKSIZ,$FF ; USE REMAINDER OF PAGE FOR HBIOS STACK .FILL HB_STKSIZ,$FF ; USE REMAINDER OF PAGE FOR HBIOS STACK
HB_STACK .EQU $ ; TOP OF HBIOS STACK HB_STACK .EQU $ ; TOP OF HBIOS STACK
@ -857,18 +937,79 @@ HB_START:
LD SP,HBX_LOC ; SETUP INITIAL STACK JUST BELOW HBIOS PROXY LD SP,HBX_LOC ; SETUP INITIAL STACK JUST BELOW HBIOS PROXY
; ;
#IF (CPUFAM == CPU_Z280) #IF (CPUFAM == CPU_Z280)
;LD C,Z280_CCR ; CACHE CONTROL REGISTER
;LD HL,$0060 ; DISABLE INSTRUCTION CACHE
;;LDCTL (C),HL ; SET IT (8 BITS)
;.DB $ED,$6E
;;PCACHE ; PURGE ANY REMNANTS OF CACHE
;.DB $ED,$65
;
; SET MAXIMUM I/O WAIT STATES FOR NOW
LD C,Z280_BTCR ; BUS TIMING AND CONTROL REGISTER LD C,Z280_BTCR ; BUS TIMING AND CONTROL REGISTER
LD HL,$0033 ; 3 I/O WAIT STATES ADDED LD HL,$0033 ; 3 I/O WAIT STATES ADDED
;LD HL,$00F3 ; 3 I/O W/S & 3 INT ACK W/S
;LDCTL (C),HL ; SET IT (8 BITS)
.DB $ED,$6E
.DB $ED,$6E ; LDCTL (C),HL
#IF (MEMMGR == MM_Z280)
; INITIALIZE MMU
; START BY SELECTING I/O PAGE $FF
LD L,$FF ; MMU AND DMA PAGE I/O REG IS $FF
LD C,$08 ; REG C POINTS TO I/O PAGE REGISTER
.DB $ED,$6E ; LDCTL (C),HL
;
; INITIALIZE ALL OF THE SYSTEM PAGE DESCRIPTORS WITH BLOCK MOVE
XOR A ; FIRST USER PDR
OUT (Z280_MMUPDRPTR),A ; SET THE PDR POINTER
LD HL,Z280_PDRTBL ; START OF PDR VALUES TABLE
LD C,Z280_MMUBLKMOV ; PDR BLOCK MOVE PORT
LD B,16 ; PROGRAM 16 PDRS
.DB $ED,$93 ; OTIRW
;
; INITIALIZE ALL OF THE USER PAGE DESCRIPTORS WITH BLOCK MOVE
LD A,$10 ; FIRST SYSTEM PDR
OUT (Z280_MMUPDRPTR),A ; SET THE PDR POINTER
LD HL,Z280_PDRTBL ; START OF PDR VALUES TABLE
LD C,Z280_MMUBLKMOV ; PDR BLOCK MOVE PORT
LD B,16 ; PROGRAM 16 PDRS
.DB $ED,$93 ; OTIRW
;
; ENABLE MMU (SYSTEM AND USER TRANSLATION)
LD C,Z280_MMUMCR ; MMU MASTER CONTROL REGISTER
LD HL,$BBFF ; ENABLE USER & SYSTEM TRANSLATE
.DB $ED,$BF ; OUTW (C),HL
;
; RESTORE I/O PAGE TO $00
LD L,$00 ; NORMAL I/O REG IS $00
LD C,$08 ; REG C POINTS TO I/O PAGE REGISTER
.DB $ED,$6E ; LDCTL (C),HL
;;
; ; COPY Z280 BANK SELECTION CODE TO $FD80
; LD HL,Z280_BNKSEL ; SOURCE
; LD DE,$FD80 ; DESTINATION
; LD BC,Z280_BNKSELZ-Z280_BNKSEL ; BYTE COUNT TO COPY
; LDIR ; COPY
;
DIAG(%11111110)
; JP XZ280_BNKSELZ ; JUMP TO CODE CONTINUATION
JR Z280_INITZ ; JUMP TO CODE CONTINUATION
;
Z280_PDRTBL:
; LOWER 32 K (BANKED)
.DW ($000 << 4) | $A
.DW ($001 << 4) | $A
.DW ($002 << 4) | $A
.DW ($003 << 4) | $A
.DW ($004 << 4) | $A
.DW ($005 << 4) | $A
.DW ($006 << 4) | $A
.DW ($007 << 4) | $A
; UPPER 32 K (COMMON)
.DW ($0F8 << 4) | $A
.DW ($0F9 << 4) | $A
.DW ($0FA << 4) | $A
.DW ($0FB << 4) | $A
.DW ($0FC << 4) | $A
.DW ($0FD << 4) | $A
.DW ($0FE << 4) | $A
.DW ($0FF << 4) | $A
;
Z280_INITZ:
;
#ENDIF
;
#ENDIF #ENDIF
; ;
#IF (CPUFAM == CPU_Z180) #IF (CPUFAM == CPU_Z180)
@ -1270,25 +1411,21 @@ HB_CPU2:
#IF (CPUFAM == CPU_Z280) #IF (CPUFAM == CPU_Z280)
; ;
LD C,Z280_BTCR ; BUS TIMING AND CONTROL REG LD C,Z280_BTCR ; BUS TIMING AND CONTROL REG
;LDCTL HL,(C) ; GET IT
.DB $ED,$66
.DB $ED,$66 ; LDCTL HL,(C)
LD A,L ; PUT IN A LD A,L ; PUT IN A
AND %00111100 ; CLEAR DC AND I/O FIELDS AND %00111100 ; CLEAR DC AND I/O FIELDS
OR Z280_INTWAIT << 6 ; SET INT ACK WAIT STATES OR Z280_INTWAIT << 6 ; SET INT ACK WAIT STATES
OR Z280_IOWAIT ; SET I/O WAIT STATES OR Z280_IOWAIT ; SET I/O WAIT STATES
LD L,A ; BACK TO L LD L,A ; BACK TO L
;LDCTL (C),HL ; SET IT
.DB $ED,$6E
.DB $ED,$6E ; LDCTL (C),HL
; ;
LD C,Z280_BTIR ; BUS TIMING AND INIT REG LD C,Z280_BTIR ; BUS TIMING AND INIT REG
;LDCTL HL,(C) ; GET IT
.DB $ED,$66
.DB $ED,$66 ; LDCTL HL,(C)
LD A,L ; PUT IN A LD A,L ; PUT IN A
AND %11110011 ; CLEAR DC AND I/O FIELDS AND %11110011 ; CLEAR DC AND I/O FIELDS
OR Z280_MEMWAIT << 2 ; SET LOW MEM WAIT STATES OR Z280_MEMWAIT << 2 ; SET LOW MEM WAIT STATES
LD L,A ; BACK TO L LD L,A ; BACK TO L
;LDCTL (C),HL ; SET IT
.DB $ED,$6E
.DB $ED,$6E ; LDCTL (C),HL
; ;
#ENDIF #ENDIF
; ;
@ -1555,8 +1692,7 @@ HB_SPDTST:
CALL PRTSTRD CALL PRTSTRD
.TEXT ", BUS @ $" .TEXT ", BUS @ $"
LD C,Z280_BTIR ; BUS TIMING AND CTL REG LD C,Z280_BTIR ; BUS TIMING AND CTL REG
;LDCTL HL,(C) ; GET IT
.DB $ED,$66
.DB $ED,$66 ; LDCTL HL,(C)
LD A,L ; MOVE TO A LD A,L ; MOVE TO A
AND %00000011 ; ISOLATE CS FIELD AND %00000011 ; ISOLATE CS FIELD
LD HL,(CB_CPUKHZ) ; GET CPU SPEED LD HL,(CB_CPUKHZ) ; GET CPU SPEED
@ -1634,26 +1770,22 @@ HB_Z280BUS1:
PRTS("Z280: $") PRTS("Z280: $")
PRTS("MSR=$") PRTS("MSR=$")
LD C,Z280_MSR ; MASTER STATUS REGISTER LD C,Z280_MSR ; MASTER STATUS REGISTER
;LDTCL HL,(C) ; GET VALUE
.DB $ED,$66
.DB $ED,$66 ; LDCTL HL,(C)
CALL PRTHEXWORDHL CALL PRTHEXWORDHL
CALL PC_SPACE CALL PC_SPACE
PRTS("BTCR=$") PRTS("BTCR=$")
LD C,Z280_BTCR ; BUS TIMING AND CONTROL REGISTER LD C,Z280_BTCR ; BUS TIMING AND CONTROL REGISTER
;LDTCL HL,(C) ; GET VALUE
.DB $ED,$66
.DB $ED,$66 ; LDTCL HL,(C)
CALL PRTHEXWORDHL CALL PRTHEXWORDHL
CALL PC_SPACE CALL PC_SPACE
PRTS("BTIR=$") PRTS("BTIR=$")
LD C,Z280_BTIR ; BUS TIMING AND CONTROL REGISTER LD C,Z280_BTIR ; BUS TIMING AND CONTROL REGISTER
;LDTCL HL,(C) ; GET VALUE
.DB $ED,$66
.DB $ED,$66 ; LDTCL HL,(C)
CALL PRTHEXWORDHL CALL PRTHEXWORDHL
CALL PC_SPACE CALL PC_SPACE
PRTS("CCR=$") PRTS("CCR=$")
LD C,Z280_CCR ; CACHE CONTROL REGISTER LD C,Z280_CCR ; CACHE CONTROL REGISTER
;LDTCL HL,(C) ; GET VALUE
.DB $ED,$66
.DB $ED,$66 ; LDTCL HL,(C)
CALL PRTHEXWORDHL CALL PRTHEXWORDHL
#ENDIF #ENDIF
; ;
@ -2953,10 +3085,8 @@ SYS_PEEK:
#IF (INTMODE == 1) #IF (INTMODE == 1)
#IF (CPUFAM == CPU_Z280) #IF (CPUFAM == CPU_Z280)
PUSH IY PUSH IY
;LD C,$00
LD C,Z280_MSR LD C,Z280_MSR
;LDCTL IY,(C)
.DB $FD,$ED,$66
.DB $FD,$ED,$66 ; LDCTL IY,(C)
PUSH IY PUSH IY
DI DI
#ELSE #ELSE
@ -2968,11 +3098,9 @@ SYS_PEEK:
CALL HBX_PEEK ; IMPLEMENTED IN PROXY CALL HBX_PEEK ; IMPLEMENTED IN PROXY
#IF (INTMODE == 1) #IF (INTMODE == 1)
#IF (CPUFAM == CPU_Z280) #IF (CPUFAM == CPU_Z280)
;LD C,$00
LD C,Z280_MSR LD C,Z280_MSR
POP IY POP IY
;LDCTL (C),IY
.DB $FD,$ED,$6E
.DB $FD,$ED,$6E ; LDCTL (C),IY
POP IY POP IY
#ELSE #ELSE
POP AF POP AF
@ -2995,8 +3123,7 @@ SYS_POKE:
#IF (CPUFAM == CPU_Z280) #IF (CPUFAM == CPU_Z280)
PUSH IY PUSH IY
LD C,Z280_MSR LD C,Z280_MSR
;LDCTL IY,(C)
.DB $FD,$ED,$66
.DB $FD,$ED,$66 ; LDCTL IY,(C)
PUSH IY PUSH IY
DI DI
#ELSE #ELSE
@ -3010,8 +3137,7 @@ SYS_POKE:
#IF (CPUFAM == CPU_Z280) #IF (CPUFAM == CPU_Z280)
LD C,Z280_MSR LD C,Z280_MSR
POP IY POP IY
;LDCTL (C),IY
.DB $FD,$ED,$6E
.DB $FD,$ED,$6E ; LDCTL (C),IY
POP IY POP IY
#ELSE #ELSE
POP AF POP AF

5
Source/HBIOS/std.asm

@ -443,7 +443,8 @@ BID_COM .EQU BID_RAMN ; COMMON BANK, UPPER 32K
; ;
SYS_SIZ .EQU $3000 ; COMBINED SIZE OF SYSTEM AREA (OS + HBIOS PROXY) SYS_SIZ .EQU $3000 ; COMBINED SIZE OF SYSTEM AREA (OS + HBIOS PROXY)
HBBUF_SIZ .EQU 1024 ; INVARIANT HBIOS PHYSICAL DISK BUFFER, 1K HBBUF_SIZ .EQU 1024 ; INVARIANT HBIOS PHYSICAL DISK BUFFER, 1K
HBX_SIZ .EQU $200 ; HBIOS PROXY SIZE (SUBJECT TO CHANGE)
;HBX_SIZ .EQU $200 ; HBIOS PROXY SIZE (SUBJECT TO CHANGE)
HBX_SIZ .EQU $200 + $80 ; HBIOS PROXY SIZE (TEMP)
CPM_SIZ .EQU SYS_SIZ - HBX_SIZ ; NET SIZE OF ALL OS COMPONENTS (EXCLUDING HBIOS PROXY) CPM_SIZ .EQU SYS_SIZ - HBX_SIZ ; NET SIZE OF ALL OS COMPONENTS (EXCLUDING HBIOS PROXY)
CCP_SIZ .EQU $800 ; INVARIANT SIZE OF CCP CCP_SIZ .EQU $800 ; INVARIANT SIZE OF CCP
BDOS_SIZ .EQU $E00 ; INVARIANT SIZE OF BDOS BDOS_SIZ .EQU $E00 ; INVARIANT SIZE OF BDOS
@ -468,7 +469,7 @@ CPM_ENT .EQU CBIOS_LOC ; CPM ENTRY POINT (IN CBIOS)
LDR_SIZ .EQU $0E00 LDR_SIZ .EQU $0E00
MON_LOC .EQU $F000 ; LOCATION OF MONITOR FOR RUNNING SYSTEM MON_LOC .EQU $F000 ; LOCATION OF MONITOR FOR RUNNING SYSTEM
MON_SIZ .EQU $0E00 ; SIZE OF MONITOR BINARY IMAGE
MON_SIZ .EQU $1000 - HBX_SIZ ; SIZE OF MONITOR BINARY IMAGE
MON_END .EQU MON_LOC + MON_SIZ ; END OF MONITOR MON_END .EQU MON_LOC + MON_SIZ ; END OF MONITOR
BAS_LOC .EQU $0200 ; NASCOM BASIC BAS_LOC .EQU $0200 ; NASCOM BASIC

10
Source/HBIOS/z280.inc

@ -1,5 +1,5 @@
; ;
; Z280 REGISTERS
; Z280 CPU CONTROL REGISTERS (VIA LDCTL)
; ;
Z280_MSR .EQU $00 ; MASTER STATUS REG Z280_MSR .EQU $00 ; MASTER STATUS REG
Z280_ISR .EQU $16 ; INTERRUPT STATUS REG Z280_ISR .EQU $16 ; INTERRUPT STATUS REG
@ -11,3 +11,11 @@ Z280_SLR .EQU $04 ; STACK LIMIT REG
Z280_TCR .EQU $10 ; TRAP CONTROL REG Z280_TCR .EQU $10 ; TRAP CONTROL REG
Z280_CCR .EQU $12 ; CACHE CONTROL REG Z280_CCR .EQU $12 ; CACHE CONTROL REG
Z280_LAR .EQU $14 ; LOCAL ADDRESS REG Z280_LAR .EQU $14 ; LOCAL ADDRESS REG
;
; Z280 MMU REGISTERS (I/O PAGE $FF, I/O ADDRESS $FF**NN)
;
Z280_MMUMCR .EQU $F0 ; Z280 MMU MASTER CONTROL REG
Z280_MMUPDRPTR .EQU $F1 ; Z280 MMU PDR POINTER REG
Z280_MMUINV .EQU $F2 ; Z280 MMU INVALIDATION PORT
Z280_MMUBLKMOV .EQU $F4 ; Z280 MMU BLOCK MOVE PORT
Z280_MMUPDR .EQU $F5 ; Z280 MMU PDR PORT

2
Source/ver.inc

@ -2,4 +2,4 @@
#DEFINE RMN 1 #DEFINE RMN 1
#DEFINE RUP 1 #DEFINE RUP 1
#DEFINE RTP 0 #DEFINE RTP 0
#DEFINE BIOSVER "3.1.1-pre.28"
#DEFINE BIOSVER "3.1.1-pre.29"

2
Source/ver.lib

@ -3,5 +3,5 @@ rmn equ 1
rup equ 1 rup equ 1
rtp equ 0 rtp equ 0
biosver macro biosver macro
db "3.1.1-pre.28"
db "3.1.1-pre.29"
endm endm

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