mirror of https://github.com/wwarthen/RomWBW.git
Dan Werner
2 months ago
44 changed files with 907 additions and 67 deletions
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; |
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;================================================================================================== |
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; ROMWBW DEFAULT BUILD SETTINGS FOR N8PC |
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;================================================================================================== |
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; |
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; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM |
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; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS |
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; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES. |
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; |
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; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: |
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; |
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; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS |
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; | |
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; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM |
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; | |
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; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD |
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; | |
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; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS |
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; |
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; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW |
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; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE |
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; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY |
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; OVERRIDE THESE SETTINGS AS DESIRED. |
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; |
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; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT |
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; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE |
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; MODIFIED. |
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; |
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; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE |
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; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY |
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; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT |
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; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). |
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; |
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; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE |
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; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST |
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; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. |
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; |
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; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE |
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; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE). |
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; |
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; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE |
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; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT |
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; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". |
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; |
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#DEFINE AUTO_CMD "" ; AUTO CMD WHEN BOOT_TIMEOUT IS ENABLED |
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#DEFINE DEFSERCFG SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL CONFIGURATION |
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; |
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#INCLUDE "cfg_N8PC.asm" |
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; |
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BOOT_TIMEOUT .SET -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE |
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BOOT_PRETTY .SET FALSE ; BOOT WITH PRETTY PLATFORM NAME |
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AUTOCON .SET TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT |
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; |
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CPUOSC .SET 9216000 ; CPU OSC FREQ IN MHZ |
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INTMODE .SET 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) |
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; |
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RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) |
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; |
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Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2 |
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Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3) |
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Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) |
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; |
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DSKYENABLE .SET FALSE ; ENABLES DSKY FUNCTIONALITY |
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ICMENABLE .SET FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218) |
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PKDENABLE .SET FALSE ; ENABLES DSKY NG PKD DRIVER (8259) |
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CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP |
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VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD |
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; |
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M6242RTCENABLE .SET TRUE ; M6242RTC: ENABLE M6242 CLOCK DRIVER (M6242.ASM) |
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; |
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UARTENABLE .SET FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) |
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ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) |
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; |
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TMSENABLE .SET TRUE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) |
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; |
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FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) |
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FDCNT .SET 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2) |
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FD0TYPE .SET FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] |
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FD1TYPE .SET FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] |
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; |
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PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) |
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; |
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PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) |
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; |
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PPPENABLE .SET FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) |
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; |
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AY38910ENABLE .SET TRUE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER |
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DSKYENABLE .SET TRUE ; ENABLES DSKY FUNCTIONALITY |
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PKDENABLE .SET TRUE ; ENABLES DSKY NG PKD DRIVER (8259) |
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PKDPPIBASE .SET N8_PPI0 ; BASE I/O ADDRESS OF PKD PPI |
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PKDOSC .SET 1000000 ; OSCILLATOR FREQ FOR PKD (IN HZ) |
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@ -0,0 +1,387 @@ |
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; |
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;================================================================================================== |
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; ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: N8PC |
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;================================================================================================== |
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; |
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; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM |
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; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, |
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; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN |
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; THE CONFIG DIRECTORY UNDER THIS DIRECTORY. |
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; |
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; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. IT IS MAINTAINED BY THE |
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; AUTHORS OF ROMWBW. TO OVERRIDE SETTINGS YOU SHOULD USE A |
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; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY. |
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; |
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; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: |
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; |
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; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS |
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; | |
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; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM |
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; | |
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; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD |
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; | |
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; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS |
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; |
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; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW |
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|
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE |
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|
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY |
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|
; OVERRIDE THESE SETTINGS AS DESIRED. |
||||
|
; |
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|
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT |
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|
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE |
||||
|
; MODIFIED. TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE |
||||
|
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY |
||||
|
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT |
||||
|
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). |
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|
; |
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|
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE |
||||
|
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST |
||||
|
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. |
||||
|
; |
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|
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE |
||||
|
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT |
||||
|
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". |
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; |
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#DEFINE PLATFORM_NAME "N8PC", " [", CONFIG, "]" ; TEXT LABEL OF THIS CONFIG IN STARTUP MESSAGES |
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#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD FOR EMPTY CMD LINE |
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#DEFINE AUTO_CMD "" ; AUTO CMD WHEN BOOT_TIMEOUT IS ENABLED |
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#DEFINE DEFSERCFG SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL CONFIGURATION |
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; |
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#INCLUDE "cfg_MASTER.asm" |
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; |
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PLATFORM .SET PLT_N8PC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC] |
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CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] |
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NMOSCPU .SET FALSE ; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND) |
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BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] |
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BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE |
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HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) |
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USELZSA2 .SET TRUE ; ENABLE FONT COMPRESSION |
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TICKFREQ .SET 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ) |
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; |
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BOOT_TIMEOUT .SET -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE |
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BOOT_DELAY .SET 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT |
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BOOT_PRETTY .SET FALSE ; BOOT WITH PRETTY PLATFORM NAME |
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BT_REC_TYPE .SET BT_REC_NONE ; BOOT RECOVERY METHOD TO USE: BT_REC_[NONE|FORCE|SBCB0|SBC1B|SBCRI|DUORI] |
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AUTOCON .SET TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT |
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STRICTPART .SET TRUE ; ENFORCE STRICT PARTITION TABLE VALIDATION |
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; |
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CPUSPDCAP .SET SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO |
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CPUSPDDEF .SET SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW |
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CPUOSC .SET 9216000 ; CPU OSC FREQ IN MHZ |
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INTMODE .SET 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) |
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; |
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RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) |
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ROMSIZE .SET 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) |
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ROMFONTS .SET TRUE ; LOAD FONTS FROM ROM |
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APP_BNKS .SET $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING) |
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MEMMGR .SET MM_N8 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON|EZ512] |
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RAMBIAS .SET 0 ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE |
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; |
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Z180_BASE .SET $40 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS |
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Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2 |
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Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3) |
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Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) |
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Z180_TIMER .SET TRUE ; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER |
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; |
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N8_PPI0 .SET $84 ; N8: FIRST PARALLEL PORT REGISTERS BASE ADR |
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N8_ACR .SET $94 ; N8: AUXILLARY CONTROL REGISTER (ACR) ADR |
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N8_RMAP .SET $96 ; N8: ROM PAGE REGISTER ADR |
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N8_DEFACR .SET $1B ; N8: AUX CTL REGISTER DEFAULT VALUE (QUIESCIENT STATE) |
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; |
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RTCIO .SET $88 ; RTC LATCH REGISTER ADR |
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; |
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KIOENABLE .SET FALSE ; ENABLE ZILOG KIO SUPPORT |
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KIOBASE .SET $80 ; KIO BASE I/O ADDRESS |
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; |
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CTCENABLE .SET FALSE ; ENABLE ZILOG CTC SUPPORT |
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CTCDEBUG .SET FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT |
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CTCBASE .SET $B0 ; CTC BASE I/O ADDRESS |
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CTCTIMER .SET FALSE ; ENABLE CTC PERIODIC TIMER |
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; |
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PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER |
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; |
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EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION |
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; |
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SKZENABLE .SET FALSE ; ENABLE SERGEY'S Z80-512K FEATURES |
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; |
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WDOGMODE .SET WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ] |
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; |
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FPLED_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL LEDS |
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FPLED_IO .SET $00 ; FP: PORT ADDRESS FOR FP LEDS |
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FPLED_INV .SET FALSE ; FP: LED BITS ARE INVERTED |
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FPLED_DSKACT .SET TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS |
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FPSW_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL SWITCHES |
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FPSW_IO .SET $00 ; FP: PORT ADDRESS FOR FP SWITCHES |
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FPSW_INV .SET FALSE ; FP: SWITCH BITS ARE INVERTED |
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; |
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DIAGLVL .SET DL_CRITICAL ; ERROR LEVEL REPORTING |
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; |
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LEDENABLE .SET TRUE ; ENABLES STATUS LED (SINGLE LED) |
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LEDMODE .SET LEDMODE_STD ; LEDMODE_[STD|SC|RTC|NABU] |
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LEDPORT .SET N8_ACR ; STATUS LED PORT ADDRESS |
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LEDDISKIO .SET TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED |
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; |
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DSKYENABLE .SET FALSE ; ENABLES DSKY FUNCTIONALITY |
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DSKYDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY |
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ICMENABLE .SET FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218) |
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ICMPPIBASE .SET N8_PPI0 ; BASE I/O ADDRESS OF ICM PPI |
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PKDENABLE .SET FALSE ; ENABLES DSKY NG PKD DRIVER (8259) |
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PKDPPIBASE .SET N8_PPI0 ; BASE I/O ADDRESS OF PKD PPI |
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PKDOSC .SET 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ) |
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H8PENABLE .SET FALSE ; ENABLES HEATH H8 FRONT PANEL |
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LCDENABLE .SET FALSE ; ENABLE LCD DISPLAY |
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LCDBASE .SET $DA ; BASE I/O ADDRESS OF LCD CONTROLLER |
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GM7303ENABLE .SET FALSE ; ENABLES THE GM7303 BOARD WITH 16X2 LCD |
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; |
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BOOTCON .SET 0 ; BOOT CONSOLE DEVICE |
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SECCON .SET $FF ; SECONDARY CONSOLE DEVICE |
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CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP |
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VDAEMU .SET EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI] |
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VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD |
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ANSITRACE .SET 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
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PPKTRACE .SET 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
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KBDTRACE .SET 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
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PPKKBLOUT .SET KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE] |
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KBDKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] |
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MKYKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] |
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KBDINTS .SET FALSE ; ENABLE KBD (PS2) KEYBOARD INTERRUPTS |
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; |
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DSRTCENABLE .SET FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) |
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DSRTCMODE .SET DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTCMODE_[STD|MFPIC|K80W] |
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DSRTCCHG .SET FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) |
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; |
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DS1501RTCENABLE .SET FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM) |
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DS1501RTC_BASE .SET $50 ; DS1501RTC: I/O BASE ADDRESS |
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; |
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BQRTCENABLE .SET FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM) |
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BQRTC_BASE .SET $50 ; BQRTC: I/O BASE ADDRESS |
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; |
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INTRTCENABLE .SET FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) |
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; |
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RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM) |
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; |
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HTIMENABLE .SET FALSE ; ENABLE SIMH TIMER SUPPORT |
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SIMRTCENABLE .SET FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) |
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; |
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DS7RTCENABLE .SET FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM) |
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DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTCMODE_[PCF] |
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; |
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DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM) |
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; |
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MMRTCENABLE .SET FALSE ; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM) |
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; |
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DS12RTCENABLE .SET FALSE ; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM) |
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; |
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M6242RTCENABLE .SET TRUE ; M6242RTC: ENABLE M6242 CLOCK DRIVER (M6242.ASM) |
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M6242RTC_BASE .SET $A0 ; M6242RTC: I/O BASE ADDRESS |
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; |
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SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM) |
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SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG |
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SSERSTATUS .SET $FF ; SSER: STATUS PORT |
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SSERDATA .SET $FF ; SSER: DATA PORT |
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SSERIRDY .SET %00000001 ; SSER: INPUT READY BIT MASK |
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SSERIINV .SET FALSE ; SSER: INPUT READY BIT INVERTED |
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SSERORDY .SET %00000010 ; SSER: OUTPUT READY BIT MASK |
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SSEROINV .SET FALSE ; SSER: OUTPUT READY BIT INVERTED |
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; |
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PLDSERENABLE .SET FALSE ; PLDSER: ENABLE PLD-USB SERIAL DRIVER (PLDSER.ASM) |
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PLDSERCFG .SET SER_9600_8N1 ; PLDSER: SERIAL LINE CONFIG |
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; |
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TSERENABLE .SET FALSE ; TSER: ENABLE T35 SERIAL DRIVER (TSER.ASM) |
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TSERCFG .SET SER_9600_8N1 ; TSER: SERIAL LINE CONFIG |
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; |
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DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) |
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; |
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UARTENABLE .SET FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) |
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UARTCNT .SET 5 ; UART: NUMBER OF CHIPS TO DETECT (1-8) |
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|
UARTOSC .SET 1843200 ; UART: OSC FREQUENCY IN MHZ |
||||
|
UARTINTS .SET FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 |
||||
|
UART4UART .SET TRUE ; UART: SUPPORT 4UART ECB BOARD |
||||
|
UART4UARTBASE .SET $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD |
||||
|
UART0BASE .SET $80 ; UART 0: REGISTERS BASE ADR |
||||
|
UART0CFG .SET DEFSERCFG ; UART 0: SERIAL LINE CONFIG |
||||
|
UART1BASE .SET $C0 ; UART 1: REGISTERS BASE ADR |
||||
|
UART1CFG .SET DEFSERCFG ; UART 1: SERIAL LINE CONFIG |
||||
|
UART2BASE .SET $C8 ; UART 2: REGISTERS BASE ADR |
||||
|
UART2CFG .SET DEFSERCFG ; UART 2: SERIAL LINE CONFIG |
||||
|
UART3BASE .SET $D0 ; UART 3: REGISTERS BASE ADR |
||||
|
UART3CFG .SET DEFSERCFG ; UART 3: SERIAL LINE CONFIG |
||||
|
UART4BASE .SET $D8 ; UART 4: REGISTERS BASE ADR |
||||
|
UART4CFG .SET DEFSERCFG ; UART 4: SERIAL LINE CONFIG |
||||
|
UART5BASE .SET $FF ; UART 5: REGISTERS BASE ADR |
||||
|
UART5CFG .SET DEFSERCFG ; UART 5: SERIAL LINE CONFIG |
||||
|
UART6BASE .SET $FF ; UART 6: REGISTERS BASE ADR |
||||
|
UART6CFG .SET DEFSERCFG ; UART 6: SERIAL LINE CONFIG |
||||
|
UART7BASE .SET $FF ; UART 7: REGISTERS BASE ADR |
||||
|
UART7CFG .SET DEFSERCFG ; UART 7: SERIAL LINE CONFIG |
||||
|
; |
||||
|
ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) |
||||
|
ASCIINTS .SET TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 |
||||
|
ASCISWAP .SET FALSE ; ASCI: SWAP CHANNELS |
||||
|
ASCIBOOT .SET 0 ; ASCI: REBOOT ON RCV CHAR (0=DISABLED) |
||||
|
ASCI0CFG .SET DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG |
||||
|
ASCI1CFG .SET DEFSERCFG ; ASCI 1: SERIAL LINE CONFIG |
||||
|
; |
||||
|
Z2UENABLE .SET FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) |
||||
|
; |
||||
|
ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) |
||||
|
; |
||||
|
SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) |
||||
|
SIODEBUG .SET FALSE ; SIO: ENABLE DEBUG OUTPUT |
||||
|
SIOBOOT .SET 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) |
||||
|
SIOCNT .SET 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP |
||||
|
SIOINTS .SET TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3 |
||||
|
SIO0MODE .SET SIOMODE_ZP ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] |
||||
|
SIO0BASE .SET $B0 ; SIO 0: REGISTERS BASE ADR |
||||
|
SIO0ACLK .SET (4915200/8) ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 |
||||
|
SIO0ACFG .SET DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG |
||||
|
SIO0ACTCC .SET -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE |
||||
|
SIO0BCLK .SET (4915200/8) ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 |
||||
|
SIO0BCFG .SET DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG |
||||
|
SIO0BCTCC .SET -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE |
||||
|
; |
||||
|
SCCENABLE .SET FALSE ; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM) |
||||
|
; |
||||
|
XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG |
||||
|
; |
||||
|
VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) |
||||
|
VDUSIZ .SET V80X25 ; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30] |
||||
|
CVDUENABLE .SET FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM) |
||||
|
CVDUMODE .SET CVDUMODE_ECB ; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC] |
||||
|
CVDUMON .SET CVDUMON_EGA ; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA] |
||||
|
GDCENABLE .SET FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM) |
||||
|
TMSENABLE .SET TRUE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) |
||||
|
TMSMODE .SET TMSMODE_N8PC ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU|N8PC] |
||||
|
TMS80COLS .SET TRUE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958 |
||||
|
TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) |
||||
|
VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) |
||||
|
VGASIZ .SET V80X25 ; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43] |
||||
|
VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) |
||||
|
SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) |
||||
|
EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) |
||||
|
TVGAENABLE .SET FALSE ; TVGA: ENABLE TRION VGA VIDEO DRIVER (TVGA.ASM) |
||||
|
; |
||||
|
MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) |
||||
|
MDROM .SET TRUE ; MD: ENABLE ROM DISK |
||||
|
MDRAM .SET TRUE ; MD: ENABLE RAM DISK |
||||
|
MDTRACE .SET 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
||||
|
MDFFENABLE .SET FALSE ; MD: ENABLE FLASH FILE SYSTEM |
||||
|
; |
||||
|
FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) |
||||
|
FDMODE .SET FDMODE_N8 ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] |
||||
|
FDCNT .SET 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2) |
||||
|
FDTRACE .SET 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL) |
||||
|
FDMAUTO .SET TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS |
||||
|
FD0TYPE .SET FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] |
||||
|
FD1TYPE .SET FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] |
||||
|
; |
||||
|
RFENABLE .SET FALSE ; RF: ENABLE RAM FLOPPY DRIVER |
||||
|
RFCNT .SET 1 ; RF: NUMBER OF RAM FLOPPY UNITS (1-4) |
||||
|
; |
||||
|
IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) |
||||
|
IDETRACE .SET 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
||||
|
IDECNT .SET 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH |
||||
|
IDE0MODE .SET IDEMODE_DIO ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] |
||||
|
IDE0BASE .SET $20 ; IDE 0: IO BASE ADDRESS |
||||
|
IDE0DATLO .SET $20 ; IDE 0: DATA LO PORT FOR 16-BIT I/O |
||||
|
IDE0DATHI .SET $28 ; IDE 0: DATA HI PORT FOR 16-BIT I/O |
||||
|
IDE0A8BIT .SET FALSE ; IDE 0A (MASTER): 8 BIT XFER |
||||
|
IDE0B8BIT .SET FALSE ; IDE 0B (MASTER): 8 BIT XFER |
||||
|
IDE1MODE .SET IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] |
||||
|
IDE1BASE .SET $00 ; IDE 1: IO BASE ADDRESS |
||||
|
IDE1DATLO .SET $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O |
||||
|
IDE1DATHI .SET $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O |
||||
|
IDE1A8BIT .SET TRUE ; IDE 1A (MASTER): 8 BIT XFER |
||||
|
IDE1B8BIT .SET TRUE ; IDE 1B (MASTER): 8 BIT XFER |
||||
|
IDE2MODE .SET IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] |
||||
|
IDE2BASE .SET $00 ; IDE 2: IO BASE ADDRESS |
||||
|
IDE2DATLO .SET $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O |
||||
|
IDE2DATHI .SET $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O |
||||
|
IDE2A8BIT .SET TRUE ; IDE 2A (MASTER): 8 BIT XFER |
||||
|
IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER |
||||
|
; |
||||
|
PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) |
||||
|
PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
||||
|
PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP |
||||
|
PPIDE0MODE .SET PPIDEMODE_STD ; PPIDE 0: DRIVER MODE: IDEMODE_[STD|S100A|S100B] |
||||
|
PPIDE0BASE .SET N8_PPI0 ; PPIDE 0: PPI REGISTERS BASE ADR |
||||
|
PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER |
||||
|
PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER |
||||
|
PPIDE1MODE .SET PPIDEMODE_STD ; PPIDE 1: DRIVER MODE: IDEMODE_[STD|S100A|S100B] |
||||
|
PPIDE1BASE .SET $00 ; PPIDE 1: PPI REGISTERS BASE ADR |
||||
|
PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER |
||||
|
PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER |
||||
|
PPIDE2MODE .SET PPIDEMODE_STD ; PPIDE 2: DRIVER MODE: IDEMODE_[STD|S100A|S100B] |
||||
|
PPIDE2BASE .SET $00 ; PPIDE 2: PPI REGISTERS BASE ADR |
||||
|
PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER |
||||
|
PPIDE2B8BIT .SET FALSE ; PPIDE 2B (SLAVE): 8 BIT XFER |
||||
|
; |
||||
|
SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) |
||||
|
SDMODE .SET SDMODE_CSIO ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|T35|GM|EZ512|K80W] |
||||
|
SDPPIBASE .SET N8_PPI0 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE |
||||
|
SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY |
||||
|
SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
||||
|
SDCSIOFAST .SET FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE |
||||
|
SDMTSWAP .SET FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011 |
||||
|
; |
||||
|
CHENABLE .SET FALSE ; CH: ENABLE CH375/376 USB SUPPORT |
||||
|
; |
||||
|
PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) |
||||
|
PRPSDENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT |
||||
|
PRPSDTRACE .SET 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
||||
|
PRPCONENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT |
||||
|
; |
||||
|
PPPENABLE .SET FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) |
||||
|
PPPBASE .SET N8_PPI0 ; PPP: PPI REGISTERS BASE ADDRESS |
||||
|
PPPSDENABLE .SET TRUE ; PPP: ENABLE PPP DRIVER SD CARD SUPPORT |
||||
|
PPPSDTRACE .SET 1 ; PPP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
||||
|
PPPCONENABLE .SET TRUE ; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT |
||||
|
; |
||||
|
ESPENABLE .SET FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM) |
||||
|
; |
||||
|
HDSKENABLE .SET FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) |
||||
|
; |
||||
|
PIOENABLE .SET FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM) |
||||
|
PIOCNT .SET 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP |
||||
|
PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR |
||||
|
PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR |
||||
|
; |
||||
|
LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) |
||||
|
; |
||||
|
PPAENABLE .SET FALSE ; PPA: ENABLE IOMEGA ZIP DRIVE (PPA) DISK DRIVER (PPA.ASM) |
||||
|
; |
||||
|
IMMENABLE .SET FALSE ; IMM: ENABLE IOMEGA ZIP PLUS DRIVE (IMM) DISK DRIVER (IMM.ASM) |
||||
|
; |
||||
|
SYQENABLE .SET FALSE ; SYQ: ENABLE SYQUEST SPARQ DISK DRIVER (SYQ.ASM) |
||||
|
; |
||||
|
ESPSDENABLE .SET FALSE ; ESPSD: ENABLE S100 ESP32 SD DISK DRIVER (ESPSD.ASM) |
||||
|
; |
||||
|
PIO_4P .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD |
||||
|
PIO4BASE .SET $90 ; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD |
||||
|
PIO_ZP .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) |
||||
|
PIOZBASE .SET $88 ; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD |
||||
|
PIO_SBC .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP |
||||
|
PIOSBASE .SET N8_PPI0 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI |
||||
|
; |
||||
|
UFENABLE .SET FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) |
||||
|
UFBASE .SET $0C ; UF: REGISTERS BASE ADR |
||||
|
; |
||||
|
SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER |
||||
|
SN76489CHNOUT .SET SNCHAN_BOTH ; SN: CHANNEL OUTPUTS: SNCHAN_[BOTH|LEFT|RIGHT] |
||||
|
AUDIOTRACE .SET FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER |
||||
|
SN7CLK .SET 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD |
||||
|
SNMODE .SET SNMODE_VGM ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO] |
||||
|
; |
||||
|
AY38910ENABLE .SET TRUE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER |
||||
|
AY_CLK .SET 3579545 ; AY: PSG CLOCK FREQ, ASSUME MSX STD |
||||
|
AYMODE .SET AYMODE_N8 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] |
||||
|
AY_FORCE .SET FALSE ; AY: BYPASS AUTO-DETECT, FORCED PRESENT |
||||
|
; |
||||
|
SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) |
||||
|
; |
||||
|
DMAENABLE .SET FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM) |
||||
|
DMABASE .SET $E0 ; DMA: DMA BASE ADDRESS |
||||
|
DMAMODE .SET DMAMODE_Z180 ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO) |
||||
|
; |
||||
|
YM2612ENABLE .SET FALSE ; YM2612: ENABLE YM2612 DRIVER |
||||
|
VGMBASE .SET $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC) |
||||
@ -0,0 +1,326 @@ |
|||||
|
; |
||||
|
;================================================================================================== |
||||
|
; M6242 CLOCK DRIVER |
||||
|
;================================================================================================== |
||||
|
; |
||||
|
M6242RTC_BUFSIZ .EQU 6 ; SIX BYTE BUFFER (YYMMDDHHMMSS) |
||||
|
; |
||||
|
; RTC DEVICE INITIALIZATION ENTRY |
||||
|
; |
||||
|
|
||||
|
; TODO: |
||||
|
; set the day of week register |
||||
|
|
||||
|
;; NOTES FOR USING DRIVER IN Z-DOS |
||||
|
; First load the LDDS datestamper |
||||
|
; A:LDDS |
||||
|
; next prepare and drives with datestamper info: |
||||
|
; eg: a:putds -d=g: -V |
||||
|
; then view date time of files with: |
||||
|
; a:filedate |
||||
|
|
||||
|
|
||||
|
REG_1SEC .EQU $00 |
||||
|
REG_10SEC .EQU $01 |
||||
|
REG_1MIN .EQU $02 |
||||
|
REG_10MIN .EQU $03 |
||||
|
REG_1HR .EQU $04 |
||||
|
REG_10HR .EQU $05 |
||||
|
REG_1DAY .EQU $06 |
||||
|
REG_10DAY .EQU $07 |
||||
|
REG_1MNTH .EQU $08 |
||||
|
REG_10MNTH .EQU $09 |
||||
|
REG_1YEAR .EQU $0A |
||||
|
REG_10YEAR .EQU $0B |
||||
|
REG_DAYWEEK .EQU $0C ; NOT USED BY THIS DRIVER |
||||
|
REG_CONTROL1 .EQU $0D |
||||
|
REG_CONTROL2 .EQU $0E |
||||
|
REG_CONTROL3 .EQU $0F |
||||
|
|
||||
|
.ECHO "M6242: IO=" |
||||
|
.ECHO M6242RTC_BASE |
||||
|
.ECHO "\n" |
||||
|
|
||||
|
M6242RTC_INIT: |
||||
|
LD A, (RTC_DISPACT) ; RTC DISPATCHER ALREADY SET? |
||||
|
OR A ; SET FLAGS |
||||
|
RET NZ ; IF ALREADY ACTIVE, ABORT |
||||
|
|
||||
|
CALL NEWLINE ; FORMATTING |
||||
|
PRTS("M6242 RTC: $") |
||||
|
|
||||
|
; PRINT RTC LATCH PORT ADDRESS |
||||
|
PRTS("IO=0x$") ; LABEL FOR IO ADDRESS |
||||
|
LD A,M6242RTC_BASE ; GET IO ADDRESS |
||||
|
CALL PRTHEXBYTE ; PRINT IT |
||||
|
CALL PC_SPACE ; FORMATTING |
||||
|
|
||||
|
; CHECK PRESENCE STATUS |
||||
|
CALL M6242RTC_DETECT ; HARDWARE DETECTION |
||||
|
JR Z, M6242RTC_INIT1 ; IF ZERO, ALL GOOD |
||||
|
PRTS("NOT PRESENT$") ; NOT ZERO, H/W NOT PRESENT |
||||
|
OR $FF ; SIGNAL FAILURE |
||||
|
RET ; BAIL OUT |
||||
|
|
||||
|
M6242RTC_INIT1: |
||||
|
; ENSURE DEVICE IS RESET AND NOT IN TEST MODE |
||||
|
LD A, 05h ; TURN OFF ALL TEST MODE BITS, SET 24 HOUR |
||||
|
OUT (REG_CONTROL3 + M6242RTC_BASE), A |
||||
|
LD A, 05h ; TURN OFF ALL TEST MODE BITS, SET 24 HOUR |
||||
|
OUT (REG_CONTROL3 + M6242RTC_BASE), A |
||||
|
LD A, 04h ; TURN OFF ALL TEST MODE BITS, SET 24 HOUR |
||||
|
OUT (REG_CONTROL3 + M6242RTC_BASE), A |
||||
|
|
||||
|
LD A, 00h ; LET CLOCK RUN |
||||
|
OUT (REG_CONTROL1 + M6242RTC_BASE), A |
||||
|
OUT (REG_CONTROL2 + M6242RTC_BASE), A |
||||
|
|
||||
|
; DISPLAY CURRENT TIME |
||||
|
LD HL, M6242RTC_BCDBUF ; POINT TO BCD BUF |
||||
|
CALL M6242RTC_GETTIM |
||||
|
CALL PRTDT |
||||
|
; |
||||
|
LD BC, M6242RTC_DISPATCH |
||||
|
CALL RTC_SETDISP |
||||
|
; |
||||
|
XOR A ; SIGNAL SUCCESS |
||||
|
RET |
||||
|
; |
||||
|
; DETECT RTC HARDWARE PRESENCE |
||||
|
; |
||||
|
M6242RTC_DETECT: |
||||
|
LD A, 01h ; TURN ON REST BIT |
||||
|
OUT (REG_CONTROL3 + M6242RTC_BASE), A |
||||
|
CALL DLY64 |
||||
|
CALL DLY64 |
||||
|
IN A,(REG_CONTROL3 + M6242RTC_BASE) |
||||
|
AND 01h |
||||
|
CP 01h |
||||
|
JR NZ, M6242RTC_DETECTERR ; IF NOT MATCH, ERROR |
||||
|
LD A, 00h ; TURN OFF REST BIT |
||||
|
OUT (REG_CONTROL3 + M6242RTC_BASE), A |
||||
|
CALL DLY64 |
||||
|
CALL DLY64 |
||||
|
IN A,(REG_CONTROL3 + M6242RTC_BASE) |
||||
|
AND 01h |
||||
|
CP 00h |
||||
|
JR NZ, M6242RTC_DETECTERR ; IF NOT MATCH, ERROR |
||||
|
LD A, 0 ; ASSUME OK |
||||
|
OR A ; SET FLAGS |
||||
|
RET |
||||
|
|
||||
|
M6242RTC_DETECTERR: |
||||
|
LD A, $FF ; ELSE STATUS IS ERROR |
||||
|
OR A ; SET FLAGS |
||||
|
RET |
||||
|
|
||||
|
; |
||||
|
; RTC DEVICE FUNCTION DISPATCH ENTRY |
||||
|
; A: RESULT (OUT), 0=OK, Z=OK, NZ=ERR |
||||
|
; B: FUNCTION (IN) |
||||
|
; |
||||
|
M6242RTC_DISPATCH: |
||||
|
LD A,B ; GET REQUESTED FUNCTION |
||||
|
AND $0F ; ISOLATE SUB-FUNCTION |
||||
|
JP Z,M6242RTC_GETTIM ; GET TIME |
||||
|
DEC A |
||||
|
JP Z,M6242RTC_SETTIM ; SET TIME |
||||
|
DEC A |
||||
|
JP Z,M6242RTC_GETBYT ; GET NVRAM BYTE VALUE |
||||
|
DEC A |
||||
|
JP Z,M6242RTC_SETBYT ; SET NVRAM BYTE VALUE |
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|
DEC A |
||||
|
JP Z,M6242RTC_GETBLK ; GET NVRAM DATA BLOCK VALUES |
||||
|
DEC A |
||||
|
JP Z,M6242RTC_SETBLK ; SET NVRAM DATA BLOCK VALUES |
||||
|
DEC A |
||||
|
JP Z,M6242RTC_GETALM ; GET ALARM |
||||
|
DEC A |
||||
|
JP Z,M6242RTC_SETALM ; SET ALARM |
||||
|
DEC A |
||||
|
JP Z,M6242RTC_DEVICE ; REPORT RTC DEVICE INFO |
||||
|
SYSCHKERR(ERR_NOFUNC) |
||||
|
RET |
||||
|
; |
||||
|
; RTC GET NVRAM BYTE |
||||
|
; C: INDEX |
||||
|
; E: VALUE (OUTPUT) |
||||
|
; A:0 IF OK, ERR_RANGE IF OUT OF RANGE |
||||
|
; |
||||
|
M6242RTC_GETBYT: |
||||
|
M6242RTC_SETBYT: |
||||
|
M6242RTC_GETBLK: |
||||
|
M6242RTC_SETBLK: |
||||
|
M6242RTC_GETALM: |
||||
|
M6242RTC_SETALM: |
||||
|
SYSCHKERR(ERR_NOTIMPL) |
||||
|
RET |
||||
|
; |
||||
|
; RTC GET TIME |
||||
|
; A: RESULT (OUT), 0=OK, Z=OK, NZ=ERR |
||||
|
; HL: DATE/TIME BUFFER (OUT) |
||||
|
; BUFFER FORMAT IS BCD: YYMMDDHHMMSS |
||||
|
; 24 HOUR TIME FORMAT IS ASSUMED |
||||
|
; |
||||
|
M6242RTC_GETTIM: |
||||
|
PUSH HL |
||||
|
PUSH BC |
||||
|
IN A,(REG_10YEAR + M6242RTC_BASE) |
||||
|
RLA |
||||
|
RLA |
||||
|
RLA |
||||
|
RLA |
||||
|
LD C,A |
||||
|
IN A,(REG_1YEAR + M6242RTC_BASE) |
||||
|
AND 0FH |
||||
|
OR C |
||||
|
LD (HL),A |
||||
|
INC HL |
||||
|
|
||||
|
IN A,(REG_10MNTH + M6242RTC_BASE) |
||||
|
RLA |
||||
|
RLA |
||||
|
RLA |
||||
|
RLA |
||||
|
LD C,A |
||||
|
IN A,(REG_1MNTH + M6242RTC_BASE) |
||||
|
AND 0FH |
||||
|
OR C |
||||
|
LD (HL),A |
||||
|
INC HL |
||||
|
|
||||
|
IN A,(REG_10DAY + M6242RTC_BASE) |
||||
|
RLA |
||||
|
RLA |
||||
|
RLA |
||||
|
RLA |
||||
|
LD C,A |
||||
|
IN A,(REG_1DAY + M6242RTC_BASE) |
||||
|
AND 0FH |
||||
|
OR C |
||||
|
LD (HL),A |
||||
|
INC HL |
||||
|
|
||||
|
IN A,(REG_10HR + M6242RTC_BASE) |
||||
|
RLA |
||||
|
RLA |
||||
|
RLA |
||||
|
RLA |
||||
|
LD C,A |
||||
|
IN A,(REG_1HR + M6242RTC_BASE) |
||||
|
AND 0FH |
||||
|
OR C |
||||
|
LD (HL),A |
||||
|
INC HL |
||||
|
|
||||
|
IN A,(REG_10MIN + M6242RTC_BASE) |
||||
|
RLA |
||||
|
RLA |
||||
|
RLA |
||||
|
RLA |
||||
|
LD C,A |
||||
|
IN A,(REG_1MIN + M6242RTC_BASE) |
||||
|
AND 0FH |
||||
|
OR C |
||||
|
LD (HL),A |
||||
|
INC HL |
||||
|
|
||||
|
IN A,(REG_10SEC + M6242RTC_BASE) |
||||
|
RLA |
||||
|
RLA |
||||
|
RLA |
||||
|
RLA |
||||
|
LD C,A |
||||
|
IN A,(REG_1SEC + M6242RTC_BASE) |
||||
|
AND 0FH |
||||
|
OR C |
||||
|
LD (HL),A |
||||
|
INC HL |
||||
|
|
||||
|
POP BC |
||||
|
POP HL |
||||
|
XOR A ; SIGNAL SUCCESS |
||||
|
RET ; AND RETURN |
||||
|
; |
||||
|
; |
||||
|
; RTC SET TIME |
||||
|
; A: RESULT (OUT), 0=OK, Z=OK, NZ=ERR |
||||
|
; HL: DATE/TIME BUFFER (IN) |
||||
|
; BUFFER FORMAT IS BCD: YYMMDDHHMMSSWW |
||||
|
; 24 HOUR TIME FORMAT IS ASSUMED |
||||
|
; |
||||
|
M6242RTC_SETTIM: |
||||
|
PUSH HL |
||||
|
LD A, (HL) |
||||
|
OUT (REG_1YEAR + M6242RTC_BASE), A |
||||
|
RRA |
||||
|
RRA |
||||
|
RRA |
||||
|
RRA |
||||
|
OUT (REG_10YEAR + M6242RTC_BASE), A |
||||
|
|
||||
|
INC HL |
||||
|
LD A, (HL) |
||||
|
OUT (REG_1MNTH + M6242RTC_BASE), A |
||||
|
RRA |
||||
|
RRA |
||||
|
RRA |
||||
|
RRA |
||||
|
OUT (REG_10MNTH + M6242RTC_BASE), A |
||||
|
|
||||
|
INC HL |
||||
|
LD A, (HL) |
||||
|
OUT (REG_1DAY+ M6242RTC_BASE), A |
||||
|
RRA |
||||
|
RRA |
||||
|
RRA |
||||
|
RRA |
||||
|
OUT (REG_10DAY + M6242RTC_BASE), A |
||||
|
|
||||
|
INC HL |
||||
|
LD A, (HL) |
||||
|
OUT (REG_1HR + M6242RTC_BASE), A |
||||
|
RRA |
||||
|
RRA |
||||
|
RRA |
||||
|
RRA |
||||
|
OUT (REG_10HR + M6242RTC_BASE), A |
||||
|
|
||||
|
INC HL |
||||
|
LD A, (HL) |
||||
|
OUT (REG_1MIN + M6242RTC_BASE), A |
||||
|
RRA |
||||
|
RRA |
||||
|
RRA |
||||
|
RRA |
||||
|
OUT (REG_10MIN + M6242RTC_BASE), A |
||||
|
|
||||
|
INC HL |
||||
|
LD A, (HL) |
||||
|
OUT (REG_1SEC + M6242RTC_BASE), A |
||||
|
RRA |
||||
|
RRA |
||||
|
RRA |
||||
|
RRA |
||||
|
OUT (REG_10SEC + M6242RTC_BASE), A |
||||
|
POP HL |
||||
|
XOR A ; SIGNAL SUCCESS |
||||
|
RET ; AND RETURN |
||||
|
; |
||||
|
; REPORT RTC DEVICE INFO |
||||
|
; |
||||
|
M6242RTC_DEVICE: |
||||
|
LD D,RTCDEV_M6242 ; D := DEVICE TYPE |
||||
|
LD E,0 ; E := PHYSICAL DEVICE NUMBER |
||||
|
LD H,0 ; H := 0, DRIVER HAS NO MODES |
||||
|
LD L,0 ; L := 0, NO I/O ADDRESS |
||||
|
XOR A ; SIGNAL SUCCESS |
||||
|
RET |
||||
|
|
||||
|
M6242RTC_BCDBUF: |
||||
|
RP5RTC_YR .DB 20 |
||||
|
RP5RTC_MO .DB 01 |
||||
|
RP5RTC_DT .DB 01 |
||||
|
RP5RTC_HH .DB 00 |
||||
|
RP5RTC_MM .DB 00 |
||||
|
RP5RTC_SS .DB 00 |
||||
Loading…
Reference in new issue