Z280 ROMless Fixes

- Corrected a couple deficiencies that caused Z280 CPUs to fail in the new ROMless configuration

Source/HBIOS/Bank Layout.txt

@@ -55,7 +55,7 @@ Bank ID         Usage
 
 
 ROMless Tiny Bank Layout (128K)
-NOTE: No ROM Apps, No CP/M 3 support
+NOTE: no ROM Apps, no CP/M 3 support, no RAM disk
 
 Bank ID         Usage
 -------         ------
@@ -63,3 +63,12 @@ Bank ID         Usage
 0x81		Loader, DbgMon, CP/M 2.2, ZSDOS
 0x82            User TPA
 0x83            Common
+
+Disk Image Sizes
+
+Image Size	ROM System	ROMless System
+----------	----------	--------------
+1024K		896K		768K
+512		384K		256K
+256		128K		0K
+128 (tiny)	n/a		0K

Source/HBIOS/Build.cmd

@@ -220,6 +220,7 @@ call Build RCZ280 ext || exit /b
 call Build RCZ280 nat || exit /b
 call Build RCZ280 zz80mb || exit /b
 call Build RCZ280 zzrc || exit /b
+call Build RCZ280 zzrc_ram || exit /b
 call Build SCZ180 sc126 || exit /b
 call Build SCZ180 sc130 || exit /b
 call Build SCZ180 sc131 || exit /b

Source/HBIOS/Build.sh

@@ -19,6 +19,7 @@ if [ "${ROM_PLATFORM}" == "dist" ] ; then
 	ROM_PLATFORM="RCZ280"; ROM_CONFIG="nat"; bash Build.sh
 	ROM_PLATFORM="RCZ280"; ROM_CONFIG="zz80mb"; bash Build.sh
 	ROM_PLATFORM="RCZ280"; ROM_CONFIG="zzrc"; bash Build.sh
+	ROM_PLATFORM="RCZ280"; ROM_CONFIG="zzrc_ram"; bash Build.sh
 #	ROM_PLATFORM="RCZ80"; ROM_CONFIG="mt"; bash Build.sh
 #	ROM_PLATFORM="RCZ80"; ROM_CONFIG="duart"; bash Build.sh
 	ROM_PLATFORM="RCZ80"; ROM_CONFIG="std"; bash Build.sh

Source/HBIOS/Config/RCZ280_zz80mb.asm

@@ -37,8 +37,7 @@ FPSW_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL SWITCHES
 ;
 MEMMGR		.SET	MM_Z280		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
 ;
-RAMLOC		.SET	23		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
-RAMBIAS		.SET	(1 << (RAMLOC - 10))	; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
+RAMBIAS		.SET	8192		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 ;
 Z280_MEMLOWAIT	.SET	0		; Z280: LOW 8MB MEMORY WAIT STATES (0-3)
 Z280_MEMHIWAIT	.SET	0		; Z280: HIGH 8MB MEMORY WAIT STATES (0-3)

Source/HBIOS/Config/RCZ280_zzrc.asm

@@ -39,10 +39,7 @@ MEMMGR		.SET	MM_Z280		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
 ;
 RAMSIZE		.SET	256		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.SET	256		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-ROMSIZE_CHK	.SET	256		; ROMSIZE VALUE VERIFICATION (0=DISABLED)
-;
-RAMLOC		.SET	18		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
-RAMBIAS		.SET	(1 << (RAMLOC - 10))	; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
+RAMBIAS		.SET	ROMSIZE		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 ;
 Z280_MEMLOWAIT	.SET	0		; Z280: LOW 8MB MEMORY WAIT STATES (0-3)
 Z280_MEMHIWAIT	.SET	0		; Z280: HIGH 8MB MEMORY WAIT STATES (0-3)

Source/HBIOS/Config/RCZ280_zzrc_ram.asm

@@ -0,0 +1,77 @@
+;
+;==================================================================================================
+;   RCBUS Z280 STANDARD CONFIGURATION (NATIVE Z280 MMU W/ LINEAR MEMORY ON ZZRC)
+;==================================================================================================
+;
+; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
+; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
+; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
+; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
+; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
+; YOUR FILE IN THE BUILD PROCESS.
+;
+; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
+; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
+; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
+; SETTINGS.
+;
+; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
+; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
+; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
+; DIRECTORIES ABOVE THIS ONE).
+;
+#DEFINE PLATFORM_NAME "ZZRC", " [", CONFIG, "]"
+;
+#DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
+;
+#include "cfg_rcz280.asm"
+;
+CPUOSC		.SET	14745600	; CPU OSC FREQ IN MHZ
+INTMODE		.SET	3		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
+CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+;
+FPLED_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL LEDS
+FPSW_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL SWITCHES
+;
+MEMMGR		.SET	MM_Z280		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
+;
+RAMSIZE		.SET	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.SET	0		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
+RAMBIAS		.SET	ROMSIZE		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
+;
+Z280_MEMLOWAIT	.SET	0		; Z280: LOW 8MB MEMORY WAIT STATES (0-3)
+Z280_MEMHIWAIT	.SET	0		; Z280: HIGH 8MB MEMORY WAIT STATES (0-3)
+Z280_IOWAIT	.SET	1		; Z280: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
+Z280_INTWAIT	.SET	0		; Z280: INT ACK WAIT STATUS (0-3)
+;
+MDROM		.SET	FALSE		; MD: ENABLE ROM DISK
+MDRAM		.SET	TRUE		; MD: ENABLE RAM DISK
+;
+Z2UENABLE	.SET	TRUE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
+Z2UOSC		.SET	(CPUOSC / 8)	; Z2U: OSC FREQUENCY IN MHZ
+Z2U0HFC		.SET	TRUE		; Z2U0: ENABLE HARDWARE FLOW CONTROL
+UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+ACIAENABLE	.SET	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+SIOENABLE	.SET	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+;
+TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
+MKYENABLE	.SET	FALSE		; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
+VRCENABLE	.SET	TRUE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+VDAEMU_SERKBD	.SET	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+;
+AY38910ENABLE	.SET	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
+AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC]
+SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+;
+FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
+;
+IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+SDENABLE	.SET	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDCNT		.SET	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT SC ONLY
+;
+PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)

Source/HBIOS/cfg_duo.asm

@@ -34,7 +34,6 @@ DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VERIFICATION (0=DISABLED)
 MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
 MPGSEL_0	.EQU	$50		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$51		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)

Source/HBIOS/cfg_dyno.asm

@@ -34,10 +34,8 @@ DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VERIFICATION (0=DISABLED)
 MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
-RAMLOC		.EQU	19		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
-RAMBIAS		.EQU	(1 << (RAMLOC - 10))	; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
+RAMBIAS		.EQU	ROMSIZE		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)

Source/HBIOS/cfg_heath.asm

@@ -34,7 +34,6 @@ DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VERIFICATION (0=DISABLED)
 MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)

Source/HBIOS/cfg_master.asm

@@ -31,10 +31,8 @@ DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VERIFICATION (0=DISABLED)
 MEMMGR		.EQU	MM_NONE		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
-RAMLOC		.EQU	19		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
-RAMBIAS		.EQU	(1 << (RAMLOC - 10))	; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
+RAMBIAS		.EQU	ROMSIZE		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 MPCL_RAM	.EQU	$78		; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
 MPCL_ROM	.EQU	$7C		; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)

Source/HBIOS/cfg_mbc.asm

@@ -34,7 +34,6 @@ DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VERIFICATION (0=DISABLED)
 MEMMGR		.EQU	MM_MBC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
 MPCL_RAM	.EQU	$78		; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
 MPCL_ROM	.EQU	$7C		; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)

Source/HBIOS/cfg_mk4.asm

@@ -34,10 +34,8 @@ DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VERIFICATION (0=DISABLED)
 MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
-RAMLOC		.EQU	19		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
-RAMBIAS		.EQU	(1 << (RAMLOC - 10))	; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
+RAMBIAS		.EQU	ROMSIZE		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 ;
 Z180_BASE	.EQU	$40		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
 Z180_CLKDIV	.EQU	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2

Source/HBIOS/cfg_n8.asm

@@ -34,10 +34,8 @@ DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VERIFICATION (0=DISABLED)
 MEMMGR		.EQU	MM_N8		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
 RAMBIAS		.EQU	0		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
-RAMLOC		.EQU	0		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
 ;
 Z180_BASE	.EQU	$40		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
 Z180_CLKDIV	.EQU	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2

Source/HBIOS/cfg_rcz180.asm

@@ -34,10 +34,8 @@ DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VERIFICATION (0=DISABLED)
 MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
-RAMLOC		.EQU	19		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
-RAMBIAS		.EQU	(1 << (RAMLOC - 10))	; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
+RAMBIAS		.EQU	ROMSIZE		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)

Source/HBIOS/cfg_rcz280.asm

@@ -34,10 +34,8 @@ DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VERIFICATION (0=DISABLED)
 MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
-RAMLOC		.EQU	19		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
-RAMBIAS		.EQU	(1 << (RAMLOC - 10))	; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
+RAMBIAS		.EQU	ROMSIZE		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)

Source/HBIOS/cfg_rcz80.asm

@@ -34,7 +34,6 @@ DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VERIFICATION (0=DISABLED)
 MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)

Source/HBIOS/cfg_rph.asm

@@ -34,10 +34,8 @@ DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VERIFICATION (0=DISABLED)
 MEMMGR		.EQU	MM_RPH		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
 RAMBIAS		.EQU	0		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
-RAMLOC		.EQU	0		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
 ;
 Z180_BASE	.EQU	$40		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
 Z180_CLKDIV	.EQU	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2

Source/HBIOS/cfg_s100.asm

@@ -34,10 +34,8 @@ DEFSERCFG	.EQU	SER_57600_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VERIFICATION (0=DISABLED)
 MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
-RAMLOC		.EQU	19		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
-RAMBIAS		.EQU	(1 << (RAMLOC - 10))	; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
+RAMBIAS		.EQU	ROMSIZE		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)

Source/HBIOS/cfg_sbc.asm

@@ -34,7 +34,6 @@ DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VERIFICATION (0=DISABLED)
 MEMMGR		.EQU	MM_SBC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
 MPCL_RAM	.EQU	$78		; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
 MPCL_ROM	.EQU	$7C		; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)

Source/HBIOS/cfg_scz180.asm

@@ -34,10 +34,8 @@ DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VERIFICATION (0=DISABLED)
 MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
-RAMLOC		.EQU	19		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
-RAMBIAS		.EQU	(1 << (RAMLOC - 10))	; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
+RAMBIAS		.EQU	ROMSIZE		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)

Source/HBIOS/cfg_z80retro.asm

@@ -34,7 +34,6 @@ DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VERIFICATION (0=DISABLED)
 MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
 MPGSEL_0	.EQU	$60		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$61		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)

Source/HBIOS/cfg_zeta.asm

@@ -34,7 +34,6 @@ DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VERIFICATION (0=DISABLED)
 MEMMGR		.EQU	MM_SBC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
 MPCL_RAM	.EQU	$78		; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
 MPCL_ROM	.EQU	$7C		; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)

Source/HBIOS/cfg_zeta2.asm

@@ -34,7 +34,6 @@ DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VERIFICATION (0=DISABLED)
 MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)

Source/HBIOS/hbios.asm

@@ -88,20 +88,6 @@ MODCNT	.SET	MODCNT + 1
 	!!!	; FORCE AN ASSEMBLY ERROR
 #ENDIF
 ;
-; SOME HARDWARE REQUIRES A SPECIFIC ROMSIZE (NOTABLY ZZRCC) OR THE
-; RESULTING BUILD IMAGES WILL BE CORRUPT.  ROMSIZE_CHK IS SPECIFIED
-; IN THE CONFIG FILE AND IS VERIFIED AGAINST THE ROMSIZE BEING USED
-; BY THE BUILD.  A ROMSIZE_CHK VALUE OF 0 INDICATES THE VERIFICATION
-; IS DISABLED (WHICH IT USUALLY IS).
-;
-#IF (ROMSIZE_CHK != 0) & (ROMSIZE != ROMSIZE_CHK)
-	.ECHO	"*** ERROR: ROMSIZE VALUE VERIFICATION FAILURE.\n"
-	.ECHO	"THIS CONFIGURATION REQUIRES A ROMSIZE OF " \ .ECHO ROMSIZE_CHK \ .ECHO ".\n"
-	.ECHO	"BUILD IS USING A ROMSIZE OF " \ .ECHO ROMSIZE \ .ECHO ".\n"
-	.ECHO	"SEE COMMENTS IN HBIOS.ASM.\n"
-	!!!	; FORCE AN ASSEMBLY ERROR
-#ENDIF
-;
 ;
 ;
 #IF (FPLED_ENABLE)
@@ -196,7 +182,13 @@ MODCNT	.SET	MODCNT + 1
   #ENDIF
 #ENDIF
 ;
+; CONVERT ROMWBW LOGICAL BANK ID TO PHYSICAL 32K BANK OFFSET
 ;
+#DEFINE PBANK(X) (((X >> 7) * (RAMBIAS / 32)) + (X & $7F))
+;
+; CONVERT ROMWBW LOGICAL BANK ID TO Z280 PHYSICAL BANK (4K) OFFSET
+;
+#DEFINE Z2_BANK(X) (PBANK(X) << 3)
 ;
 ; THE RTCDEF EQUATE IS INITIALIZED HERE AND UPDATED BY DRIVER INCLUDES
 ; THAT SHARE THE RTC LATCH.  AS EACH DRIVER FILE IS INCLUDED, IT CAN
@@ -1222,14 +1214,14 @@ Z280_BOOTPDRTBL:
 	.DW	($006 << 4) | $A
 	.DW	($007 << 4) | $A
 	; UPPER 32 K (COMMON)
-	.DW	(((((BID_COM & $7F) * 8) + 0) + (1 << (RAMLOC - 12))) << 4) | $A
-	.DW	(((((BID_COM & $7F) * 8) + 1) + (1 << (RAMLOC - 12))) << 4) | $A
-	.DW	(((((BID_COM & $7F) * 8) + 2) + (1 << (RAMLOC - 12))) << 4) | $A
-	.DW	(((((BID_COM & $7F) * 8) + 3) + (1 << (RAMLOC - 12))) << 4) | $A
-	.DW	(((((BID_COM & $7F) * 8) + 4) + (1 << (RAMLOC - 12))) << 4) | $A
-	.DW	(((((BID_COM & $7F) * 8) + 5) + (1 << (RAMLOC - 12))) << 4) | $A
-	.DW	(((((BID_COM & $7F) * 8) + 6) + (1 << (RAMLOC - 12))) << 4) | $A
-	.DW	(((((BID_COM & $7F) * 8) + 7) + (1 << (RAMLOC - 12))) << 4) | $A
+	.DW	((Z2_BANK(BID_COM) + 0) << 4) | $A
+	.DW	((Z2_BANK(BID_COM) + 1) << 4) | $A
+	.DW	((Z2_BANK(BID_COM) + 2) << 4) | $A
+	.DW	((Z2_BANK(BID_COM) + 3) << 4) | $A
+	.DW	((Z2_BANK(BID_COM) + 4) << 4) | $A
+	.DW	((Z2_BANK(BID_COM) + 5) << 4) | $A
+	.DW	((Z2_BANK(BID_COM) + 6) << 4) | $A
+	.DW	((Z2_BANK(BID_COM) + 7) << 4) | $A
 ;
 Z280_INITZ:
 ;
@@ -1609,12 +1601,16 @@ MBC_SINGLE:
 ;
 ; IF ALREADY EXECUTING IN RAM, BYPASS RAM BANK INSTALLATION
 ;
-	LD	A,TRUE
-	LD	(HB_RAMFLAG),A
 	LD	A,(HB_RAMFLAG)
 	OR	A
 	JR	NZ,HB_START1
 ;
+; IF BID_BOOT AND BID_BIOS ARE THE SAME, THEN IT IS NEVER APPROPRIATE
+; TO COPY THE HBIOS IMAGE FROM BID_BOOT TO BID_BIOS.  THIS IS TYPICALLY
+; THE CASE FOR A ROMLESS SYSTEM.
+;
+#IF (BID_BOOT != BID_BIOS)
+;
 ; INSTALL HBIOS IN RAM BANK
 ;
 	LD	A,(HB_CURBNK)
@@ -1644,6 +1640,8 @@ MBC_SINGLE:
 	HALT				; WE SHOULD NOT COME BACK HERE!
   #ENDIF
 ;
+#ENDIF
+;
 HB_RAMFLAG	.DB	FALSE		; INITIALLY FALSE, SET TO TRUE BELOW AFTER RAM TRANSITION
 ;
 ; EXECUTION RESUMES HERE AFTER SWITCH TO RAM BANK
@@ -1676,7 +1674,7 @@ HB_START1:				; BNKCALL ARRIVES HERE, BUT NOW RUNNING IN RAM BANK
 	; HL IS TOP 16 BITS OF PHYSICAL ADDRESS OF IVT
 	; IVT *MUST* BE ON A 4K BOUNDARY
 	LD	C,Z280_VPR
-	LD	HL,0 + ((((BID_BIOS & $7F) * 8) + (1 << (RAMLOC - 12))) << 4) + (Z280_IVT >> 8)
+	LD	HL,0 + (((PBANK(BID_BIOS) << 15) + Z280_IVT) >> 8)
 	LDCTL	(C),HL
 #ENDIF
 ;
@@ -5791,7 +5789,7 @@ Z280_BNKSEL:
 	LDCTL	HL,(C)			; GET CURRENT I/O PAGE
 	PUSH	HL			; SAVE IT
 	LD	L,$FF			; NEW I/O PAGE
-	LDCTL	(C),HL
+	LDCTL	(C),HL			; IMPLEMENT
 ;
 	; CONVERT BANK ID TO TOP 12 BITS OF PHYSICAL ADDRESS
 	; WITH $0A IN THE LOW ORDER NIBBLE:
@@ -5802,8 +5800,10 @@ Z280_BNKSEL:
 	MULTU	A,$80			; HL=0R00 0BBB B000 0000
 	BIT	6,H			; RAM BIT SET?
 	JR	Z,Z280_BNKSEL2		; IF NOT, ALL DONE
-	RES	6,H			; OTHERWISE, MOVE RAM BIT
-	SET	RAMLOC-16,H		; HL=0000 RBBB B000 0000
+	RES	6,H			; OTHERWISE, REMOVE RAM BIT
+	LD	A,RAMBIAS >> 6		; RAM OFFSET (TOP 8 BITS)
+	OR	H			; RECOMBINE
+	LD	H,A			; AND PUT BACK IN H
 ;
 Z280_BNKSEL2:
 ;
@@ -6051,10 +6051,12 @@ Z2DMAADR1:
 	; MOVE THE RAM/ROM BIT.
 	; RCBUS DMA HI=0000 RBBB BAAA 1111 LO=1111 AAAA AAAA AAAA
 	; ZZ80MB DMA HI=R000 0BBB BAAA 1111 LO=1111 AAAA AAAA AAAA
-	BIT	6,H
-	JR	Z,Z2DMAADR2
-	RES	6,H
-	SET	RAMLOC-16,H
+	BIT	6,H			; RAM BIT SET?
+	JR	Z,Z2DMAADR2		; IF NOT, ALL DONE
+	RES	6,H			; OTHERWISE, REMOVE RAM BIT
+	LD	A,RAMBIAS >> 6		; RAM OFFSET (TOP 8 BITS)
+	OR	H			; RECOMBINE
+	LD	H,A			; AND PUT BACK IN H
 ;
 Z2DMAADR2:
 	PUSH	HL			; SAVE IT FOR NOW

Source/ZZRC/Build.cmd

@@ -4,39 +4,38 @@ setlocal
 set ROMFILE=..\..\Binary\RCZ280_zzrc.rom
 set ROMSIZE=262144
 
-if not exist %ROMFILE% goto :eof
+set TOOLS=../../Tools
 
-::
-:: The ROM image *must* be exactly 256K or the resulting disk
-:: image produced below will be invalid.  Check for the proper size.
-::
+set PATH=%TOOLS%\srecord;%PATH%
 
-call :filesize %ROMFILE%
+if exist ..\..\Binary\RCZ280_zzrc.rom call :build_zzrc
 
-if "%FILESIZE%" neq "%ROMSIZE%" (
-  echo.
-  echo.
-  echo ERROR: "%ROMFILE%" is not exactly %ROMSIZE% bytes as required!!!
-  echo You must specify a ROMSIZE of "256" when building the ZZRCC ROM image.
-  echo.
-  echo.
-  exit /b 1
-)
+if exist ..\..\Binary\RCZ280_zzrc_ram.rom call :build_zzrc_ram
 
-rem ..\..\Tools\srecord\srec_cat.exe ..\..\Binary\RCZ280_zzrc.rom -Binary -Exclude 0x5000 0x7000 zzrc_romldr.hex -Intel -Output ..\..\Binary\RCZ280_zzrc.hex -Intel || exit /b
-
-..\..\Tools\srecord\srec_cat.exe ..\..\Binary\RCZ280_zzrc.rom -Binary -Output ..\..\Binary\RCZ280_zzrc.hex -Intel || exit /b
-
-rem ..\..\Tools\srecord\srec_cat.exe ..\..\Binary\RCZ280_zzrc.hex -Intel -Output ..\..\Binary\RCZ280_zzrc_ldr.rom -Binary || exit /b
+goto :eof
 
-rem copy /b zzrc_cfldr.bin + zzrc_ptbl.bin + zzrc_fill_1.bin + zzrc_mon.bin + zzrc_fill_2.bin + ..\..\Binary\RCZ280_zzrc_ldr.rom + zzrc_fill_3.bin ..\..\Binary\hd1k_zzrc_prefix.dat || exit /b
+:build_zzrc
 
-copy /b zzrc_cfldr.bin + zzrc_ptbl.bin + zzrc_fill_1.bin + zzrc_mon.bin + zzrc_fill_2.bin + ..\..\Binary\RCZ280_zzrc.rom + zzrc_fill_3.bin ..\..\Binary\hd1k_zzrc_prefix.dat || exit /b
+srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary
+srec_cat temp.dat -binary -exclude 0x0 0x100 zzrc_cfldr.bin -binary -o temp.dat -binary
+srec_cat temp.dat -binary -exclude 0x100 0x200 zzrc_ptbl.bin -binary -offset 0x100 -o temp.dat -binary
+srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zzrc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary
+srec_cat temp.dat -binary -exclude 0x24000 0xA4000 ..\..\Binary\RCZ280_zzrc.rom -binary -offset 0x24000 -o temp.dat -binary
+move temp.dat ..\..\Binary\hd1k_zzrc_prefix.dat
 
 copy /b ..\..\Binary\hd1k_zzrc_prefix.dat + ..\..\Binary\hd1k_cpm22.img + ..\..\Binary\hd1k_zsdos.img + ..\..\Binary\hd1k_nzcom.img + ..\..\Binary\hd1k_cpm3.img + ..\..\Binary\hd1k_zpm3.img + ..\..\Binary\hd1k_ws4.img ..\..\Binary\hd1k_zzrc_combo.img || exit /b
 
 goto :eof
 
-:filesize
-set FILESIZE=%~z1
+:build_zzrc_ram
+
+srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary
+srec_cat temp.dat -binary -exclude 0x0 0x100 zzrc_cfldr.bin -binary -o temp.dat -binary
+srec_cat temp.dat -binary -exclude 0x100 0x200 zzrc_ptbl.bin -binary -offset 0x100 -o temp.dat -binary
+srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zzrc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary
+srec_cat temp.dat -binary -exclude 0x24000 0xA4000 ..\..\Binary\RCZ280_zzrc_ram.rom -binary -offset 0x24000 -o temp.dat -binary
+move temp.dat ..\..\Binary\hd1k_zzrc_ram_prefix.dat
+
+copy /b ..\..\Binary\hd1k_zzrc_ram_prefix.dat + ..\..\Binary\hd1k_cpm22.img + ..\..\Binary\hd1k_zsdos.img + ..\..\Binary\hd1k_nzcom.img + ..\..\Binary\hd1k_cpm3.img + ..\..\Binary\hd1k_zpm3.img + ..\..\Binary\hd1k_ws4.img ..\..\Binary\hd1k_zzrc_ram_combo.img || exit /b
+
 goto :eof

Source/ZZRC/Makefile

@@ -1,15 +1,20 @@
 HD1KZZRCPREFIX = hd1k_zzrc_prefix.dat
 HD1KZZRCCOMBOIMG = hd1k_zzrc_combo.img
+HD1KZZRCRAMPREFIX = hd1k_zzrc_ram_prefix.dat
+HD1KZZRCRAMCOMBOIMG = hd1k_zzrc_ram_combo.img
 ZZRCROM = ../../Binary/RCZ280_zzrc.rom
-ZZRCROMHEX = RCZ280_zzrc.hex
+ZZRCRAMROM = ../../Binary/RCZ280_zzrc_ram.rom
 HD1KIMGS = ../../Binary/hd1k_cpm22.img ../../Binary/hd1k_zsdos.img ../../Binary/hd1k_nzcom.img \
 	../../Binary/hd1k_cpm3.img ../../Binary/hd1k_zpm3.img ../../Binary/hd1k_ws4.img
-ZZRCROMSIZE = 262144
 
 OBJECTS :=
 
 ifneq ($(wildcard $(ZZRCROM)),)
-	OBJECTS += $(ZZRCROMHEX) $(HD1KZZRCPREFIX) $(HD1KZZRCCOMBOIMG)
+	OBJECTS += $(HD1KZZRCPREFIX) $(HD1KZZRCCOMBOIMG)
+endif
+
+ifneq ($(wildcard $(ZZRCRAMROM)),)
+	OBJECTS += $(HD1KZZRCRAMPREFIX) $(HD1KZZRCRAMCOMBOIMG)
 endif
 
 DEST=../../Binary
@@ -20,14 +25,24 @@ include $(TOOLS)/Makefile.inc
 
 DIFFPATH = $(DIFFTO)/Binary
 
-zzrcromchk:
-	[ `wc -c $(ZZRCROM) | awk '{print $$1}'` = $(ZZRCROMSIZE) ]
-	
-$(HD1KZZRCPREFIX): zzrcromchk
-	cat zzrc_cfldr.bin zzrc_ptbl.bin zzrc_fill_1.bin zzrc_mon.bin zzrc_fill_2.bin $(ZZRCROM) zzrc_fill_3.bin >$@
-
-$(HD1KZZRCCOMBOIMG): zzrcromchk $(HD1KZZRCPREFIX) $(HD1KIMGS)
-	cat $(HD1KZZRCPREFIX) $(HD1KIMGS) > $@
-
-$(ZZRCROMHEX): zzrcromchk $(ZZRCROM)
-	srec_cat $(ZZRCROM) -Binary -Output $(ZZRCROMHEX) -Intel -CRLF
+$(HD1KZZRCPREFIX):
+	srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary
+	srec_cat temp.dat -binary -exclude 0x0 0x100 zzrc_cfldr.bin -binary -o temp.dat -binary
+	srec_cat temp.dat -binary -exclude 0x100 0x200 zzrc_ptbl.bin -binary -offset 0x100 -o temp.dat -binary
+	srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zzrc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary
+	srec_cat temp.dat -binary -exclude 0x24000 0xA4000 $(ZZRCROM) -binary -offset 0x24000 -o temp.dat -binary
+	mv temp.dat $@
+
+$(HD1KZZRCRAMPREFIX):
+	srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary
+	srec_cat temp.dat -binary -exclude 0x0 0x100 zzrc_cfldr.bin -binary -o temp.dat -binary
+	srec_cat temp.dat -binary -exclude 0x100 0x200 zzrc_ptbl.bin -binary -offset 0x100 -o temp.dat -binary
+	srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zzrc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary
+	srec_cat temp.dat -binary -exclude 0x24000 0xA4000 $(ZZRCRAMROM) -binary -offset 0x24000 -o temp.dat -binary
+	mv temp.dat $@
+
+$(HD1KZZRCCOMBOIMG): $(HD1KZZRCPREFIX) $(HD1KIMGS)
+	cat $^ > $@
+
+$(HD1KZZRCRAMCOMBOIMG): $(HD1KZZRCRAMPREFIX) $(HD1KIMGS)
+	cat $^ > $@

Source/ver.inc

@@ -2,7 +2,7 @@
 #DEFINE	RMN	3
 #DEFINE	RUP	0
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"3.3.0-dev.58"
+#DEFINE BIOSVER	"3.3.0-dev.59"
 #define rmj	RMJ
 #define rmn	RMN
 #define rup	RUP

Source/ver.lib

@@ -3,5 +3,5 @@ rmn	equ	3
 rup	equ	0
 rtp	equ	0
 biosver	macro
-	db	"3.3.0-dev.58"
+	db	"3.3.0-dev.59"
 	endm