RTC Port Shadow Register

Implemented a shadow copy of the RTC port value to enable multiple drivers to share the port without causing side effects to other drivers that use other bits of the RTC port.

Source/HBIOS/Config/RCZ180_sc126.asm

@@ -13,7 +13,6 @@ DIAGPORT	.SET	$0D		; DIAGNOSTIC PORT ADDRESS
 ;
 CPUOSC		.SET	18432000	; CPU OSC FREQ
 DEFSERCFG	.SET	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG
-DSRTCMODE	.SET	DSRTCMODE_SC126	; DSRTCMODE_STD, DSRTCMODE_MFPIC, DSRTCMODE_126
 ;
 ASCIENABLE	.SET	TRUE		; TRUE FOR Z180 ASCI SUPPORT
 SIOENABLE	.SET	FALSE		; TRUE TO AUTO-DETECT ZILOG SIO/2 

Source/HBIOS/cfg_ezz80.asm

@@ -21,7 +21,7 @@ DSKYENABLE	.EQU	FALSE		; TRUE FOR DSKY SUPPORT (DO NOT COMBINE WITH PPIDE)
 HTIMENABLE	.EQU	FALSE		; TRUE FOR SIMH TIMER SUPPORT
 SIMRTCENABLE	.EQU	FALSE		; SIMH CLOCK DRIVER
 DSRTCENABLE	.EQU	FALSE		; DS-1302 CLOCK DRIVER
-DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTCMODE_STD, DSRTCMODE_MFPIC, DSRTCMODE_126
+DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTCMODE_STD, DSRTCMODE_MFPIC
 DSRTCCHG	.EQU	FALSE		; DS-1302 CONFIGURE CHARGE ON (TRUE) OR OFF (FALSE)
 ;
 ASCIENABLE	.EQU	FALSE		; TRUE FOR Z180 ASCI SUPPORT

Source/HBIOS/cfg_mk4.asm

@@ -21,7 +21,7 @@ DSKYENABLE	.EQU	FALSE		; TRUE FOR DSKY SUPPORT (DO NOT COMBINE WITH PPIDE)
 HTIMENABLE	.EQU	FALSE		; TRUE FOR SIMH TIMER SUPPORT
 SIMRTCENABLE	.EQU	FALSE		; SIMH CLOCK DRIVER
 DSRTCENABLE	.EQU	TRUE		; DS-1302 CLOCK DRIVER
-DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTCMODE_STD, DSRTCMODE_MFPIC, DSRTCMODE_126
+DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTCMODE_STD, DSRTCMODE_MFPIC
 DSRTCCHG	.EQU	FALSE		; DS-1302 CONFIGURE CHARGE ON (TRUE) OR OFF (FALSE)
 ;
 ASCIENABLE	.EQU	TRUE		; TRUE FOR Z180 ASCI SUPPORT

Source/HBIOS/cfg_n8.asm

@@ -21,7 +21,7 @@ DSKYENABLE	.EQU	FALSE		; TRUE FOR DSKY SUPPORT (DO NOT COMBINE WITH PPIDE)
 HTIMENABLE	.EQU	FALSE		; TRUE FOR SIMH TIMER SUPPORT
 SIMRTCENABLE	.EQU	FALSE		; SIMH CLOCK DRIVER
 DSRTCENABLE	.EQU	TRUE		; DS-1302 CLOCK DRIVER
-DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTCMODE_STD, DSRTCMODE_MFPIC, DSRTCMODE_126
+DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTCMODE_STD, DSRTCMODE_MFPIC
 DSRTCCHG	.EQU	FALSE		; DS-1302 CONFIGURE CHARGE ON (TRUE) OR OFF (FALSE)
 ;
 ASCIENABLE	.EQU	TRUE		; TRUE FOR Z180 ASCI SUPPORT

Source/HBIOS/cfg_rcz180.asm

@@ -21,7 +21,7 @@ DSKYENABLE	.EQU	FALSE		; TRUE FOR DSKY SUPPORT (DO NOT COMBINE WITH PPIDE)
 HTIMENABLE	.EQU	FALSE		; TRUE FOR SIMH TIMER SUPPORT
 SIMRTCENABLE	.EQU	FALSE		; SIMH CLOCK DRIVER
 DSRTCENABLE	.EQU	FALSE		; DS-1302 CLOCK DRIVER
-DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTCMODE_STD, DSRTCMODE_MFPIC, DSRTCMODE_126
+DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTCMODE_STD, DSRTCMODE_MFPIC
 DSRTCCHG	.EQU	FALSE		; DS-1302 CONFIGURE CHARGE ON (TRUE) OR OFF (FALSE)
 ;
 ASCIENABLE	.EQU	TRUE		; TRUE FOR Z180 ASCI SUPPORT

Source/HBIOS/cfg_rcz80.asm

@@ -21,7 +21,7 @@ DSKYENABLE	.EQU	FALSE		; TRUE FOR DSKY SUPPORT (DO NOT COMBINE WITH PPIDE)
 HTIMENABLE	.EQU	FALSE		; TRUE FOR SIMH TIMER SUPPORT
 SIMRTCENABLE	.EQU	FALSE		; SIMH CLOCK DRIVER
 DSRTCENABLE	.EQU	FALSE		; DS-1302 CLOCK DRIVER
-DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTCMODE_STD, DSRTCMODE_MFPIC, DSRTCMODE_126
+DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTCMODE_STD, DSRTCMODE_MFPIC
 DSRTCCHG	.EQU	FALSE		; DS-1302 CONFIGURE CHARGE ON (TRUE) OR OFF (FALSE)
 ;
 ASCIENABLE	.EQU	FALSE		; TRUE FOR Z180 ASCI SUPPORT

Source/HBIOS/cfg_sbc.asm

@@ -21,7 +21,7 @@ DSKYENABLE	.EQU	FALSE		; TRUE FOR DSKY SUPPORT (DO NOT COMBINE WITH PPIDE)
 HTIMENABLE	.EQU	FALSE		; TRUE FOR SIMH TIMER SUPPORT
 SIMRTCENABLE	.EQU	FALSE		; SIMH CLOCK DRIVER
 DSRTCENABLE	.EQU	TRUE		; DS-1302 CLOCK DRIVER
-DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTCMODE_STD, DSRTCMODE_MFPIC, DSRTCMODE_126
+DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTCMODE_STD, DSRTCMODE_MFPIC
 DSRTCCHG	.EQU	FALSE		; DS-1302 CONFIGURE CHARGE ON (TRUE) OR OFF (FALSE)
 ;
 ASCIENABLE	.EQU	FALSE		; TRUE FOR Z180 ASCI SUPPORT

Source/HBIOS/cfg_zeta.asm

@@ -21,7 +21,7 @@ DSKYENABLE	.EQU	FALSE		; TRUE FOR DSKY SUPPORT (DO NOT COMBINE WITH PPIDE)
 HTIMENABLE	.EQU	FALSE		; TRUE FOR SIMH TIMER SUPPORT
 SIMRTCENABLE	.EQU	FALSE		; SIMH CLOCK DRIVER
 DSRTCENABLE	.EQU	TRUE		; DS-1302 CLOCK DRIVER
-DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTCMODE_STD, DSRTCMODE_MFPIC, DSRTCMODE_126
+DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTCMODE_STD, DSRTCMODE_MFPIC
 DSRTCCHG	.EQU	FALSE		; DS-1302 CONFIGURE CHARGE ON (TRUE) OR OFF (FALSE)
 ;
 ASCIENABLE	.EQU	FALSE		; TRUE FOR Z180 ASCI SUPPORT

Source/HBIOS/dsrtc.asm

@@ -63,64 +63,51 @@
 ;
 ; CONSTANTS
 ;
-; RTC	SBC	SBC-004	N8	N8-CSIO	SC126	
-; -----	-------	-------	-------	-------	-------	
-; D7 WR	RTC_OUT RTC_OUT RTC_OUT RTC_OUT RTC_OUT, I2C_SDA
-; D6 WR	RTC_CLK RTC_CLK RTC_CLK RTC_CLK RTC_CLK 
-; D5 WR	/RTC_WE /RTC_WE /RTC_WE /RTC_WE /RTC_WE  
-; D4 WR	RTC_CE  RTC_CE  RTC_CE  RTC_CE  RTC_CE  
-; D3 WR	NC      SPK     NC      NC      /SPI_CS1      
-; D2 WR	NC      CLKHI   SPI_CS	SPI_CS	/SPI_CS2 
-; D1 WR	--      --	SPI_CLK	NC	FS 
-; D0 WR	--	--	SPI_DI	NC	I2C_SCL    
+; RTC	SBC	SBC-004	MFPIC	N8	N8-CSIO	SC126	
+; -----	-------	-------	-------	-------	-------	-------	
+; D7 WR	RTC_OUT RTC_OUT --	RTC_OUT RTC_OUT RTC_OUT, I2C_SDA
+; D6 WR	RTC_CLK RTC_CLK --	RTC_CLK RTC_CLK RTC_CLK 
+; D5 WR	/RTC_WE /RTC_WE --	/RTC_WE /RTC_WE /RTC_WE  
+; D4 WR	RTC_CE  RTC_CE  --	RTC_CE  RTC_CE  RTC_CE  
+; D3 WR	NC      SPK     /RTC_CE	NC      NC      /SPI_CS2      
+; D2 WR	NC      CLKHI   RTC_CLK	SPI_CS	SPI_CS	/SPI_CS1 
+; D1 WR	--      --	RTC_WE	SPI_CLK	NC	FS 
+; D0 WR	--	--	RTC_OUT	SPI_DI	NC	I2C_SCL    
 ;                       
-; D7 RD	--	--	--	--	I2C_SDA	 
-; D6 RD	CFG	CFG	SPI_DO	CFG	--	 
-; D5 RD	--	--	--	--	--	
-; D4 RD	--	--	--	--	--	
-; D3 RD	--	--	--	--	--	     
-; D2 RD	--	--	--	--	--	
-; D1 RD	--      --      --      --      --      
-; D0 RD	RTC_IN  RTC_IN  RTC_IN	RTC_IN  RTC_IN     
+; D7 RD	--	--	--	--	--	I2C_SDA	 
+; D6 RD	CFG	CFG	--	SPI_DO	CFG	--	 
+; D5 RD	--	--	--	--	--	--	
+; D4 RD	--	--	--	--	--	--	
+; D3 RD	--	--	--	--	--	--	     
+; D2 RD	--	--	--	--	--	--	
+; D1 RD	--      --      --      --      --      --      
+; D0 RD	RTC_IN  RTC_IN  RTC_IN	RTC_IN	RTC_IN  RTC_IN     
 ;
 #IF (DSRTCMODE == DSRTCMODE_STD)
 ;
-DSRTC_BASE	.EQU	RTC		; RTC PORT ON ALL SBC SERIES Z80 PLATFORMS
-;
-DSRTC_DATA	.EQU	%10000000	; BIT 7 CONTROLS RTC DATA (I/O) LINE
-DSRTC_CLK	.EQU	%01000000	; BIT 6 CONTROLS RTC CLOCK LINE, 1 = HIGH
-DSRTC_RD	.EQU	%00100000	; BIT 5 CONTROLS DATA DIRECTION, 1 = READ
-DSRTC_CE	.EQU	%00010000	; BIT 4 CONTROLS RTC CE LINE, 1 = HIGH (ENABLED)
-;
-DSRTC_RESET	.EQU	%00000000	; ALL LOW
-;
-#ENDIF
-;
-#IF (DSRTCMODE == DSRTCMODE_SC126)
-;
 DSRTC_BASE	.EQU	RTC		; RTC PORT
 ;
-DSRTC_DATA	.EQU	%10000000	; BIT 7 CONTROLS RTC DATA (I/O) LINE
-DSRTC_CLK	.EQU	%01000000	; BIT 6 CONTROLS RTC CLOCK LINE, 1 = HIGH
-DSRTC_RD	.EQU	%00100000	; BIT 5 CONTROLS DATA DIRECTION, 1 = READ
-DSRTC_CE	.EQU	%00010000	; BIT 4 CONTROLS RTC CE LINE, 1 = HIGH (ENABLED)
+DSRTC_DATA	.EQU	%10000000	; BIT 7 IS RTC DATA OUT
+DSRTC_CLK	.EQU	%01000000	; BIT 6 IS RTC CLOCK (CLK)
+DSRTC_RD	.EQU	%00100000	; BIT 5 IS DATA  DIRECTION (/WE)
+DSRTC_CE	.EQU	%00010000	; BIT 4 IS CHIP ENABLE (CE)
 ;
-DSRTC_RESET	.EQU	%00001101	; /SPI_CS1, /SPI_CS2, & I2C_SCL HIGH
+DSRTC_MASK	.EQU	%11110000	; MASK FOR BITS WE OWN IN RTC LATCH PORT
+DSRTC_IDLE	.EQU	%00100000	; QUIESCENT STATE
 ;
 #ENDIF
-
-
 ;
 #IF (DSRTCMODE == DSRTCMODE_MFPIC)
 ;
 DSRTC_BASE	.EQU	$43		; RTC PORT ON MF/PIC
 ;
-DSRTC_DATA	.EQU	%00000001	; BIT 0 CONTROLS RTC DATA (I/O) LINE
-DSRTC_CLK	.EQU	%00000100	; BIT 2 CONTROLS RTC CLOCK LINE, 1 = HIGH
-DSRTC_WR	.EQU	%00000010	; BIT 1 CONTROLS DATA DIRECTION, 1 = WRITE
-DSRTC_CE	.EQU	%00001000	; BIT 3 CONTROLS RTC CE LINE, 0 = ENABLED
+DSRTC_DATA	.EQU	%00000001	; BIT 0 IS RTC DATA OUT
+DSRTC_CLK	.EQU	%00000100	; BIT 2 IS RTC CLOCK (CLK)
+DSRTC_WR	.EQU	%00000010	; BIT 1 IS DATA DIRECTION (WE)
+DSRTC_CE	.EQU	%00001000	; BIT 3 CHIP ENABLE (/CE)
 ;
-DSRTC_RESET	.EQU	%00001000	; ALL LOW, BUT CE = 1
+DSRTC_MASK	.EQU	%00001111	; MASK FOR BITS WE OWN IN RTC LATCH PORT
+DSRTC_IDLE	.EQU	%00101000	; QUIESCENT STATE
 ;
 #ENDIF
 ;
@@ -138,9 +125,13 @@ DSRTC_INIT:
 #IF (DSRTCMODE == DSRTCMODE_MFPIC)
 	PRTS("MFPIC$")
 #ENDIF
-#IF (DSRTCMODE == DSRTCMODE_SC126)
-	PRTS("SC126$")
-#ENDIF
+;
+	; SET RELEVANT BITS IN RTC LATCH SHADOW REGISTER
+	; TO THEIR QUIESENT STATE
+	LD	A,(RTCVAL)
+	AND	DSRTC_MASK
+	OR	DSRTC_IDLE
+	LD	(RTCVAL),A
 ;
 	; CHECK FOR CLOCK HALTED
 	CALL	DSRTC_TSTCLK
@@ -162,21 +153,21 @@ DSRTC_INIT1:
 	CALL	PRTDT
 	
 #IF	DSRTCCHG			; FORCE_RTC_CHARGE_ENABLE
-	LD	C,$8E			; ACCESS WRITE PROT REG
+	LD	E,$8E			; ACCESS WRITE PROT REG
 	CALL	DSRTC_CMD		; 
-	LD	A,$00			; WRITE PROTECT OFF
+	LD	E,$00			; WRITE PROTECT OFF
 	CALL	DSRTC_PUT		; 	
 	CALL	DSRTC_END		; FINISH CMD
 	
-	LD	C,$90			; ACCESS CHARGE REGISTER
+	LD	E,$90			; ACCESS CHARGE REGISTER
 	CALL	DSRTC_CMD		; 
-	LD	A,$A5			; STD CHARGE VALUES
+	LD	E,$A5			; STD CHARGE VALUES
 	CALL	DSRTC_PUT		; 
 	CALL	DSRTC_END		; FINISH REG WRITE
 	
-	LD	C,$8E			; ACCESS WRITE PROT REG
+	LD	E,$8E			; ACCESS WRITE PROT REG
 	CALL	DSRTC_CMD		; 
-	LD	A,$80			; WRITE PROTECT ON
+	LD	E,$80			; WRITE PROTECT ON
 	CALL	DSRTC_PUT		; 	
 	CALL	DSRTC_END		; FINISH CMD
 #ENDIF
@@ -341,12 +332,13 @@ DSRTC_TIM2CLK:
 ; TEST CLOCK FOR CHARGE DATA
 ;
 DSRTC_TSTCHG:
-	LD		C,$91			; CHARGE RESISTOR & DIODE VALUES
+	LD	E,$91			; CHARGE RESISTOR & DIODE VALUES
 	CALL	DSRTC_CMD		; SEND THE COMMAND
 	CALL	DSRTC_GET		; READ THE REGISTER
 	CALL	DSRTC_END		; FINISH IT
-	AND		%11110000		; CHECK FOR
-	CP		%10100000		; ENABLED FLAG
+	LD	A,E			; VALUE TO A
+	AND	%11110000		; CHECK FOR
+	CP	%10100000		; ENABLED FLAG
 	RET	
 ;
 ; TEST CLOCK FOR VALID DATA
@@ -355,23 +347,24 @@ DSRTC_TSTCHG:
 ;   1 = HALTED
 ;
 DSRTC_TSTCLK:
-	LD	C,$81			; SECONDS REGISTER HAS CLOCK HALT FLAG
+	LD	E,$81			; SECONDS REGISTER HAS CLOCK HALT FLAG
 	CALL	DSRTC_CMD		; SEND THE COMMAND
 	CALL	DSRTC_GET		; READ THE REGISTER
 	CALL	DSRTC_END		; FINISH IT
+	LD	A,E			; VALUE TO A
 	AND	%10000000		; HIGH ORDER BIT IS CLOCK HALT
 	RET
 ;
 ; BURST READ CLOCK DATA INTO BUFFER AT HL
 ;
 DSRTC_RDCLK:
-	LD	C,$BF			; COMMAND = $BF TO BURST READ CLOCK
+	LD	E,$BF			; COMMAND = $BF TO BURST READ CLOCK
 	CALL	DSRTC_CMD		; SEND COMMAND TO RTC
 	LD	B,DSRTC_BUFSIZ		; B IS LOOP COUNTER
 DSRTC_RDCLK1:
 	PUSH	BC			; PRESERVE BC
 	CALL	DSRTC_GET		; GET NEXT BYTE
-	LD	(HL),A			; SAVE IN BUFFER
+	LD	(HL),E			; SAVE IN BUFFER
 	INC	HL			; INC BUF POINTER
 	POP	BC			; RESTORE BC
 	DJNZ	DSRTC_RDCLK1		; LOOP IF NOT DONE
@@ -380,34 +373,35 @@ DSRTC_RDCLK1:
 ; BURST WRITE CLOCK DATA FROM BUFFER AT HL
 ;
 DSRTC_WRCLK:
-	LD	C,$8E			; COMMAND = $8E TO WRITE CONTROL REGISTER
+	LD	E,$8E			; COMMAND = $8E TO WRITE CONTROL REGISTER
 	CALL	DSRTC_CMD		; SEND COMMAND
-	XOR	A			; $00 = UNPROTECT
+	LD	E,$00			; $00 = UNPROTECT
 	CALL	DSRTC_PUT		; SEND VALUE TO CONTROL REGISTER
 	CALL	DSRTC_END		; FINISH IT
 ;
-	LD	C,$BE			; COMMAND = $BE TO BURST WRITE CLOCK
+	LD	E,$BE			; COMMAND = $BE TO BURST WRITE CLOCK
 	CALL	DSRTC_CMD		; SEND COMMAND TO RTC
 	LD	B,DSRTC_BUFSIZ		; B IS LOOP COUNTER
 DSRTC_WRCLK1:
 	PUSH	BC			; PRESERVE BC
-	LD	A,(HL)			; GET NEXT BYTE TO WRITE
+	LD	E,(HL)			; GET NEXT BYTE TO WRITE
 	CALL	DSRTC_PUT		; PUT NEXT BYTE
 	INC	HL			; INC BUF POINTER
 	POP	BC			; RESTORE BC
 	DJNZ	DSRTC_WRCLK1		; LOOP IF NOT DONE
-	LD	A,$80			; ADD CONTROL REG BYTE, $80 = PROTECT ON
+	LD	E,$80			; ADD CONTROL REG BYTE, $80 = PROTECT ON
 	CALL	DSRTC_PUT		; WRITE REQUIRED 8TH BYTE
 	JP	DSRTC_END		; FINISH IT
 ;
-#IF ((DSRTCMODE == DSRTCMODE_STD) | (DSRTCMODE == DSRTCMODE_SC126))
-;
-; SEND COMMAND IN C TO RTC
+; SEND COMMAND IN E TO RTC
 ;   ALL RTC SEQUENCES MUST CALL THIS FIRST TO SEND THE RTC COMMAND.
-;   THE COMMAND IS SENT VIA A PUT.  CE AND CLK ARE LEFT HIGH!  THIS
+;   THE COMMAND IS SENT VIA A PUT.  CE AND CLK ARE LEFT ASSERTED!  THIS
 ;   IS INTENTIONAL BECAUSE WHEN THE CLOCK IS LOWERED, THE FIRST BIT
 ;   WILL BE PRESENTED TO READ (IN THE CASE OF A READ CMD).
 ;
+;   N.B. REGISTER A CONTAINS WORKING VALUE OF LATCH PORT AND MUST NOT
+;   BE MODIFIED BETWEEN CALLS TO DSRTC_CMD, DSRTC_PUT, AND DSRTC_GET.
+;
 ;   0) ASSUME ALL LINES UNDEFINED AT ENTRY
 ;   1) DEASSERT ALL LINES (CE, RD, CLOCK, & DATA)
 ;   2) WAIT 1US
@@ -416,19 +410,22 @@ DSRTC_WRCLK1:
 ;   5) PUT COMMAND
 ;
 DSRTC_CMD:
-	LD	A,DSRTC_RESET		; QUIESCENT STATE
-	OUT	(DSRTC_BASE),A		; WRITE TO RTC PORT
+	LD	A,(RTCVAL)		; INIT A WITH QUIESCENT STATE
+	OUT	(DSRTC_BASE),A		; WRITE TO PORT
 	CALL	DLY2			; DELAY 2 * 27 T-STATES
-	XOR	DSRTC_CE		; NOW SET CE HIGH
+#IF (DSRTCMODE == DSRTCMODE_MFPIC)
+	AND	~DSRTC_CE		; ASSERT CE (LOW)
+#ELSE
+	OR	DSRTC_CE		; ASSERT CE (HIGH)
+#ENDIF
 	OUT	(DSRTC_BASE),A		; WRITE TO RTC PORT
 	CALL	DLY2			; DELAY 2 * 27 T-STATES
-	LD	A,C			; LOAD COMMAND
 	CALL	DSRTC_PUT		; WRITE IT
 	RET
 ;
-; WRITE BYTE IN A TO THE RTC
-;   WRITE BYTE IN A TO THE RTC.  CE IS IMPLICITY ASSERTED AT
-;   THE START.  CE AND CLK ARE LEFT HIGH AT THE END IN CASE
+; WRITE BYTE IN E TO THE RTC
+;   WRITE BYTE IN E TO THE RTC.  CE IS IMPLICITY ASSERTED AT
+;   THE START.  CE AND CLK ARE LEFT ASSERTED AT THE END IN CASE
 ;   NEXT ACTION IS A READ.
 ;
 ;   0) ASSUME ENTRY WITH CE HI, OTHERS UNDEFINED
@@ -442,135 +439,36 @@ DSRTC_CMD:
 ;
 DSRTC_PUT:
 	LD	B,8			; LOOP FOR 8 BITS
-	LD	C,A			; SAVE THE WORKING VALUE
-DSRTC_PUT1:
-	LD	A,DSRTC_RESET | DSRTC_CE	; SET CLOCK LOW
-	OUT	(DSRTC_BASE),A		; DO IT
-	CALL	DLY1			; DELAY 27 T-STATES
-	LD	A,C			; RECOVER WORKING VALUE
-	RRCA				; ROTATE NEXT BIT TO SEND INTO BIT 7
-	LD	C,A			; SAVE WORKING VALUE
-	AND	%10000000		; ISOLATE THE DATA BIT
-	OR	DSRTC_RESET | DSRTC_CE		; KEEP CE HIGH
-	OUT	(DSRTC_BASE),A		; ASSERT DATA BIT ON BUS
-	OR	DSRTC_CLK		; SET CLOCK HI
-	OUT	(DSRTC_BASE),A		; DO IT
-	CALL	DLY1			; DELAY 27 T-STATES
-	DJNZ	DSRTC_PUT1		; LOOP IF NOT DONE
-	RET
-;
-; READ BYTE FROM RTC, RETURN VALUE IN A
-;   READ THE NEXT BYTE FROM THE RTC INTO A.  CE IS IMPLICITLY
-;   ASSERTED AT THE START.  CE AND CLK ARE LEFT HIGH AT
-;   THE END.  CLOCK *MUST* BE LEFT HIGH FROM DSRTC_CMD!
-;
-;   0) ASSUME ENTRY WITH CE HI, OTHERS UNDEFINED
-;   1) SET RD HI AND CLOCK LOW
-;   3) WAIT 250NS (CLOCK PUTS DATA BIT ON BUS)
-;   4) READ DATA BIT
-;   5) SET CLOCK HI
-;   6) WAIT 250NS
-;   7) LOOP FOR 8 DATA BITS
-;   8) EXIT WITH CE,CLK,RD HI
-;
-DSRTC_GET:
-	LD	C,0			; INITIALIZE WORKING VALUE TO 0
-	LD	B,8			; LOOP FOR 8 BITS
-DSRTC_GET1:
-	LD	A,DSRTC_RESET | DSRTC_CE | DSRTC_RD	; SET CLK LO
-	OUT	(DSRTC_BASE),A		; WRITE TO RTC PORT
-	CALL	DLY2			; DELAY 2 * 27 T-STATES
-	IN	A,(DSRTC_BASE)		; READ THE RTC PORT
-	AND	%00000001		; ISOLATE THE DATA BIT
-	OR	C			; COMBINE WITH WORKING VALUE
-	RRCA				; ROTATE FOR NEXT BIT
-	LD	C,A			; SAVE WORKING VALUE
-	LD	A,DSRTC_RESET | DSRTC_CE | DSRTC_CLK | DSRTC_RD	; CLOCK BACK TO HI
-	OUT	(DSRTC_BASE),A		; WRITE TO RTC PORT
-	CALL	DLY1			; DELAY 27 T-STATES
-	DJNZ	DSRTC_GET1		; LOOP IF NOT DONE (13)
-	LD	A,C			; GET RESULT INTO A
-	RET
-;
-; COMPLETE A COMMAND SEQUENCE
-;   FINISHES UP A COMMAND SEQUENCE.
-;   DOES NOT DESTROY ANY REGISTERS.
-;
-;   1) SET ALL LINES LO
-;
-DSRTC_END:
-	PUSH	AF			; SAVE AF
-	LD	A,DSRTC_RESET		; QUIESCENT STATE
-	OUT	(DSRTC_BASE),A		; WRITE TO RTC PORT
-	POP	AF			; RESTORE AF
-	RET
-;
-#ENDIF
-;
 #IF (DSRTCMODE == DSRTCMODE_MFPIC)
-;
-;
-; SEND COMMAND IN C TO RTC
-;   ALL RTC SEQUENCES MUST CALL THIS FIRST TO SEND THE RTC COMMAND.
-;   THE COMMAND IS SENT VIA A PUT.  CE AND CLK ARE LEFT ACTIVE!  THIS
-;   IS INTENTIONAL BECAUSE WHEN THE CLOCK IS LOWERED, THE FIRST BIT
-;   WILL BE PRESENTED TO READ (IN THE CASE OF A READ CMD).
-;
-;   0) ASSUME ALL LINES UNDEFINED AT ENTRY
-;   1) DEASSERT ALL LINES (CE, RD, CLOCK, & DATA)
-;   2) WAIT 1US
-;   3) SET CE HI
-;   4) WAIT 1US
-;   5) PUT COMMAND
-;
-DSRTC_CMD:
-	;XOR	A			; ALL LINES LOW TO RESET
-	LD	A,DSRTC_RESET		; QUIESCENT STATE
-	OUT	(DSRTC_BASE),A		; WRITE TO RTC PORT
-	CALL	DLY2			; DELAY 2 * 27 T-STATES
-	XOR	DSRTC_CE		; NOW ASSERT CE
-	OUT	(DSRTC_BASE),A		; WRITE TO RTC PORT
-	CALL	DLY2			; DELAY 2 * 27 T-STATES
-	LD	A,C			; LOAD COMMAND
-	CALL	DSRTC_PUT		; WRITE IT
-	RET
-;
-; WRITE BYTE IN A TO THE RTC
-;   WRITE BYTE IN A TO THE RTC.  CE IS IMPLICITY ASSERTED AT
-;   THE START.  CE AND CLK ARE LEFT ASSERTED AT THE END IN CASE
-;   NEXT ACTION IS A READ.
-;
-;   0) ASSUME ENTRY WITH CE ASSERTED, OTHERS UNDEFINED
-;   1) CLOCK -> LOW
-;   2) WAIT 250NS
-;   3) SET DATA ACCORDING TO BIT VALUE
-;   4) CLOCK -> HIGH
-;   5) WAIT 250NS (CLOCK READS DATA BIT FROM BUS)
-;   6) LOOP FOR 8 DATA BITS
-;   7) EXIT WITH CE AND CLOCK ASSERTED
-;
-DSRTC_PUT:
-	LD	B,8			; LOOP FOR 8 BITS
-	LD	C,A			; SAVE THE WORKING VALUE
-	LD	A,DSRTC_RESET | DSRTC_WR | DSRTC_CLK	; MODE=WRITE, CLOCK ON, CE ACTIVE (0)
+	OR	DSRTC_WR		; SET WRITE MODE
+#ELSE
+	AND	~DSRTC_RD		; SET WRITE MODE
+#ENDIF
 DSRTC_PUT1:
-	XOR	DSRTC_CLK		; FLIP CLOCK OFF
+	AND	~DSRTC_CLK		; SET CLOCK LOW
 	OUT	(DSRTC_BASE),A		; DO IT
 	CALL	DLY1			; DELAY 27 T-STATES
+	
+#IF (DSRTCMODE == DSRTCMODE_MFPIC)
 	RRA				; PREP ACCUM TO GET DATA BIT IN CARRY
-	RR	C			; ROTATE NEXT BIT TO SEND INTO CARRY
+	RR	E			; ROTATE NEXT BIT TO SEND INTO CARRY
 	RLA				; ROTATE BITS BACK TO CORRECT POSTIIONS
+#ELSE
+	RLA				; PREP ACCUM TO GET DATA BIT IN CARRY
+	RR	E			; ROTATE NEXT BIT TO SEND INTO CARRY
+	RRA				; ROTATE BITS BACK TO CORRECT POSTIIONS
+#ENDIF	
 	OUT	(DSRTC_BASE),A		; ASSERT DATA BIT ON BUS
-	XOR	DSRTC_CLK		; FLIP CLOCK ON
-	OUT	(DSRTC_BASE),A		; DO IT, DATA BIT SENT ON RISING EDGE
+	OR	DSRTC_CLK		; SET CLOCK HI
+	OUT	(DSRTC_BASE),A		; DO IT
 	CALL	DLY1			; DELAY 27 T-STATES
 	DJNZ	DSRTC_PUT1		; LOOP IF NOT DONE
 	RET
 ;
-; READ BYTE FROM RTC, RETURN VALUE IN A
-;   READ THE NEXT BYTE FROM THE RTC INTO A.  CE IS IMPLICITLY
-;   ASSERTED AT THE START.  CE AND CLK ARE LEFT HIGH AT
-;   THE END.  CLOCK *MUST* BE LEFT HIGH FROM DSRTC_CMD!
+; READ BYTE FROM RTC, RETURN VALUE IN E
+;   READ THE NEXT BYTE FROM THE RTC INTO E.  CE IS IMPLICITLY
+;   ASSERTED AT THE START.  CE AND CLK ARE LEFT ASSERTED AT
+;   THE END.  CLOCK *MUST* BE LEFT ASSERTED FROM DSRTC_CMD!
 ;
 ;   0) ASSUME ENTRY WITH CE HI, OTHERS UNDEFINED
 ;   1) SET RD HI AND CLOCK LOW
@@ -582,38 +480,38 @@ DSRTC_PUT1:
 ;   8) EXIT WITH CE,CLK,RD HI
 ;
 DSRTC_GET:
-	LD	C,0			; INITIALIZE WORKING VALUE TO 0
+	LD	E,0			; INITIALIZE WORKING VALUE TO 0
 	LD	B,8			; LOOP FOR 8 BITS
-	LD	A,DSRTC_RESET | DSRTC_CLK	; MODE=READ, CLOCK ON, CE ACTIVE (0)
+#IF (DSRTCMODE == DSRTCMODE_MFPIC)
+	AND	~DSRTC_WR		; SET READ MODE
+#ELSE
+	OR	DSRTC_RD		; SET READ MODE
+#ENDIF
 DSRTC_GET1:
-	XOR	DSRTC_CLK		; FLIP CLOCK OFF
-	OUT	(DSRTC_BASE),A		; DO IT
-	CALL	DLY2			; DELAY 2 * 27 T-STATES
+	AND	~DSRTC_CLK		; SET CLK LO
+	OUT	(DSRTC_BASE),A		; WRITE TO RTC PORT
+	CALL	DLY1			; DELAY 2 * 27 T-STATES
+	PUSH	AF			; SAVE PORT VALUE
 	IN	A,(DSRTC_BASE)		; READ THE RTC PORT
 	RRA				; DATA BIT TO CARRY
-	RR	C			; SHIFT INTO WORKING VALUE
-	LD	A,DSRTC_RESET | DSRTC_CLK	; CLOCK ON
+	RR	E			; SHIFT INTO WORKING VALUE
+	POP	AF			; RESTORE PORT VALUE
+	OR	DSRTC_CLK		; CLOCK BACK TO HI
 	OUT	(DSRTC_BASE),A		; WRITE TO RTC PORT
 	CALL	DLY1			; DELAY 27 T-STATES
-	DJNZ	DSRTC_GET1		; LOOP IF NOT DONE
-	LD	A,C			; GET RESULT INTO A
+	DJNZ	DSRTC_GET1		; LOOP IF NOT DONE (13)
 	RET
 ;
 ; COMPLETE A COMMAND SEQUENCE
 ;   FINISHES UP A COMMAND SEQUENCE.
 ;   DOES NOT DESTROY ANY REGISTERS.
 ;
-;   1) BACK TO QUIESCENT STATE
+;   1) SET ALL LINES BACK TO QUIESCENT STATE
 ;
 DSRTC_END:
-	PUSH	AF			; SAVE AF
-	;XOR	A			; ALL LINES OFF TO CLEAN UP
-	LD	A,DSRTC_RESET		; QUIESCENT STATE
-	OUT	(DSRTC_BASE),A		; WRITE TO RTC PORT
-	POP	AF			; RESTORE AF
-	RET
-;
-#ENDIF
+	LD	A,(RTCVAL)		; INIT A WITH QUIESCENT STATE
+	OUT	(DSRTC_BASE),A		; WRITE TO PORT
+	RET				; RETURN
 ;
 ; WORKING VARIABLES
 ;

Source/HBIOS/hbios.asm

@@ -1343,6 +1343,15 @@ PSCNX	.EQU	$ + 1
   #ENDIF
 ;
 #ENDIF
+;
+#IF 0
+HB_SPDTST:
+	CALL	HB_CPUSPD		; CPU SPEED DETECTION
+	CALL	NEWLINE
+	LD	HL,(CB_CPUKHZ)
+	CALL	PRTD3M			; PRINT AS DECIMAL WITH 3 DIGIT MANTISSA
+	JR	HB_SPDTST
+#ENDIF
 ;
 	HB_EI				; INTERRUPTS SHOULD BE OK NOW
 ;
@@ -2819,42 +2828,39 @@ HB_CPUSPD:
 	RET	NZ
 ;
 HB_CPUSPD1:
-;	LD	B,8
-;HB_CPUSPDX:
-;	PUSH	BC
+#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RCZ180))
+	; USE MEM W/S = 2 AND I/O W/S = 3 FOR TEST
+	IN0	A,(Z180_DCNTL)
+	PUSH	AF
+	LD	A,$B0
+	;LD	A,$F0
+	OUT0	(Z180_DCNTL),A
+#ENDIF
 
 	; WAIT FOR AN INITIAL TICK TO ALIGN, THEN WAIT
 	; FOR SECOND TICK AND TO GET A FULL ONE SECOND LOOP COUNT
-
 	CALL	HB_RDSEC		; GET SECONDS
 	LD	(HB_CURSEC),A		; AND INIT CURSEC
 	CALL	HB_WAITSEC		; WAIT FOR SECONDS TICK
 	LD	(HB_CURSEC),A		; SAVE NEW VALUE
 	CALL	HB_WAITSEC		; WAIT FOR SECONDS TICK
-
-;	PUSH	DE
-;	POP	BC
-;	CALL	NEWLINE
-;	CALL	PRTHEXWORD
-
-;	POP	BC
-;	DJNZ	HB_CPUSPDX
+;
+#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RCZ180))
+	; RESTORE W/S SETTINGS FROM BEFORE TEST
+	POP	AF
+	OUT0	(Z180_DCNTL),A
+#ENDIF
 ;
 	LD	A,H
 	OR	L
 	RET	Z			; FAILURE, USE DEFAULT CPU SPEED
-
 ;
 	; MOVE LOOP COUNT TO HL
 	PUSH	DE
 	POP	HL
 ;
 	; TIMES 4 FOR CPU SPEED IN KHZ
-	RES	0,L			; GRANULARITY
-#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RCZ180))
-	SLA	L
-	RL	H
-#ENDIF
+;	RES	0,L			; GRANULARITY
 	SLA	L
 	RL	H
 	SLA	L
@@ -2873,48 +2879,47 @@ HB_WAITSEC:
 	; RETURN SECS VALUE IN A, LOOP COUNT IN DE
 	LD	DE,0			; INIT LOOP COUNTER
 HB_WAITSEC1:
+;
 #IF ((PLATFORM == PLT_SBC) | (PLATFORM == PLT_ZETA) | (PLATFORM == PLT_ZETA2) | (PLATFORM == PLT_RCZ80) | (PLATFORM == PLT_EZZ80))
 	; LOOP TARGET IS 4000 T-STATES, SO CPU FREQ IN KHZ = LOOP COUNT * 4
 	CALL	DLY32
-	CALL	DLY8
-	CALL	DLY2
-	JP	$ + 3			; 10 TSTATES
-	JP	$ + 3			; 10 TSTATES
-	JP	$ + 3			; 10 TSTATES
-	JP	$ + 3			; 10 TSTATES
-	NOP				; 4 TSTATES
+	CALL	DLY16
+	CALL	DLY1			; 27 TSTATES
+	SBC	HL,HL			; 15 TSTATES
+	SBC	HL,HL			; 15 TSTATES
+	INC	HL			; 6 TSTATES
+	INC	HL			; 6 TSTATES
 #ENDIF
-
+;
 #IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RCZ180))
-	; LOOP TARGET IS 8000 T-STATES, SO CPU FREQ IN KHZ = LOOP COUNT * 8
-	CALL	DLY32
-	CALL	DLY16
-	CALL	DLY8
-	CALL	DLY4
+	; LOOP TARGET IS 4000 T-STATES, SO CPU FREQ IN KHZ = LOOP COUNT * 4
 	CALL	DLY2
-	CALL	DLY1			; CALL (25TS) & RET (18TS) = 43TS
-	ADD	A,A			; 4 TSTATES
-	NOP				; 6 TSTATES
+	ADD	IX,BC			; 10 + 4 = 14 TSTATES
+	NOP				; 5 TSTATES
+	NOP				; 5 TSTATES
+	NOP				; 5 TSTATES
+	NOP				; 5 TSTATES
 #ENDIF
 ;
-	PUSH	DE
+	PUSH	DE			; SAVE COUNTER
 	CALL	HB_RDSEC		; GET SECONDS
-	POP	DE
+	POP	DE			; RESTORE COUNTER
 	INC	DE			; BUMP COUNTER
 	LD	HL,HB_CURSEC		; POINT TO COMP VALUE
 	CP	(HL)			; TEST FOR CHANGE
 	RET	NZ			; DONE IF TICK OCCURRED
-	LD	A,D			; CHECK HL
+	LD	A,D			; CHECK DE
 	OR	E			; ... FOR OVERFLOW
 	RET	Z			; TIMEOUT, SOMETHING IS WRONG
 	JR	HB_WAITSEC1		; LOOP
 ;
 HB_RDSEC:
 	; READ SECONDS BYTE INTO A
-	LD	C,$81			; SECONDS REGISTER
+	LD	E,$81			; SECONDS REGISTER
 	CALL	DSRTC_CMD		; SEND THE COMMAND
 	CALL	DSRTC_GET		; READ THE REGISTER
 	CALL	DSRTC_END		; FINISH IT
+	LD	A,E			; VALUE TO A
 	RET
 ;
 #ELSE
@@ -3716,6 +3721,8 @@ HB_TICKS	.FILL	4,0		; 32 BIT TICK COUNTER
 ;
 HB_CPUTYPE	.DB	0		; 0=Z80, 1=80180, 2=SL1960, 3=ASCI BRG
 ;
+RTCVAL		.DB	0		; SHADOW VALUE FOR RTC LATCH PORT
+;
 STR_BANNER	.DB	"RetroBrew HBIOS v", BIOSVER, ", ", TIMESTAMP, "$"
 STR_PLATFORM	.DB	PLATFORM_NAME, "$"
 STR_SWITCH	.DB	"*** Activating CRT Console ***$"

Source/HBIOS/sd.asm

@@ -82,7 +82,7 @@
 #IF (SDMODE == SDMODE_JUHA)		; JUHA MINI-BOARD
 SD_DEVCNT	.EQU	1		; NUMBER OF PHYSICAL UNITS (SOCKETS)
 SD_OPRREG	.EQU	RTC		; USES RTC LATCHES FOR OPERATION
-SD_OPRDEF	.EQU	%00000001	; QUIESCENT STATE???
+SD_OPRDEF	.EQU	%00000001	; QUIESCENT STATE
 SD_INPREG	.EQU	RTC		; INPUT REGISTER IS RTC
 SD_CS		.EQU	%00000100	; RTC:2 IS SELECT
 SD_CLK		.EQU	%00000010	; RTC:1 IS CLOCK
@@ -93,7 +93,7 @@ SD_DO		.EQU	%10000000	; RTC:7 IS DATA OUT (CARD -> CPU)
 #IF (SDMODE == SDMODE_N8)		; UNMODIFIED N8-2511
 SD_DEVCNT	.EQU	1		; NUMBER OF PHYSICAL UNITS (SOCKETS)
 SD_OPRREG	.EQU	RTC		; USES RTC LATCHES FOR OPERATION
-SD_OPRDEF	.EQU	%00000001	; QUIESCENT STATE???
+SD_OPRDEF	.EQU	%00000001	; QUIESCENT STATE
 SD_INPREG	.EQU	RTC		; INPUT REGISTER IS RTC
 SD_CS		.EQU	%00000100	; RTC:2 IS SELECT
 SD_CLK		.EQU	%00000010	; RTC:1 IS CLOCK
@@ -161,8 +161,8 @@ SD_TRDR		.EQU	Z180_TRDR
 #IF (SDMODE == SDMODE_SC126)		; SC126
 SD_DEVCNT	.EQU	1		; NUMBER OF PHYSICAL UNITS (SOCKETS)
 SD_OPRREG	.EQU	RTC		; USES RTC LATCHES FOR OPERATION
-SD_OPRDEF	.EQU	%00001101	; QUIESCENT STATE
-SD_CS		.EQU	%00000100	; RTC:2 IS SELECT
+SD_OPRDEF	.EQU	%00001100	; QUIESCENT STATE (DEASSERT /CS1 & /CS2)
+SD_CS		.EQU	%00000100	; RTC:2 IS SELECT FOR PRIMARY SPI CARD
 SD_CNTR		.EQU	Z180_CNTR
 SD_TRDR		.EQU	Z180_TRDR
 #ENDIF
@@ -257,6 +257,10 @@ SD_INIT:
 	PRTS(" IO=0x$")
 	LD	A,SD_OPRREG
 	CALL	PRTHEXBYTE
+;
+	LD	A,(RTCVAL)		; GET RTC PORT SHADOW VALUE
+	OR	SD_OPRDEF		; SET OUR BIT DEFAULTS
+	LD	(RTCVAL),A		; SAVE IT
 #ENDIF
 ;
 #IF (SDMODE == SDMODE_N8)
@@ -264,6 +268,10 @@ SD_INIT:
 	PRTS(" IO=0x$")
 	LD	A,SD_OPRREG
 	CALL	PRTHEXBYTE
+;
+	LD	A,(RTCVAL)		; GET RTC PORT SHADOW VALUE
+	OR	SD_OPRDEF		; SET OUR BIT DEFAULTS
+	LD	(RTCVAL),A		; SAVE IT
 #ENDIF
 ;
 #IF (SDMODE == SDMODE_CSIO)
@@ -280,6 +288,10 @@ SD_INIT:
 	PRTS(" TRDR=0x$")
 	LD	A,SD_TRDR
 	CALL	PRTHEXBYTE
+;
+	LD	A,(RTCVAL)		; GET RTC PORT SHADOW VALUE
+	OR	SD_OPRDEF		; SET OUR BIT DEFAULTS
+	LD	(RTCVAL),A		; SAVE IT
 #ENDIF
 ;
 #IF (SDMODE == SDMODE_PPI)
@@ -339,6 +351,10 @@ SD_INIT:
 	PRTS(" TRDR=0x$")
 	LD	A,SD_TRDR
 	CALL	PRTHEXBYTE
+;
+	LD	A,(RTCVAL)		; GET RTC PORT SHADOW VALUE
+	OR	SD_OPRDEF		; SET OUR BIT DEFAULTS
+	LD	(RTCVAL),A		; SAVE IT
 #ENDIF
 ;
 	CALL	SD_PROBE		; CHECK FOR HARDWARE
@@ -1320,27 +1336,27 @@ SD_DONE:
 ;
 SD_SETUP:
 ;
-#IF ((SDMODE == SDMODE_JUHA) | (SDMODE == SDMODE_N8) | (SDMODE == SDMODE_DSD))
-	LD	A,SD_OPRDEF
-	LD	(SD_OPRVAL),A
-	OUT	(SD_OPRREG),A
+#IF (SDMODE == SDMODE_PPI)
+	; PPISD IS DESIGNED TO CORESIDE ON THE SAME PARALLEL PORT
+	; AS A DSKY.  SEE DSKY.ASM FOR DETAILS.
+	LD	A,82H			; PPI PORT A=OUT, B=IN, C=OUT
+	OUT	(SD_PPIX),A
 #ENDIF
 ;
 #IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC126))
-	; CSIO SETUP
+	; CSIO SETUP FOR Z180 CSIO
 ;	LD	A,2			; 18MHz/20 <= 400kHz
 	LD	A,6			; ???
 	OUT0	(SD_CNTR),A
-	LD	A,SD_OPRDEF
+#ENDIF
+;
+#IF ((SDMODE == SDMODE_JUHA) | (SDMODE == SDMODE_N8) | (SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_SC126))
+	LD	A,(RTCVAL)
 	LD	(SD_OPRVAL),A
 	OUT	(SD_OPRREG),A
 #ENDIF
 ;
-#IF (SDMODE == SDMODE_PPI)
-	; PPISD IS DESIGNED TO CORESIDE ON THE SAME PARALLEL PORT
-	; AS A DSKY.  SEE DSKY.ASM FOR DETAILS.
-	LD	A,82H			; PPI PORT A=OUT, B=IN, C=OUT
-	OUT	(SD_PPIX),A
+#IF ((SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_DSD) | (SDMODE == SDMODE_PPI))
 	LD	A,SD_OPRDEF
 	LD	(SD_OPRVAL),A
 	OUT	(SD_OPRREG),A

Source/HBIOS/spk.asm

@@ -9,7 +9,7 @@ SPK_INIT:
 	LD	A,DSRTC_BASE
 	CALL	PRTHEXBYTE
 	CALL	SPK_BEEP
-	XOR		A
+	XOR	A
 	RET
 ;
 SPK_BEEP:
@@ -17,7 +17,8 @@ SPK_BEEP:
 	PUSH	HL
 	LD	HL,400			; CYCLES OF TONE
 	;LD	B,%00000100		; D2 MAPPED TO Q0
-	LD	A,DSRTC_RESET
+	;LD	A,DSRTC_RESET
+	LD	A,(RTCVAL)		; GET RTC PORT VALUE FROM SHADOW
 	OR	%00000100		; D2 MAPPED TO Q0
 	LD	B,A
 SPK_BEEP1:

Source/HBIOS/std.asm

@@ -90,7 +90,6 @@ MID_FD111	.EQU	9
 DSRTCMODE_NONE	.EQU	0		; NO DSRTC
 DSRTCMODE_STD	.EQU	1		; ORIGINAL DSRTC CIRCUIT (SBC, ZETA, MK4)
 DSRTCMODE_MFPIC	.EQU	2		; MF/PIC VARIANT
-DSRTCMODE_SC126	.EQU	3		; SC126 VARIANT
 ;
 ; SIO MODE SELECTIONS
 ;