mirror of https://github.com/wwarthen/RomWBW.git
Wayne Warthen
4 years ago
56 changed files with 341 additions and 11804 deletions
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; Z3BASE - Dynamic Configuration |
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; |
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; ZCPR33 is copyright 1987 by Echelon, Inc. All rights reserved. End-user |
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; distribution and duplication permitted for non-commercial purposes only. |
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; Any commercial use of ZCPR33, defined as any situation where the duplicator |
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; recieves revenue by duplicating or distributing ZCPR33 by itself or in |
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; conjunction with any hardware or software product, is expressly prohibited |
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; unless authorized in writing by Echelon. |
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; |
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; This is a special version of Z3BASE, inspired by Joe Wright's Z3BASE |
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; for Z-Com. All segment addresses are automatically derived when the |
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; CCP equate is set. The benefit of this is that reconfiguration of the |
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; system after initial installation is greatly eased. |
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; |
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; Although this version of Z3BASE is being distributed with ZCPR 3.3, any |
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; previous version of Z3BASE can be used to assemble the Z33 Command |
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; Processor. No new symbols are needed. So, if you have an existing |
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; Z3BASE, go ahead and use it. |
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; |
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; Instructions: |
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; |
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; The user should first design the ZCPR3 memory usage using the chart |
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; below. (Echelon recommends the chart be filled out, even though it is |
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; not read by the assembler, so that your system will be self-documenting.) |
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; Then set the CCP equate for the beginning address of ZCPR3. Next, examine |
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; and change the SEGn equates which follow in the file to ensure that the |
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; system segments and buffers are placed at the proper addresses. |
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; |
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; This file has been customized for use with AMPRO hard disk systems. The |
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; target configuration has support for hard disks up to 49 Meg, extended |
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; IOP support, and 28-entry NDR. |
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; |
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;**************************************************************** |
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;* * |
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;* Z3BASE.LIB -- Base Addresses for ZCPR 3.3/Z-System * |
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;* * |
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;* Segments: * |
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;* * |
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;* Segment Function * |
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;* ------- -------- * |
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;* ZRDOS Echelon Z80 Replacement Disk Operating * |
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;* System, Version 1.7 (Public ZRDOS Plus) * |
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;* CBIOSZ Ampro-compatible BIOS with additional * |
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;* ZCPR3 initialization routines * |
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;* ZCPR3 Echelon Z80 Command Processor * |
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;* Replacement, Version 3.3 (ZCPR3) * |
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;* *.ENV All Environment Descriptors * |
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;* *.FCP All Flow Command Packages * |
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;* *.NDR All Named Directory Definition Files * |
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;* *.RCP All Resident Command Packages * |
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;* *.IOP All Input/Output Packages * |
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;* * |
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;* * |
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;* Memory Map of System (for CCP EQU 0BC00H): * |
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;* * |
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;* Address Range Size Function * |
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;* ------------- ------- -------- * |
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;* 0 - FF 256 b Standard CP/M Buffers except * |
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;* 100 - C3FF ~49 K Transient Program Area * |
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;* BC00 - C3FF 2K ZCPR 3.3 Command Processor * |
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;* C400 - D1FF 3.5 K ZRDOS * |
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;* D200 - EAFF 6.25K Ampro BIOS w/hard disk buffers * |
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;* EB00 - F2FF 2 K Resident Command Package * |
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;* F300 - F8FF 1.5 K Input/Output Package * |
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;* F900 - FAFF .5 K Flow Command Package * |
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;* FB00 - FB7F 128 b ZCPR3 Shell Stack * |
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;* FB80 - FBCF 80 b ZCPR3 Message Buffers * |
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;* FBD0 - FBF3 36 b ZCPR3 External FCB * |
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;* FBF4 - FBFE 11 b ZCPR3 External Path * |
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;* FBFF 1 b Wheel Byte * |
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;* FC00 - FDFF .5 K Memory-Based Named Directory * |
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;* FE00 - FEFF 256 b Environment Descriptor * |
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;* Bytes 00H-7FH: Z3 Parameters * |
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;* Bytes 80H-FFH: Z3 TCAP * |
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;* FF00 - FFCF 208 B Multiple Command Line Buffer * |
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;* FD00 - FFFF 48 b ZCPR3 External Stack * |
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;**************************************************************** |
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|
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FALSE equ 0 |
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TRUE equ NOT FALSE |
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|
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Z3REV EQU 33 ; ZCPR3 REV NUMBER |
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MSIZE EQU 54 ; SIZE OF CPM SYSTEM |
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|
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BASE EQU 0 |
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|
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CCP EQU 0BC00H ; ZCPR3 COMMAND PROCESSOR |
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|
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seg1 equ CCP+2F00h ; 11.75k from CCP to here (adding 2k ZCPR, |
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; 3.5k DOS, and 6.25k BIOS). |
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|
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; |
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; RCP definition. Set RCPS to 0 to eliminate RCP |
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; |
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|
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RCPS EQU 16 ; 16 128-byte Blocks (2K bytes) |
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|
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IF RCPS NE 0 |
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RCP EQU seg1 ; RESIDENT COMMAND PACKAGE |
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ELSE |
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RCP EQU 0 |
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ENDIF |
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|
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seg2 equ seg1+[rcps*128] |
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|
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; |
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; IOP definition. Set IOPS to 0 to eliminate IOP |
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; |
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IOPS EQU 12 ; 12 128-byte Blocks (1.5K bytes) |
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|
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IF IOPS NE 0 |
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IOP EQU seg2 ; REDIRECTABLE I/O PACKAGE |
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ELSE |
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IOP EQU 0 |
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ENDIF |
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|
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seg3 equ seg2+[iops*128] |
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|
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; |
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; FCP definition. Set FCPS to 0 to eliminate FCP |
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; |
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|
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FCPS EQU 4 ; 4 128-byte Blocks (0.5K bytes) |
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|
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IF FCPS NE 0 |
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fcp equ seg3 |
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ELSE |
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fcp equ 0 |
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ENDIF |
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|
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seg4 equ seg3+[fcps*128] |
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|
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; |
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; Shell Stack definition. Set SHSTKS to 0 to eliminate Shell Stack |
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; |
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|
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SHSTKS EQU 4 ; NUMBER OF SHSIZE-BYTE SHELL STACK ENTRIES |
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SHSIZE EQU 32 ; SIZE OF A SHELL STACK ENTRY |
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; (STACK SIZE = SHSTKS * SHSIZE) |
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IF SHSTKS NE 0 |
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SHSTK EQU seg4 |
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ELSE |
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SHSTK EQU 0 |
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ENDIF |
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|
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seg5 equ seg4+[shstks*shsize] |
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|
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; |
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; The ZCPR3 Message Buffers are mandatory for ZCPR 3.3. |
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; |
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Z3MSG EQU seg5 ; ZCPR3 MESSAGE BUFFER |
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|
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seg6 equ seg5+80 |
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|
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; |
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; The ZCPR3 External FCB is mandatory for ZCPR 3.3. |
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; |
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|
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EXTFCB EQU seg6 ; ZCPR3 EXTERNAL FCB |
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seg7 equ seg6+36 |
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|
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; |
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; The Path is mandatory for ZCPR 3.3. No more than 5 path elements can be |
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; used with this Z3BASE.LIB file. |
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; |
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|
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EXPATH EQU seg7 ; EXTERNAL PATH |
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EXPATHS EQU 5 ; 5 2-byte Path Elements |
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; (PATH SIZE = EXPATHS*2 + 1) |
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|
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seg8 equ seg7+[expaths*2]+1 |
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|
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; |
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; The ZCPR3 Wheel Byte is mandatory for ZCPR 3.3. |
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; |
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|
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Z3WHL EQU seg8 ; WHEEL BYTE ADDRESS |
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seg9 equ seg8+1 |
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|
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; |
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; ZCPR3 Named Directory Buffer definition. Set Z3NDIRS to 0 to eliminate |
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; the named directory buffer. If Z3NDIRS is changed, also change the seg10 |
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; equate below. |
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; |
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Z3NDIRS EQU 28 ; 28 18-byte Named Directory Elements permitted |
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; (NDIR SIZE = Z3NDIRS*18 + 1 for trailing 0) |
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IF Z3NDIRS NE 0 |
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Z3NDIR EQU seg9 ; ZCPR3 NAMED DIRECTORY AREA |
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ELSE |
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Z3NDIR EQU 0 |
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ENDIF |
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|
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seg10 equ seg9+512 ; add 512 for 28-entry NDR |
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; add 256 for 14-entry NDR ("standard") |
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; add 0 if Z3NDIRS is set to 0 |
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|
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; |
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; The ZCPR3 External Environment Descriptor is mandatory for ZCPR 3.3. |
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; Echelon recommends you work this out so that your ENV begins at address |
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; FE00h, but this is only a recommendation and not mandatory. |
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; |
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|
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Z3ENV EQU seg10 ; ENVIRONMENT DESCRIPTORS |
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Z3ENVS EQU 2 ; SIZE OF ENVIRONMENT DESCRIPTOR IN 128-BYTE BLOCKS |
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seg11 equ seg10+[z3envs*128] |
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; |
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; The ZCPR3 External Command Line Buffer is mandatory for ZCPR 3.3. |
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; |
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Z3CL EQU seg11 ; ZCPR3 COMMAND LINE BUFFER |
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Z3CLS EQU 208 ; SIZE OF COMMAND LINE BUFFER |
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seg12 equ seg11+z3cls |
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|
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; |
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; The ZCPR3 External Stack is mandatory for ZCPR 3.3. |
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; |
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EXTSTK EQU seg12 ; ZCPR3 EXTERNAL STACK |
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|
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; end of Z3BASE.LIB |
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@ -1,384 +0,0 @@ |
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;:::::::::::::::::::::::::::::::::::::::::::::::********************** |
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; B/P BIOS Configuration and Equate File. ** System Dependant ** |
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; - Retro-Brew boards /w RomWBW HBIOS - ********************** |
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; Setup for a Non-banked, internal HBIOS proxy System |
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; Custom tailor your system here. |
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; |
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; 02 May 18 - changes made to conform with HBIOS v 2.9.1p2 WW+LN |
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; 04 Sep 16 - Mods for RomWBW V 2.8 WW+LN |
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; 30 Apr 15 - changes made to conform with v 2.7.2 of RomWBW WW+LN |
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; 17 Jan 14 - Initial N8VEM release WW+LN |
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; 30 Aug 01 - Cleaned up for GPL release. HFB |
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; 11 May 97 - Added GIDE and adjusted HD equates. HFB |
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; 5 Jan 97 - Reformatted to Standard. HFB |
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; 10 Jun 96 - Initial Test Release. HFB |
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;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::: |
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; BIOS Configuration Equates and Macros |
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|
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DATE MACRO |
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DEFB '02 Aug 21' ; Date of this version |
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ENDM |
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AUTOCL MACRO |
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DEFB 8,'ZEX ZSTN',0 ; Autostart command line |
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ENDM |
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|
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;--- Basic System and Z-System Section --- |
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|
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MOVCPM EQU NO ; Integrate into MOVCPM "type" loader? |
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IF MOVCPM |
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VERS EQU 13H ; Version number in BCD (Hex) (Major/Minor) |
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ELSE |
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VERS EQU 21H ; Version number w/Device Swapping permitted |
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ENDIF |
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BANKED EQU NO ; Is this a banked BIOS? |
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ZSDOS2 EQU NO ; Yes = Banked Dos, No = CP/M 2.2 Compatible |
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INROM EQU NO ; Alternate bank in ROM? |
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MHZ EQU 18 ; Set to Speed in MHZ (6/9/12/16/18/24) |
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FASTWB EQU YES ; Yes if restoring CPR from banked RAM |
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; ..No if restoring from Drive A |
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Z3 EQU YES ; Include ZCPR init code? |
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HAVIOP EQU NO ; Include IOP code into Jump table? |
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INTPXY EQU YES ; YES to use internal HBIOS proxy |
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; and load Proxy as part of BPBIOS. |
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; NO to use HBIOS Proxy in high RAM |
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; (already loaded) |
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IF INTPXY |
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; YES load Proxy as part of BPBIOS. |
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MEMTOP EQU 0FFE0H - 1 ; Reserve memory above this for HBIOS |
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; interface (32 bytes) |
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ELSE |
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; NO use HBIOS Proxy in high RAM |
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; (already loaded) |
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HBLOC EQU 0FE00H ; Location of HBIOS proxy (if used) |
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MEMTOP EQU HBLOC - 1 ; Reserve memory above this for HBIOS |
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ENDIF |
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|
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;--- Memory configuration Section --- (Expansion Memory configured here) |
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|
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IBMOVS EQU NO ; Yes = Inter-bank Moves allowed (Z180/64180) |
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; No = Include Common RAM transfer buffer |
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|
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;--- Character Device Section --- |
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MORDEV EQU NO ; YES = Include any extra Char Device Drivers |
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; NO = Only use the 4 defined Char Devices |
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|
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QSIZE EQU 32 ; size of interrupt typeahead buffers (if used) |
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; ..must be 2^n with n<8 |
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RTSCTS EQU no ; Include RTS/CTS code on Serial Outputs? |
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XONOFF EQU no ; Include Xon/Xoff handshaking in Serial lines? |
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|
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;--- Clock and Time Section --- |
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|
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CLOCK EQU YES ; Include ZSDOS Clock Driver Code? |
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CLKSET EQU YES ; Allow Clock Sets? (Error if No) |
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|
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;--- Floppy Diskette Section --- |
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FLPYDSK EQU NO ; YES = Make Floppy-Disk Code, NO = No code made |
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|
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BIOERM EQU yes ; Print BIOS error messages? |
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CALCSK EQU YES ; Calculate skew table? |
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AUTOSL EQU YES ; Auto select floppy formats? |
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; If AUTOSL=True, the next two are active... |
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FDDMA EQU no ; Use DMA Control for Floppy Drive Transfers? |
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FLOPYH EQU no ; Include "Hi-Density" Floppy Formats? |
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FLOPY8 EQU no ; Include 8" Floppy Formats? |
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MORDPB EQU NO ; Include additional Floppy DPB Formats? |
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|
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;;--- RAM Disk Section --- |
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; |
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;RAMDSK EQU YES ; YES = Make RAM-Disk Code, NO = No code made |
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|
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;--- Hard Disk Section --- |
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|
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HARDDSK EQU YES ; YES = Add Hard-disk Code, NO = Floppy Only |
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; (Pick 1 of 3 options below) |
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HBDSK EQU YES ; YES = Use HBIOS Disk Driver |
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HDDMA EQU NO ; Use DMA-Controlled Hard Disk Data Transfers? |
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; (DMA not implemented for GIDE) |
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UNIT_0 EQU YES ; Hard Disk Physical Unit 1 |
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UNIT_1 EQU YES ; Hard Disk Physical Unit 2 |
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UNIT_2 EQU YES ; Hard Disk Physical Unit 3 |
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|
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;--- Logical Drive Section --- |
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; |
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; Set each of these equates for the drive and partition complement of |
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; your system. Set equates to no if drive exists or is wanted. |
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|
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DRV_A EQU yes ; A is always RAMDSK on HBIOS Device 0. |
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DRV_B EQU yes ; B is always ROMDSK on HBIOS Device 1. |
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DRV_C EQU yes |
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DRV_D EQU yes |
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DRV_E EQU yes ; Default is C-J are Hard Disk Slices |
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DRV_F EQU yes ; on the first hard drive (room for |
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DRV_G EQU yes ; up to 8 Slices provided) e.g. CF card. |
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DRV_H EQU yes |
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DRV_I EQU yes |
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DRV_J EQU yes |
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DRV_K EQU yes ; Default is K-N are Hard Disk Slices |
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DRV_L EQU yes ; on a second hard drive (room for up to |
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DRV_M EQU yes ; 4 Slices provided) e.g. SD card |
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DRV_N EQU yes |
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if FLPYDSK |
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DRV_O EQU yes ; O & P are floppies |
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DRV_P EQU yes |
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else |
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DRV_O EQU no ; O & P are floppies |
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DRV_P EQU no |
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endif |
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|
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;========== Configuration Unique Equates =========== |
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;>>>>>>>>>>>>>>>>>>>>>>>>>>> W A R N I N G <<<<<<<<<<<<<<<<<<<<<<<<<<<<< |
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;>>> Do NOT Alter these unless you KNOW what you're doing <<< |
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;>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>><<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< |
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|
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REFRSH EQU NO ; Set to NO for only Static RAM, needed for |
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; systems with dynamic RAMs. |
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NOWAIT EQU NO ; Set to NO to use configured Wait States in |
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; Hard Disk Driver. Yes to eliminate Waits. |
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|
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;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
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; For Z-180/HD64180 systems, The Bank numbers should reflect Physical |
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; memory in 32k increments. In SBC V1&2, Zeta and Simh, RAM occupies the |
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; first 512k (16 32k banks). The upper 32k bank is fixed as the last 32k |
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; of 512k. HBIOS occupies bank 1. The upper |
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; memory bounds (BNKU, BNK3 and BNKM) should be set for your configuration. |
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|
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BNK0 EQU BID_USR ; First TPA Bank (switched in/out) 40000H |
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BNK1 EQU BID_HB ; Second TPA Bank (Common Bank) 48000H |
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BNK2 EQU BID_SYS ; System Bank (BIOS, DOS, CPR) 50000H |
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BNKU EQU 00H ; User Area Bank 58000H |
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; (set to 0 to disable) |
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BNK3 EQU BID_RAMD ; First Bank for RAM disk 60000H |
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BNKM EQU BID_RAMM ; Maximum Bank # F8000H |
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; With both on-board RAMs only (MEM1 or MEM2), |
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; the maximum Bank number is 11 (0BH). |
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|
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IF NO ; REMOVE CODE - NOT NEEDED WITH HBIOS makes a |
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; nice resource for Z180 programing in general |
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;=========== CPU-dependent Equates, Zilog Z-180/Hitachi HD64180 ========== |
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|
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CNTLA0 EQU 00H ; Control Port ASCI 0 |
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CNTLA1 EQU 01H ; Control Port ASCI 1 |
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STAT0 EQU 04H ; Serial port 0 Status |
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STAT1 EQU 05H ; Serial port 1 Status |
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TDR0 EQU 06H ; Serial port 0 Output Data |
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TDR1 EQU 07H ; Serial port 1 Output Data |
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RDR0 EQU 08H ; Serial port 0 Input Data |
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RDR1 EQU 09H ; Serial Port 1 Input Data |
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CNTR EQU 0AH ; HD64180 Counter port |
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TMDR0L EQU 0CH ; HD64180 DMA channel reg (low) |
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TMDR0H EQU 0DH ; HD64180 DMA channel reg (hi) |
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RLDR0L EQU 0EH ; CTC0 Reload Count, Low |
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RLDR0H EQU 0FH ; CTC0 Reload Count, High |
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TCR EQU 10H ; Interrupt Control Register |
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TMDR1L EQU 14H ; Timer Data Reg Ch1 (Low) |
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TMDR1H EQU 15H ; Timer Data Reg Ch1 (High) |
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RLDR1L EQU 16H ; Timer Reload Reg Ch1 (Low) |
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RLDR1H EQU 17H ; Timer Reload Reg Ch1 (High) |
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FRC EQU 18H ; Free-Running Counter |
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CCR EQU 1FH ; CPU Control Register (ZS8180/Z80182) |
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SAR0L EQU 20H ; DMA Channel 0 Register start (8 ports) |
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MAR1L EQU 28H ; DMA Channel 1 Register start (8 ports) |
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DSTAT EQU 30H ; DMA Status/Control port |
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DMODE EQU 31H ; DMA Mode Control port |
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DCNTL EQU 32H ; DMA/WAIT Control Register |
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IL EQU 33H ; Interrupt Segment Register |
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ITC EQU 34H ; Interrupt/Trap Control Register |
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RCR EQU 36H ; HD64180 Refresh Control register |
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CBR EQU 38H ; MMU Common Base Register |
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BBR EQU 39H ; MMU Bank Base Register |
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CBAR EQU 3AH ; MMU Common/Bank Area Register |
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OMCR EQU 3EH ; Operation Mode Control Reg |
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ICR EQU 3FH ; I/O Control Register |
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|
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; Some bit definitions used with the Z-180 on-chip peripherals: |
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|
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TDRE EQU 02H ; ACSI Transmitter Buffer Empty |
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RDRF EQU 80H ; ACSI Received Character available |
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|
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;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
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; Extended Features of Z80182 for P112 |
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|
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WSGCS EQU 0D8H ; Wait-State Generator CS |
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ENH182 EQU 0D9H ; Z80182 Enhancements Register |
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PINMUX EQU 0DFH ; Interrupt Edge/Pin Mux Register |
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RAMUBR EQU 0E6H ; RAM End Boundary |
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RAMLBR EQU 0E7H ; RAM Start Boundary |
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ROMBR EQU 0E8H ; ROM Boundary |
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FIFOCTL EQU 0E9H ; FIFO Control Register |
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RTOTC EQU 0EAH ; RX Time-Out Time Constant |
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TTOTC EQU 0EBH ; TX Time-Out Time Constant |
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FCR EQU 0ECH ; FIFO Register |
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SCR EQU 0EFH ; System Pin Control |
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RBR EQU 0F0H ; MIMIC RX Buffer Register (R) |
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THR EQU 0F0H ; MIMIN TX Holding Register (W) |
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IER EQU 0F1H ; Interrupt Enable Register |
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LCR EQU 0F3H ; Line Control Register |
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MCR EQU 0F4H ; Modem Control Register |
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LSR EQU 0F5H ; Line Status Register |
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MDMSR EQU 0F6H ; Modem Status Register |
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MSCR EQU 0F7H ; MIMIC Scratch Register |
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DLATL EQU 0F8H ; Divisor Latch (Low) |
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DLATM EQU 0F9H ; Divisor Latch (High) |
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TTCR EQU 0FAH ; TX Time Constant |
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RTCR EQU 0FBH ; RX Time Constant |
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IVEC EQU 0FCH ; MIMIC Interrupt Vector |
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MIMIE EQU 0FDH ; MIMIC Interrupt Enable Register |
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IUSIP EQU 0FEH ; MIMIC Interrupt Under-Service Register |
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MMCR EQU 0FFH ; MIMIC Master Control Register |
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|
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; Z80182 PIO Registers |
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|
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DDRA EQU 0EDH ; Data Direction Register A |
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DRA EQU 0EEH ; Port A Data |
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DDRB EQU 0E4H ; Data Direction Register B |
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DRB EQU 0E5H ; Data B Data |
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DDRC EQU 0DDH ; Data Direction Register C |
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DRC EQU 0DEH ; Data C Data |
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|
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;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
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; ESCC Registers on Z80182 |
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|
|||
SCCACNT EQU 0E0H ; ESCC Control Channel A |
|||
SCCAD EQU 0E1H ; ESCC Data Channel A |
|||
SCCBCNT EQU 0E2H ; ESCC Control Channel B |
|||
SCCBD EQU 0E3H ; ESCC Data Channel B |
|||
|
|||
; [E]SCC Internal Register Definitions |
|||
|
|||
RR0 EQU 00H |
|||
RR1 EQU 01H |
|||
RR2 EQU 02H |
|||
RR3 EQU 03H |
|||
RR6 EQU 06H |
|||
RR7 EQU 07H |
|||
RR10 EQU 0AH |
|||
RR12 EQU 0CH |
|||
RR13 EQU 0DH |
|||
RR15 EQU 0FH |
|||
|
|||
WR0 EQU 00H |
|||
WR1 EQU 01H |
|||
WR2 EQU 02H |
|||
WR3 EQU 03H |
|||
WR4 EQU 04H |
|||
WR5 EQU 05H |
|||
WR6 EQU 06H |
|||
WR7 EQU 07H |
|||
WR9 EQU 09H |
|||
WR10 EQU 0AH |
|||
WR11 EQU 0BH |
|||
WR12 EQU 0CH |
|||
WR13 EQU 0DH |
|||
WR14 EQU 0EH |
|||
WR15 EQU 0FH |
|||
|
|||
; FDC37C665/6 Parallel Port in Standard AT Mode |
|||
|
|||
DPORT EQU 8CH ; Data Port |
|||
SPORT EQU 8DH ; Status Port |
|||
CPORT EQU 8EH ; Control Port |
|||
|
|||
; FDC37C665/6 Configuration Control (access internal registers) |
|||
|
|||
CFCNTL EQU 90H ; Configuration control port |
|||
CFDATA EQU 91H ; Configuration data port |
|||
|
|||
; FDC37C665/6 Floppy Controller on P112 (Intel 80277 compatible) |
|||
|
|||
DCR EQU 92H ; Drive Control Register (Digital Output) |
|||
MSR EQU 94H ; Main Status Register |
|||
DR EQU 95H ; Data/Command Register |
|||
DRR EQU 97H ; Data Rate Register/Disk Changed Bit in B7 |
|||
|
|||
_DMA EQU 0A0H ; Diskette DMA Address |
|||
|
|||
; FDC37C665/6 Serial Port (National 16550 compatible) |
|||
|
|||
_RBR EQU 68H ;R Receiver Buffer |
|||
_THR EQU 68H ;W Transmit Holding Reg |
|||
_IER EQU 69H ;RW Interrupt-Enable Reg |
|||
_IIR EQU 6AH ;R Interrupt Ident. Reg |
|||
_FCR EQU 6AH ;W FIFO Control Reg |
|||
_LCR EQU 6BH ;RW Line Control Reg |
|||
_MCR EQU 6CH ;RW Modem Control Reg |
|||
_LSR EQU 6DH ;RW Line Status Reg |
|||
_MMSR EQU 6EH ;RW Modem Status Reg |
|||
_SCR EQU 6FH ;N/A Scratch Reg. (not avail in XT) |
|||
_DDL EQU 68H ;RW Divisor LSB | wih DLAB |
|||
_DLM EQU 69H ;RW Divisor MSB | set High |
|||
|
|||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
|||
; Equates for the National DP8490/NCR 5380 Prototype SCSI controller |
|||
|
|||
IF HARDDSK |
|||
NCR EQU 40H ; Base of NCR 5380 |
|||
|
|||
; 5380 Chip Registers |
|||
|
|||
NCRDAT EQU NCR ; Current SCSI Data (Read) |
|||
; Output Data Register (Write) |
|||
NCRCMD EQU NCR+1 ; Initiator Command Register (Read/Write) |
|||
NCRMOD EQU NCR+2 ; Mode Register (Read/Write) |
|||
NCRTGT EQU NCR+3 ; Target Command Register (Read/Write) |
|||
NCRBUS EQU NCR+4 ; Current SCSI Bus Status (Read) |
|||
NCRST EQU NCR+5 ; Bus & Status Register (Read) |
|||
; Start DMA Send (Write) |
|||
NCRINT EQU NCR+7 ; Reset Parity/Interrupt (Read) |
|||
; Start DMA Initiator Receive (Write) |
|||
DMAACK EQU NCR+8 ; SCSI Dack IO Port (Read/Write) |
|||
|
|||
; Bit Assignments for NCR 5380 Ports as indicated |
|||
|
|||
B_ARST EQU 10000000B ; Assert *RST (NCRCMD) |
|||
B_AACK EQU 00010000B ; Assert *ACK (NCRCMD) |
|||
B_ASEL EQU 00000100B ; Assert *SEL (NCRCMD) |
|||
B_ABUS EQU 00000001B ; Assert *Data Bus (NCRCMD) |
|||
|
|||
B_BSY EQU 01000000B ; *Busy (NCRBUS) |
|||
B_REQ EQU 00100000B ; *Request (NCRBUS) |
|||
B_MSG EQU 00010000B ; *Message (NCRBUS) |
|||
B_CD EQU 00001000B ; *Command/Data (NCRBUS) |
|||
B_IO EQU 00000100B ; *I/O (NCRBUS) |
|||
B_SEL EQU 00000010B ; *Select (NCRBUS) |
|||
|
|||
B_PHAS EQU 00001000B ; Phase Match (NCRST) |
|||
B_BBSY EQU 00000100B ; Bus Busy (NCRST) |
|||
|
|||
B_MBSY EQU 00000100B ; Monitor Busy Flag (NCRMOD) |
|||
B_DMA EQU 00000010B ; DMA Mode of transfer (NCRMOD) |
|||
ENDIF ;harddsk |
|||
|
|||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
|||
; Equates reflecting GIDE Base address from Address Jumpers (if GIDE added) |
|||
; Set the base GIDE equate to the jumper setting on the GIDE board. |
|||
|
|||
IF IDE |
|||
GIDE EQU 50H ; Set base of 16 byte address range |
|||
|
|||
IDEDOR EQU GIDE+6 ; Digital Output Register |
|||
IDEDat EQU GIDE+8 ; IDE Data Register (16-bit wide) |
|||
IDEErr EQU GIDE+9 ; IDE Error Register |
|||
IDESCnt EQU GIDE+0AH ; IDE Sector Count Register |
|||
IDESNum EQU GIDE+0BH ; IDE Sector Number Register |
|||
IDECLo EQU GIDE+0CH ; IDE Cylinder Number (Low) |
|||
IDECHi EQU GIDE+0DH ; IDE Cylinter Number (High) |
|||
IDESDH EQU GIDE+0EH ; IDE S-Drive-Head Register |
|||
IDECmd EQU GIDE+0FH ; IDE Command/Status Register |
|||
|
|||
CMDHOM EQU 10H ; Home Drive Heads |
|||
CMDRD EQU 20H ; Read Sector Command (w/retry) |
|||
CMDWR EQU 30H ; Write Sector Command (w/retry) |
|||
CMDVER EQU 40H ; Verify Sector(s) Command (w/retry) |
|||
CMDFMT EQU 50H ; Format Track Command |
|||
CMDDIAG EQU 90H ; Execute Diagnostics Command |
|||
CMDINIT EQU 91H ; Initialize Drive Params Command |
|||
CMDPW0 EQU 0E0H ; Low Range of Power Control Commands |
|||
CMDPW3 EQU 0E3H ; High Range of Power Control Commands |
|||
CMDPWQ EQU 0E5H ; Power Status Query Command |
|||
CMDID EQU 0ECH ; Read Drive Ident Data Command |
|||
ENDIF ;ide |
|||
;=================== End Unique Equates ======================= |
|||
ENDIF ; REMOVE CODE |
|||
@ -1,383 +0,0 @@ |
|||
;:::::::::::::::::::::::::::::::::::::::::::::::********************** |
|||
; B/P BIOS Configuration and Equate File. ** System Dependant ** |
|||
; - Retro-Brew boards /w RomWBW HBIOS - ********************** |
|||
; Setup for banked bios & internal HBIOS proxy System |
|||
; Custom tailor your system here. |
|||
; |
|||
; 02 May 18 - changes made to conform with HBIOS v 2.9.1p2 WW+LN |
|||
; 04 Sep 16 - Mods for RomWBW V 2.8 WW+LN |
|||
; 30 Apr 15 - changes made to conform with v 2.7.2 of RomWBW WW+LN |
|||
; 17 Jan 14 - Initial N8VEM release WW+LN |
|||
; 30 Aug 01 - Cleaned up for GPL release. HFB |
|||
; 11 May 97 - Added GIDE and adjusted HD equates. HFB |
|||
; 5 Jan 97 - Reformatted to Standard. HFB |
|||
; 10 Jun 96 - Initial Test Release. HFB |
|||
;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::: |
|||
; BIOS Configuration Equates and Macros |
|||
|
|||
DATE MACRO |
|||
DEFB '02 Aug 21' ; Date of this version |
|||
ENDM |
|||
AUTOCL MACRO |
|||
DEFB 8,'ZEX ZSTN',0 ; Autostart command line |
|||
ENDM |
|||
|
|||
;--- Basic System and Z-System Section --- |
|||
|
|||
MOVCPM EQU NO ; Integrate into MOVCPM "type" loader? |
|||
IF MOVCPM |
|||
VERS EQU 13H ; Version number in BCD (Hex) (Major/Minor) |
|||
ELSE |
|||
VERS EQU 21H ; Version number w/Device Swapping permitted |
|||
ENDIF |
|||
BANKED EQU YES ; Is this a banked BIOS? |
|||
ZSDOS2 EQU NO ; Yes = Banked Dos, No = CP/M 2.2 Compatible |
|||
INROM EQU NO ; Alternate bank in ROM? |
|||
MHZ EQU 18 ; Set to Speed in MHZ (6/9/12/16/18/24) |
|||
FASTWB EQU YES ; Yes if restoring CPR from banked RAM |
|||
; ..No if restoring from Drive A |
|||
Z3 EQU YES ; Include ZCPR init code? |
|||
HAVIOP EQU NO ; Include IOP code into Jump table? |
|||
INTPXY EQU YES ; YES to use internal HBIOS Mini proxy |
|||
; and load Proxy as part of BPBIOS. |
|||
; NO to use HBIOS Proxy in high RAM |
|||
; (already loaded) |
|||
IF INTPXY |
|||
; YES load Proxy as part of BPBIOS. |
|||
MEMTOP EQU 0FFE0H - 1 ; Reserve memory above this for HBIOS |
|||
; interface (32 bytes) |
|||
ELSE |
|||
; NO use HBIOS Proxy in high RAM |
|||
; (already loaded) |
|||
HBLOC EQU 0FE00H ; Location of HBIOS proxy (if used) |
|||
MEMTOP EQU HBLOC - 1 ; Reserve memory above this for HBIOS |
|||
ENDIF |
|||
|
|||
;--- Memory configuration Section --- (Expansion Memory configured here) |
|||
|
|||
IBMOVS EQU NO ; Yes = Inter-bank Moves allowed (Z180/64180) |
|||
; No = Include Common RAM transfer buffer |
|||
|
|||
;--- Character Device Section --- |
|||
|
|||
MORDEV EQU NO ; YES = Include any extra Char Device Drivers |
|||
; NO = Only use the 4 defined Char Devices |
|||
|
|||
QSIZE EQU 32 ; size of interrupt typeahead buffers (if used) |
|||
; ..must be 2^n with n<8 |
|||
RTSCTS EQU no ; Include RTS/CTS code on Serial Outputs? |
|||
XONOFF EQU no ; Include Xon/Xoff handshaking in Serial lines? |
|||
|
|||
;--- Clock and Time Section --- |
|||
|
|||
CLOCK EQU YES ; Include ZSDOS Clock Driver Code? |
|||
CLKSET EQU YES ; Allow Clock Sets? (Error if No) |
|||
|
|||
;--- Floppy Diskette Section --- |
|||
|
|||
FLPYDSK EQU NO ; YES = Make Floppy-Disk Code, NO = No code made |
|||
BIOERM EQU yes ; Print BIOS error messages? |
|||
CALCSK EQU YES ; Calculate skew table? |
|||
AUTOSL EQU YES ; Auto select floppy formats? |
|||
; If AUTOSL=True, the next two are active... |
|||
FDDMA EQU no ; Use DMA Control for Floppy Drive Transfers? |
|||
FLOPYH EQU no ; Include "Hi-Density" Floppy Formats? |
|||
FLOPY8 EQU no ; Include 8" Floppy Formats? |
|||
MORDPB EQU NO ; Include additional Floppy DPB Formats? |
|||
|
|||
;;--- RAM Disk Section --- |
|||
; |
|||
;RAMDSK EQU YES ; YES = Make RAM-Disk Code, NO = No code made |
|||
|
|||
;--- Hard Disk Section --- |
|||
|
|||
HARDDSK EQU YES ; YES = Add Hard-disk Code, NO = Floppy Only |
|||
; (Pick 1 of 3 options below) |
|||
HBDSK EQU YES ; YES = Use HBIOS Disk Driver |
|||
HDDMA EQU NO ; Use DMA-Controlled Hard Disk Data Transfers? |
|||
; (DMA not implemented for GIDE) |
|||
UNIT_0 EQU YES ; Hard Disk Physical Unit 1 |
|||
UNIT_1 EQU YES ; Hard Disk Physical Unit 2 |
|||
UNIT_2 EQU YES ; Hard Disk Physical Unit 3 |
|||
|
|||
;--- Logical Drive Section --- |
|||
; |
|||
; Set each of these equates for the drive and partition complement of |
|||
; your system. Set equates to no if drive exists or is wanted. |
|||
|
|||
DRV_A EQU yes ; A is always RAMDSK on HBIOS Device 0. |
|||
DRV_B EQU yes ; B is always ROMDSK on HBIOS Device 1. |
|||
DRV_C EQU yes |
|||
DRV_D EQU yes |
|||
DRV_E EQU yes ; Default is C-J are Hard Disk Slices |
|||
DRV_F EQU yes ; on the first hard drive (room for |
|||
DRV_G EQU yes ; up to 8 Slices provided) e.g. CF card. |
|||
DRV_H EQU yes |
|||
DRV_I EQU yes |
|||
DRV_J EQU yes |
|||
DRV_K EQU yes ; Default is K-N are Hard Disk Slices |
|||
DRV_L EQU yes ; on a second hard drive (room for up to |
|||
DRV_M EQU yes ; 4 Slices provided) e.g. SD card |
|||
DRV_N EQU yes |
|||
if FLPYDSK |
|||
DRV_O EQU yes ; O & P are floppies |
|||
DRV_P EQU yes |
|||
else |
|||
DRV_O EQU no ; O & P are floppies |
|||
DRV_P EQU no |
|||
endif |
|||
|
|||
;========== Configuration Unique Equates =========== |
|||
;>>>>>>>>>>>>>>>>>>>>>>>>>>> W A R N I N G <<<<<<<<<<<<<<<<<<<<<<<<<<<<< |
|||
;>>> Do NOT Alter these unless you KNOW what you're doing <<< |
|||
;>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>><<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< |
|||
|
|||
REFRSH EQU NO ; Set to NO for only Static RAM, needed for |
|||
; systems with dynamic RAMs. |
|||
NOWAIT EQU NO ; Set to NO to use configured Wait States in |
|||
; Hard Disk Driver. Yes to eliminate Waits. |
|||
|
|||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
|||
; For Z-180/HD64180 systems, The Bank numbers should reflect Physical |
|||
; memory in 32k increments. In SBC V1&2, Zeta and Simh, RAM occupies the |
|||
; first 512k (16 32k banks). The upper 32k bank is fixed as the last 32k |
|||
; of 512k. HBIOS occupies bank 1. The upper |
|||
; memory bounds (BNKU, BNK3 and BNKM) should be set for your configuration. |
|||
|
|||
BNK0 EQU BID_USR ; First TPA Bank (switched in/out) 40000H |
|||
BNK1 EQU BID_HB ; Second TPA Bank (Common Bank) 48000H |
|||
BNK2 EQU BID_SYS ; System Bank (BIOS, DOS, CPR) 50000H |
|||
BNKU EQU 00H ; User Area Bank 58000H |
|||
; (set to 0 to disable) |
|||
BNK3 EQU BID_RAMD ; First Bank for RAM disk 60000H |
|||
BNKM EQU BID_RAMM ; Maximum Bank # F8000H |
|||
; With both on-board RAMs only (MEM1 or MEM2), |
|||
; the maximum Bank number is 11 (0BH). |
|||
|
|||
IF NO ; REMOVE CODE - NOT NEEDED WITH HBIOS makes a |
|||
; nice resource for Z180 programing in general |
|||
;=========== CPU-dependent Equates, Zilog Z-180/Hitachi HD64180 ========== |
|||
|
|||
CNTLA0 EQU 00H ; Control Port ASCI 0 |
|||
CNTLA1 EQU 01H ; Control Port ASCI 1 |
|||
STAT0 EQU 04H ; Serial port 0 Status |
|||
STAT1 EQU 05H ; Serial port 1 Status |
|||
TDR0 EQU 06H ; Serial port 0 Output Data |
|||
TDR1 EQU 07H ; Serial port 1 Output Data |
|||
RDR0 EQU 08H ; Serial port 0 Input Data |
|||
RDR1 EQU 09H ; Serial Port 1 Input Data |
|||
CNTR EQU 0AH ; HD64180 Counter port |
|||
TMDR0L EQU 0CH ; HD64180 DMA channel reg (low) |
|||
TMDR0H EQU 0DH ; HD64180 DMA channel reg (hi) |
|||
RLDR0L EQU 0EH ; CTC0 Reload Count, Low |
|||
RLDR0H EQU 0FH ; CTC0 Reload Count, High |
|||
TCR EQU 10H ; Interrupt Control Register |
|||
TMDR1L EQU 14H ; Timer Data Reg Ch1 (Low) |
|||
TMDR1H EQU 15H ; Timer Data Reg Ch1 (High) |
|||
RLDR1L EQU 16H ; Timer Reload Reg Ch1 (Low) |
|||
RLDR1H EQU 17H ; Timer Reload Reg Ch1 (High) |
|||
FRC EQU 18H ; Free-Running Counter |
|||
CCR EQU 1FH ; CPU Control Register (ZS8180/Z80182) |
|||
SAR0L EQU 20H ; DMA Channel 0 Register start (8 ports) |
|||
MAR1L EQU 28H ; DMA Channel 1 Register start (8 ports) |
|||
DSTAT EQU 30H ; DMA Status/Control port |
|||
DMODE EQU 31H ; DMA Mode Control port |
|||
DCNTL EQU 32H ; DMA/WAIT Control Register |
|||
IL EQU 33H ; Interrupt Segment Register |
|||
ITC EQU 34H ; Interrupt/Trap Control Register |
|||
RCR EQU 36H ; HD64180 Refresh Control register |
|||
CBR EQU 38H ; MMU Common Base Register |
|||
BBR EQU 39H ; MMU Bank Base Register |
|||
CBAR EQU 3AH ; MMU Common/Bank Area Register |
|||
OMCR EQU 3EH ; Operation Mode Control Reg |
|||
ICR EQU 3FH ; I/O Control Register |
|||
|
|||
; Some bit definitions used with the Z-180 on-chip peripherals: |
|||
|
|||
TDRE EQU 02H ; ACSI Transmitter Buffer Empty |
|||
RDRF EQU 80H ; ACSI Received Character available |
|||
|
|||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
|||
; Extended Features of Z80182 for P112 |
|||
|
|||
WSGCS EQU 0D8H ; Wait-State Generator CS |
|||
ENH182 EQU 0D9H ; Z80182 Enhancements Register |
|||
PINMUX EQU 0DFH ; Interrupt Edge/Pin Mux Register |
|||
RAMUBR EQU 0E6H ; RAM End Boundary |
|||
RAMLBR EQU 0E7H ; RAM Start Boundary |
|||
ROMBR EQU 0E8H ; ROM Boundary |
|||
FIFOCTL EQU 0E9H ; FIFO Control Register |
|||
RTOTC EQU 0EAH ; RX Time-Out Time Constant |
|||
TTOTC EQU 0EBH ; TX Time-Out Time Constant |
|||
FCR EQU 0ECH ; FIFO Register |
|||
SCR EQU 0EFH ; System Pin Control |
|||
RBR EQU 0F0H ; MIMIC RX Buffer Register (R) |
|||
THR EQU 0F0H ; MIMIN TX Holding Register (W) |
|||
IER EQU 0F1H ; Interrupt Enable Register |
|||
LCR EQU 0F3H ; Line Control Register |
|||
MCR EQU 0F4H ; Modem Control Register |
|||
LSR EQU 0F5H ; Line Status Register |
|||
MDMSR EQU 0F6H ; Modem Status Register |
|||
MSCR EQU 0F7H ; MIMIC Scratch Register |
|||
DLATL EQU 0F8H ; Divisor Latch (Low) |
|||
DLATM EQU 0F9H ; Divisor Latch (High) |
|||
TTCR EQU 0FAH ; TX Time Constant |
|||
RTCR EQU 0FBH ; RX Time Constant |
|||
IVEC EQU 0FCH ; MIMIC Interrupt Vector |
|||
MIMIE EQU 0FDH ; MIMIC Interrupt Enable Register |
|||
IUSIP EQU 0FEH ; MIMIC Interrupt Under-Service Register |
|||
MMCR EQU 0FFH ; MIMIC Master Control Register |
|||
|
|||
; Z80182 PIO Registers |
|||
|
|||
DDRA EQU 0EDH ; Data Direction Register A |
|||
DRA EQU 0EEH ; Port A Data |
|||
DDRB EQU 0E4H ; Data Direction Register B |
|||
DRB EQU 0E5H ; Data B Data |
|||
DDRC EQU 0DDH ; Data Direction Register C |
|||
DRC EQU 0DEH ; Data C Data |
|||
|
|||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
|||
; ESCC Registers on Z80182 |
|||
|
|||
SCCACNT EQU 0E0H ; ESCC Control Channel A |
|||
SCCAD EQU 0E1H ; ESCC Data Channel A |
|||
SCCBCNT EQU 0E2H ; ESCC Control Channel B |
|||
SCCBD EQU 0E3H ; ESCC Data Channel B |
|||
|
|||
; [E]SCC Internal Register Definitions |
|||
|
|||
RR0 EQU 00H |
|||
RR1 EQU 01H |
|||
RR2 EQU 02H |
|||
RR3 EQU 03H |
|||
RR6 EQU 06H |
|||
RR7 EQU 07H |
|||
RR10 EQU 0AH |
|||
RR12 EQU 0CH |
|||
RR13 EQU 0DH |
|||
RR15 EQU 0FH |
|||
|
|||
WR0 EQU 00H |
|||
WR1 EQU 01H |
|||
WR2 EQU 02H |
|||
WR3 EQU 03H |
|||
WR4 EQU 04H |
|||
WR5 EQU 05H |
|||
WR6 EQU 06H |
|||
WR7 EQU 07H |
|||
WR9 EQU 09H |
|||
WR10 EQU 0AH |
|||
WR11 EQU 0BH |
|||
WR12 EQU 0CH |
|||
WR13 EQU 0DH |
|||
WR14 EQU 0EH |
|||
WR15 EQU 0FH |
|||
|
|||
; FDC37C665/6 Parallel Port in Standard AT Mode |
|||
|
|||
DPORT EQU 8CH ; Data Port |
|||
SPORT EQU 8DH ; Status Port |
|||
CPORT EQU 8EH ; Control Port |
|||
|
|||
; FDC37C665/6 Configuration Control (access internal registers) |
|||
|
|||
CFCNTL EQU 90H ; Configuration control port |
|||
CFDATA EQU 91H ; Configuration data port |
|||
|
|||
; FDC37C665/6 Floppy Controller on P112 (Intel 80277 compatible) |
|||
|
|||
DCR EQU 92H ; Drive Control Register (Digital Output) |
|||
MSR EQU 94H ; Main Status Register |
|||
DR EQU 95H ; Data/Command Register |
|||
DRR EQU 97H ; Data Rate Register/Disk Changed Bit in B7 |
|||
|
|||
_DMA EQU 0A0H ; Diskette DMA Address |
|||
|
|||
; FDC37C665/6 Serial Port (National 16550 compatible) |
|||
|
|||
_RBR EQU 68H ;R Receiver Buffer |
|||
_THR EQU 68H ;W Transmit Holding Reg |
|||
_IER EQU 69H ;RW Interrupt-Enable Reg |
|||
_IIR EQU 6AH ;R Interrupt Ident. Reg |
|||
_FCR EQU 6AH ;W FIFO Control Reg |
|||
_LCR EQU 6BH ;RW Line Control Reg |
|||
_MCR EQU 6CH ;RW Modem Control Reg |
|||
_LSR EQU 6DH ;RW Line Status Reg |
|||
_MMSR EQU 6EH ;RW Modem Status Reg |
|||
_SCR EQU 6FH ;N/A Scratch Reg. (not avail in XT) |
|||
_DDL EQU 68H ;RW Divisor LSB | wih DLAB |
|||
_DLM EQU 69H ;RW Divisor MSB | set High |
|||
|
|||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
|||
; Equates for the National DP8490/NCR 5380 Prototype SCSI controller |
|||
|
|||
IF HARDDSK |
|||
NCR EQU 40H ; Base of NCR 5380 |
|||
|
|||
; 5380 Chip Registers |
|||
|
|||
NCRDAT EQU NCR ; Current SCSI Data (Read) |
|||
; Output Data Register (Write) |
|||
NCRCMD EQU NCR+1 ; Initiator Command Register (Read/Write) |
|||
NCRMOD EQU NCR+2 ; Mode Register (Read/Write) |
|||
NCRTGT EQU NCR+3 ; Target Command Register (Read/Write) |
|||
NCRBUS EQU NCR+4 ; Current SCSI Bus Status (Read) |
|||
NCRST EQU NCR+5 ; Bus & Status Register (Read) |
|||
; Start DMA Send (Write) |
|||
NCRINT EQU NCR+7 ; Reset Parity/Interrupt (Read) |
|||
; Start DMA Initiator Receive (Write) |
|||
DMAACK EQU NCR+8 ; SCSI Dack IO Port (Read/Write) |
|||
|
|||
; Bit Assignments for NCR 5380 Ports as indicated |
|||
|
|||
B_ARST EQU 10000000B ; Assert *RST (NCRCMD) |
|||
B_AACK EQU 00010000B ; Assert *ACK (NCRCMD) |
|||
B_ASEL EQU 00000100B ; Assert *SEL (NCRCMD) |
|||
B_ABUS EQU 00000001B ; Assert *Data Bus (NCRCMD) |
|||
|
|||
B_BSY EQU 01000000B ; *Busy (NCRBUS) |
|||
B_REQ EQU 00100000B ; *Request (NCRBUS) |
|||
B_MSG EQU 00010000B ; *Message (NCRBUS) |
|||
B_CD EQU 00001000B ; *Command/Data (NCRBUS) |
|||
B_IO EQU 00000100B ; *I/O (NCRBUS) |
|||
B_SEL EQU 00000010B ; *Select (NCRBUS) |
|||
|
|||
B_PHAS EQU 00001000B ; Phase Match (NCRST) |
|||
B_BBSY EQU 00000100B ; Bus Busy (NCRST) |
|||
|
|||
B_MBSY EQU 00000100B ; Monitor Busy Flag (NCRMOD) |
|||
B_DMA EQU 00000010B ; DMA Mode of transfer (NCRMOD) |
|||
ENDIF ;harddsk |
|||
|
|||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
|||
; Equates reflecting GIDE Base address from Address Jumpers (if GIDE added) |
|||
; Set the base GIDE equate to the jumper setting on the GIDE board. |
|||
|
|||
IF IDE |
|||
GIDE EQU 50H ; Set base of 16 byte address range |
|||
|
|||
IDEDOR EQU GIDE+6 ; Digital Output Register |
|||
IDEDat EQU GIDE+8 ; IDE Data Register (16-bit wide) |
|||
IDEErr EQU GIDE+9 ; IDE Error Register |
|||
IDESCnt EQU GIDE+0AH ; IDE Sector Count Register |
|||
IDESNum EQU GIDE+0BH ; IDE Sector Number Register |
|||
IDECLo EQU GIDE+0CH ; IDE Cylinder Number (Low) |
|||
IDECHi EQU GIDE+0DH ; IDE Cylinter Number (High) |
|||
IDESDH EQU GIDE+0EH ; IDE S-Drive-Head Register |
|||
IDECmd EQU GIDE+0FH ; IDE Command/Status Register |
|||
|
|||
CMDHOM EQU 10H ; Home Drive Heads |
|||
CMDRD EQU 20H ; Read Sector Command (w/retry) |
|||
CMDWR EQU 30H ; Write Sector Command (w/retry) |
|||
CMDVER EQU 40H ; Verify Sector(s) Command (w/retry) |
|||
CMDFMT EQU 50H ; Format Track Command |
|||
CMDDIAG EQU 90H ; Execute Diagnostics Command |
|||
CMDINIT EQU 91H ; Initialize Drive Params Command |
|||
CMDPW0 EQU 0E0H ; Low Range of Power Control Commands |
|||
CMDPW3 EQU 0E3H ; High Range of Power Control Commands |
|||
CMDPWQ EQU 0E5H ; Power Status Query Command |
|||
CMDID EQU 0ECH ; Read Drive Ident Data Command |
|||
ENDIF ;ide |
|||
;=================== End Unique Equates ======================= |
|||
ENDIF ; REMOVE CODE |
|||
@ -1,384 +0,0 @@ |
|||
;:::::::::::::::::::::::::::::::::::::::::::::::********************** |
|||
; B/P BIOS Configuration and Equate File. ** System Dependant ** |
|||
; - Retro-Brew boards /w RomWBW HBIOS - ********************** |
|||
; Setup for a Non-banked, internal HBIOS proxy System |
|||
; Custom tailor your system here. |
|||
; |
|||
; 02 May 18 - changes made to conform with HBIOS v 2.9.1p2 WW+LN |
|||
; 04 Sep 16 - Mods for RomWBW V 2.8 WW+LN |
|||
; 30 Apr 15 - changes made to conform with v 2.7.2 of RomWBW WW+LN |
|||
; 17 Jan 14 - Initial N8VEM release WW+LN |
|||
; 30 Aug 01 - Cleaned up for GPL release. HFB |
|||
; 11 May 97 - Added GIDE and adjusted HD equates. HFB |
|||
; 5 Jan 97 - Reformatted to Standard. HFB |
|||
; 10 Jun 96 - Initial Test Release. HFB |
|||
;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::: |
|||
; BIOS Configuration Equates and Macros |
|||
|
|||
DATE MACRO |
|||
DEFB '02 Aug 21' ; Date of this version |
|||
ENDM |
|||
AUTOCL MACRO |
|||
DEFB 8,'ZEX ZSTN',0 ; Autostart command line |
|||
ENDM |
|||
|
|||
;--- Basic System and Z-System Section --- |
|||
|
|||
MOVCPM EQU NO ; Integrate into MOVCPM "type" loader? |
|||
IF MOVCPM |
|||
VERS EQU 13H ; Version number in BCD (Hex) (Major/Minor) |
|||
ELSE |
|||
VERS EQU 21H ; Version number w/Device Swapping permitted |
|||
ENDIF |
|||
BANKED EQU NO ; Is this a banked BIOS? |
|||
ZSDOS2 EQU NO ; Yes = Banked Dos, No = CP/M 2.2 Compatible |
|||
INROM EQU NO ; Alternate bank in ROM? |
|||
MHZ EQU 18 ; Set to Speed in MHZ (6/9/12/16/18/24) |
|||
FASTWB EQU YES ; Yes if restoring CPR from banked RAM |
|||
; ..No if restoring from Drive A |
|||
Z3 EQU YES ; Include ZCPR init code? |
|||
HAVIOP EQU NO ; Include IOP code into Jump table? |
|||
INTPXY EQU YES ; YES to use internal HBIOS proxy |
|||
; and load Proxy as part of BPBIOS. |
|||
; NO to use HBIOS Proxy in high RAM |
|||
; (already loaded) |
|||
IF INTPXY |
|||
; YES load Proxy as part of BPBIOS. |
|||
MEMTOP EQU 0FFE0H - 1 ; Reserve memory above this for HBIOS |
|||
; interface (32 bytes) |
|||
ELSE |
|||
; NO use HBIOS Proxy in high RAM |
|||
; (already loaded) |
|||
HBLOC EQU 0FE00H ; Location of HBIOS proxy (if used) |
|||
MEMTOP EQU HBLOC - 1 ; Reserve memory above this for HBIOS |
|||
ENDIF |
|||
|
|||
;--- Memory configuration Section --- (Expansion Memory configured here) |
|||
|
|||
IBMOVS EQU NO ; Yes = Inter-bank Moves allowed (Z180/64180) |
|||
; No = Include Common RAM transfer buffer |
|||
|
|||
;--- Character Device Section --- |
|||
|
|||
MORDEV EQU NO ; YES = Include any extra Char Device Drivers |
|||
; NO = Only use the 4 defined Char Devices |
|||
|
|||
QSIZE EQU 32 ; size of interrupt typeahead buffers (if used) |
|||
; ..must be 2^n with n<8 |
|||
RTSCTS EQU no ; Include RTS/CTS code on Serial Outputs? |
|||
XONOFF EQU no ; Include Xon/Xoff handshaking in Serial lines? |
|||
|
|||
;--- Clock and Time Section --- |
|||
|
|||
CLOCK EQU YES ; Include ZSDOS Clock Driver Code? |
|||
CLKSET EQU YES ; Allow Clock Sets? (Error if No) |
|||
|
|||
;--- Floppy Diskette Section --- |
|||
|
|||
FLPYDSK EQU NO ; YES = Make Floppy-Disk Code, NO = No code made |
|||
|
|||
BIOERM EQU yes ; Print BIOS error messages? |
|||
CALCSK EQU YES ; Calculate skew table? |
|||
AUTOSL EQU YES ; Auto select floppy formats? |
|||
; If AUTOSL=True, the next two are active... |
|||
FDDMA EQU no ; Use DMA Control for Floppy Drive Transfers? |
|||
FLOPYH EQU no ; Include "Hi-Density" Floppy Formats? |
|||
FLOPY8 EQU no ; Include 8" Floppy Formats? |
|||
MORDPB EQU NO ; Include additional Floppy DPB Formats? |
|||
|
|||
;;--- RAM Disk Section --- |
|||
; |
|||
;RAMDSK EQU YES ; YES = Make RAM-Disk Code, NO = No code made |
|||
|
|||
;--- Hard Disk Section --- |
|||
|
|||
HARDDSK EQU YES ; YES = Add Hard-disk Code, NO = Floppy Only |
|||
; (Pick 1 of 3 options below) |
|||
HBDSK EQU YES ; YES = Use HBIOS Disk Driver |
|||
HDDMA EQU NO ; Use DMA-Controlled Hard Disk Data Transfers? |
|||
; (DMA not implemented for GIDE) |
|||
UNIT_0 EQU YES ; Hard Disk Physical Unit 1 |
|||
UNIT_1 EQU YES ; Hard Disk Physical Unit 2 |
|||
UNIT_2 EQU YES ; Hard Disk Physical Unit 3 |
|||
|
|||
;--- Logical Drive Section --- |
|||
; |
|||
; Set each of these equates for the drive and partition complement of |
|||
; your system. Set equates to no if drive exists or is wanted. |
|||
|
|||
DRV_A EQU yes ; A is always RAMDSK on HBIOS Device 0. |
|||
DRV_B EQU yes ; B is always ROMDSK on HBIOS Device 1. |
|||
DRV_C EQU yes |
|||
DRV_D EQU yes |
|||
DRV_E EQU yes ; Default is C-J are Hard Disk Slices |
|||
DRV_F EQU yes ; on the first hard drive (room for |
|||
DRV_G EQU yes ; up to 8 Slices provided) e.g. CF card. |
|||
DRV_H EQU yes |
|||
DRV_I EQU yes |
|||
DRV_J EQU yes |
|||
DRV_K EQU yes ; Default is K-N are Hard Disk Slices |
|||
DRV_L EQU yes ; on a second hard drive (room for up to |
|||
DRV_M EQU yes ; 4 Slices provided) e.g. SD card |
|||
DRV_N EQU yes |
|||
if FLPYDSK |
|||
DRV_O EQU yes ; O & P are floppies |
|||
DRV_P EQU yes |
|||
else |
|||
DRV_O EQU no ; O & P are floppies |
|||
DRV_P EQU no |
|||
endif |
|||
|
|||
;========== Configuration Unique Equates =========== |
|||
;>>>>>>>>>>>>>>>>>>>>>>>>>>> W A R N I N G <<<<<<<<<<<<<<<<<<<<<<<<<<<<< |
|||
;>>> Do NOT Alter these unless you KNOW what you're doing <<< |
|||
;>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>><<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< |
|||
|
|||
REFRSH EQU NO ; Set to NO for only Static RAM, needed for |
|||
; systems with dynamic RAMs. |
|||
NOWAIT EQU NO ; Set to NO to use configured Wait States in |
|||
; Hard Disk Driver. Yes to eliminate Waits. |
|||
|
|||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
|||
; For Z-180/HD64180 systems, The Bank numbers should reflect Physical |
|||
; memory in 32k increments. In SBC V1&2, Zeta and Simh, RAM occupies the |
|||
; first 512k (16 32k banks). The upper 32k bank is fixed as the last 32k |
|||
; of 512k. HBIOS occupies bank 1. The upper |
|||
; memory bounds (BNKU, BNK3 and BNKM) should be set for your configuration. |
|||
|
|||
BNK0 EQU BID_USR ; First TPA Bank (switched in/out) 40000H |
|||
BNK1 EQU BID_HB ; Second TPA Bank (Common Bank) 48000H |
|||
BNK2 EQU BID_SYS ; System Bank (BIOS, DOS, CPR) 50000H |
|||
BNKU EQU 00H ; User Area Bank 58000H |
|||
; (set to 0 to disable) |
|||
BNK3 EQU BID_RAMD ; First Bank for RAM disk 60000H |
|||
BNKM EQU BID_RAMM ; Maximum Bank # F8000H |
|||
; With both on-board RAMs only (MEM1 or MEM2), |
|||
; the maximum Bank number is 11 (0BH). |
|||
|
|||
IF NO ; REMOVE CODE - NOT NEEDED WITH HBIOS makes a |
|||
; nice resource for Z180 programing in general |
|||
;=========== CPU-dependent Equates, Zilog Z-180/Hitachi HD64180 ========== |
|||
|
|||
CNTLA0 EQU 00H ; Control Port ASCI 0 |
|||
CNTLA1 EQU 01H ; Control Port ASCI 1 |
|||
STAT0 EQU 04H ; Serial port 0 Status |
|||
STAT1 EQU 05H ; Serial port 1 Status |
|||
TDR0 EQU 06H ; Serial port 0 Output Data |
|||
TDR1 EQU 07H ; Serial port 1 Output Data |
|||
RDR0 EQU 08H ; Serial port 0 Input Data |
|||
RDR1 EQU 09H ; Serial Port 1 Input Data |
|||
CNTR EQU 0AH ; HD64180 Counter port |
|||
TMDR0L EQU 0CH ; HD64180 DMA channel reg (low) |
|||
TMDR0H EQU 0DH ; HD64180 DMA channel reg (hi) |
|||
RLDR0L EQU 0EH ; CTC0 Reload Count, Low |
|||
RLDR0H EQU 0FH ; CTC0 Reload Count, High |
|||
TCR EQU 10H ; Interrupt Control Register |
|||
TMDR1L EQU 14H ; Timer Data Reg Ch1 (Low) |
|||
TMDR1H EQU 15H ; Timer Data Reg Ch1 (High) |
|||
RLDR1L EQU 16H ; Timer Reload Reg Ch1 (Low) |
|||
RLDR1H EQU 17H ; Timer Reload Reg Ch1 (High) |
|||
FRC EQU 18H ; Free-Running Counter |
|||
CCR EQU 1FH ; CPU Control Register (ZS8180/Z80182) |
|||
SAR0L EQU 20H ; DMA Channel 0 Register start (8 ports) |
|||
MAR1L EQU 28H ; DMA Channel 1 Register start (8 ports) |
|||
DSTAT EQU 30H ; DMA Status/Control port |
|||
DMODE EQU 31H ; DMA Mode Control port |
|||
DCNTL EQU 32H ; DMA/WAIT Control Register |
|||
IL EQU 33H ; Interrupt Segment Register |
|||
ITC EQU 34H ; Interrupt/Trap Control Register |
|||
RCR EQU 36H ; HD64180 Refresh Control register |
|||
CBR EQU 38H ; MMU Common Base Register |
|||
BBR EQU 39H ; MMU Bank Base Register |
|||
CBAR EQU 3AH ; MMU Common/Bank Area Register |
|||
OMCR EQU 3EH ; Operation Mode Control Reg |
|||
ICR EQU 3FH ; I/O Control Register |
|||
|
|||
; Some bit definitions used with the Z-180 on-chip peripherals: |
|||
|
|||
TDRE EQU 02H ; ACSI Transmitter Buffer Empty |
|||
RDRF EQU 80H ; ACSI Received Character available |
|||
|
|||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
|||
; Extended Features of Z80182 for P112 |
|||
|
|||
WSGCS EQU 0D8H ; Wait-State Generator CS |
|||
ENH182 EQU 0D9H ; Z80182 Enhancements Register |
|||
PINMUX EQU 0DFH ; Interrupt Edge/Pin Mux Register |
|||
RAMUBR EQU 0E6H ; RAM End Boundary |
|||
RAMLBR EQU 0E7H ; RAM Start Boundary |
|||
ROMBR EQU 0E8H ; ROM Boundary |
|||
FIFOCTL EQU 0E9H ; FIFO Control Register |
|||
RTOTC EQU 0EAH ; RX Time-Out Time Constant |
|||
TTOTC EQU 0EBH ; TX Time-Out Time Constant |
|||
FCR EQU 0ECH ; FIFO Register |
|||
SCR EQU 0EFH ; System Pin Control |
|||
RBR EQU 0F0H ; MIMIC RX Buffer Register (R) |
|||
THR EQU 0F0H ; MIMIN TX Holding Register (W) |
|||
IER EQU 0F1H ; Interrupt Enable Register |
|||
LCR EQU 0F3H ; Line Control Register |
|||
MCR EQU 0F4H ; Modem Control Register |
|||
LSR EQU 0F5H ; Line Status Register |
|||
MDMSR EQU 0F6H ; Modem Status Register |
|||
MSCR EQU 0F7H ; MIMIC Scratch Register |
|||
DLATL EQU 0F8H ; Divisor Latch (Low) |
|||
DLATM EQU 0F9H ; Divisor Latch (High) |
|||
TTCR EQU 0FAH ; TX Time Constant |
|||
RTCR EQU 0FBH ; RX Time Constant |
|||
IVEC EQU 0FCH ; MIMIC Interrupt Vector |
|||
MIMIE EQU 0FDH ; MIMIC Interrupt Enable Register |
|||
IUSIP EQU 0FEH ; MIMIC Interrupt Under-Service Register |
|||
MMCR EQU 0FFH ; MIMIC Master Control Register |
|||
|
|||
; Z80182 PIO Registers |
|||
|
|||
DDRA EQU 0EDH ; Data Direction Register A |
|||
DRA EQU 0EEH ; Port A Data |
|||
DDRB EQU 0E4H ; Data Direction Register B |
|||
DRB EQU 0E5H ; Data B Data |
|||
DDRC EQU 0DDH ; Data Direction Register C |
|||
DRC EQU 0DEH ; Data C Data |
|||
|
|||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
|||
; ESCC Registers on Z80182 |
|||
|
|||
SCCACNT EQU 0E0H ; ESCC Control Channel A |
|||
SCCAD EQU 0E1H ; ESCC Data Channel A |
|||
SCCBCNT EQU 0E2H ; ESCC Control Channel B |
|||
SCCBD EQU 0E3H ; ESCC Data Channel B |
|||
|
|||
; [E]SCC Internal Register Definitions |
|||
|
|||
RR0 EQU 00H |
|||
RR1 EQU 01H |
|||
RR2 EQU 02H |
|||
RR3 EQU 03H |
|||
RR6 EQU 06H |
|||
RR7 EQU 07H |
|||
RR10 EQU 0AH |
|||
RR12 EQU 0CH |
|||
RR13 EQU 0DH |
|||
RR15 EQU 0FH |
|||
|
|||
WR0 EQU 00H |
|||
WR1 EQU 01H |
|||
WR2 EQU 02H |
|||
WR3 EQU 03H |
|||
WR4 EQU 04H |
|||
WR5 EQU 05H |
|||
WR6 EQU 06H |
|||
WR7 EQU 07H |
|||
WR9 EQU 09H |
|||
WR10 EQU 0AH |
|||
WR11 EQU 0BH |
|||
WR12 EQU 0CH |
|||
WR13 EQU 0DH |
|||
WR14 EQU 0EH |
|||
WR15 EQU 0FH |
|||
|
|||
; FDC37C665/6 Parallel Port in Standard AT Mode |
|||
|
|||
DPORT EQU 8CH ; Data Port |
|||
SPORT EQU 8DH ; Status Port |
|||
CPORT EQU 8EH ; Control Port |
|||
|
|||
; FDC37C665/6 Configuration Control (access internal registers) |
|||
|
|||
CFCNTL EQU 90H ; Configuration control port |
|||
CFDATA EQU 91H ; Configuration data port |
|||
|
|||
; FDC37C665/6 Floppy Controller on P112 (Intel 80277 compatible) |
|||
|
|||
DCR EQU 92H ; Drive Control Register (Digital Output) |
|||
MSR EQU 94H ; Main Status Register |
|||
DR EQU 95H ; Data/Command Register |
|||
DRR EQU 97H ; Data Rate Register/Disk Changed Bit in B7 |
|||
|
|||
_DMA EQU 0A0H ; Diskette DMA Address |
|||
|
|||
; FDC37C665/6 Serial Port (National 16550 compatible) |
|||
|
|||
_RBR EQU 68H ;R Receiver Buffer |
|||
_THR EQU 68H ;W Transmit Holding Reg |
|||
_IER EQU 69H ;RW Interrupt-Enable Reg |
|||
_IIR EQU 6AH ;R Interrupt Ident. Reg |
|||
_FCR EQU 6AH ;W FIFO Control Reg |
|||
_LCR EQU 6BH ;RW Line Control Reg |
|||
_MCR EQU 6CH ;RW Modem Control Reg |
|||
_LSR EQU 6DH ;RW Line Status Reg |
|||
_MMSR EQU 6EH ;RW Modem Status Reg |
|||
_SCR EQU 6FH ;N/A Scratch Reg. (not avail in XT) |
|||
_DDL EQU 68H ;RW Divisor LSB | wih DLAB |
|||
_DLM EQU 69H ;RW Divisor MSB | set High |
|||
|
|||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
|||
; Equates for the National DP8490/NCR 5380 Prototype SCSI controller |
|||
|
|||
IF HARDDSK |
|||
NCR EQU 40H ; Base of NCR 5380 |
|||
|
|||
; 5380 Chip Registers |
|||
|
|||
NCRDAT EQU NCR ; Current SCSI Data (Read) |
|||
; Output Data Register (Write) |
|||
NCRCMD EQU NCR+1 ; Initiator Command Register (Read/Write) |
|||
NCRMOD EQU NCR+2 ; Mode Register (Read/Write) |
|||
NCRTGT EQU NCR+3 ; Target Command Register (Read/Write) |
|||
NCRBUS EQU NCR+4 ; Current SCSI Bus Status (Read) |
|||
NCRST EQU NCR+5 ; Bus & Status Register (Read) |
|||
; Start DMA Send (Write) |
|||
NCRINT EQU NCR+7 ; Reset Parity/Interrupt (Read) |
|||
; Start DMA Initiator Receive (Write) |
|||
DMAACK EQU NCR+8 ; SCSI Dack IO Port (Read/Write) |
|||
|
|||
; Bit Assignments for NCR 5380 Ports as indicated |
|||
|
|||
B_ARST EQU 10000000B ; Assert *RST (NCRCMD) |
|||
B_AACK EQU 00010000B ; Assert *ACK (NCRCMD) |
|||
B_ASEL EQU 00000100B ; Assert *SEL (NCRCMD) |
|||
B_ABUS EQU 00000001B ; Assert *Data Bus (NCRCMD) |
|||
|
|||
B_BSY EQU 01000000B ; *Busy (NCRBUS) |
|||
B_REQ EQU 00100000B ; *Request (NCRBUS) |
|||
B_MSG EQU 00010000B ; *Message (NCRBUS) |
|||
B_CD EQU 00001000B ; *Command/Data (NCRBUS) |
|||
B_IO EQU 00000100B ; *I/O (NCRBUS) |
|||
B_SEL EQU 00000010B ; *Select (NCRBUS) |
|||
|
|||
B_PHAS EQU 00001000B ; Phase Match (NCRST) |
|||
B_BBSY EQU 00000100B ; Bus Busy (NCRST) |
|||
|
|||
B_MBSY EQU 00000100B ; Monitor Busy Flag (NCRMOD) |
|||
B_DMA EQU 00000010B ; DMA Mode of transfer (NCRMOD) |
|||
ENDIF ;harddsk |
|||
|
|||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
|||
; Equates reflecting GIDE Base address from Address Jumpers (if GIDE added) |
|||
; Set the base GIDE equate to the jumper setting on the GIDE board. |
|||
|
|||
IF IDE |
|||
GIDE EQU 50H ; Set base of 16 byte address range |
|||
|
|||
IDEDOR EQU GIDE+6 ; Digital Output Register |
|||
IDEDat EQU GIDE+8 ; IDE Data Register (16-bit wide) |
|||
IDEErr EQU GIDE+9 ; IDE Error Register |
|||
IDESCnt EQU GIDE+0AH ; IDE Sector Count Register |
|||
IDESNum EQU GIDE+0BH ; IDE Sector Number Register |
|||
IDECLo EQU GIDE+0CH ; IDE Cylinder Number (Low) |
|||
IDECHi EQU GIDE+0DH ; IDE Cylinter Number (High) |
|||
IDESDH EQU GIDE+0EH ; IDE S-Drive-Head Register |
|||
IDECmd EQU GIDE+0FH ; IDE Command/Status Register |
|||
|
|||
CMDHOM EQU 10H ; Home Drive Heads |
|||
CMDRD EQU 20H ; Read Sector Command (w/retry) |
|||
CMDWR EQU 30H ; Write Sector Command (w/retry) |
|||
CMDVER EQU 40H ; Verify Sector(s) Command (w/retry) |
|||
CMDFMT EQU 50H ; Format Track Command |
|||
CMDDIAG EQU 90H ; Execute Diagnostics Command |
|||
CMDINIT EQU 91H ; Initialize Drive Params Command |
|||
CMDPW0 EQU 0E0H ; Low Range of Power Control Commands |
|||
CMDPW3 EQU 0E3H ; High Range of Power Control Commands |
|||
CMDPWQ EQU 0E5H ; Power Status Query Command |
|||
CMDID EQU 0ECH ; Read Drive Ident Data Command |
|||
ENDIF ;ide |
|||
;=================== End Unique Equates ======================= |
|||
ENDIF ; REMOVE CODE |
|||
@ -1,383 +0,0 @@ |
|||
;:::::::::::::::::::::::::::::::::::::::::::::::********************** |
|||
; B/P BIOS Configuration and Equate File. ** System Dependant ** |
|||
; - Retro-Brew boards /w RomWBW HBIOS - ********************** |
|||
; Setup for banked bios & internal HBIOS proxy System |
|||
; Custom tailor your system here. |
|||
; |
|||
; 02 May 18 - changes made to conform with HBIOS v 2.9.1p2 WW+LN |
|||
; 04 Sep 16 - Mods for RomWBW V 2.8 WW+LN |
|||
; 30 Apr 15 - changes made to conform with v 2.7.2 of RomWBW WW+LN |
|||
; 17 Jan 14 - Initial N8VEM release WW+LN |
|||
; 30 Aug 01 - Cleaned up for GPL release. HFB |
|||
; 11 May 97 - Added GIDE and adjusted HD equates. HFB |
|||
; 5 Jan 97 - Reformatted to Standard. HFB |
|||
; 10 Jun 96 - Initial Test Release. HFB |
|||
;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::: |
|||
; BIOS Configuration Equates and Macros |
|||
|
|||
DATE MACRO |
|||
DEFB '02 Aug 21' ; Date of this version |
|||
ENDM |
|||
AUTOCL MACRO |
|||
DEFB 8,'ZEX ZSTN',0 ; Autostart command line |
|||
ENDM |
|||
|
|||
;--- Basic System and Z-System Section --- |
|||
|
|||
MOVCPM EQU NO ; Integrate into MOVCPM "type" loader? |
|||
IF MOVCPM |
|||
VERS EQU 13H ; Version number in BCD (Hex) (Major/Minor) |
|||
ELSE |
|||
VERS EQU 21H ; Version number w/Device Swapping permitted |
|||
ENDIF |
|||
BANKED EQU YES ; Is this a banked BIOS? |
|||
ZSDOS2 EQU NO ; Yes = Banked Dos, No = CP/M 2.2 Compatible |
|||
INROM EQU NO ; Alternate bank in ROM? |
|||
MHZ EQU 18 ; Set to Speed in MHZ (6/9/12/16/18/24) |
|||
FASTWB EQU YES ; Yes if restoring CPR from banked RAM |
|||
; ..No if restoring from Drive A |
|||
Z3 EQU YES ; Include ZCPR init code? |
|||
HAVIOP EQU NO ; Include IOP code into Jump table? |
|||
INTPXY EQU YES ; YES to use internal HBIOS Mini proxy |
|||
; and load Proxy as part of BPBIOS. |
|||
; NO to use HBIOS Proxy in high RAM |
|||
; (already loaded) |
|||
IF INTPXY |
|||
; YES load Proxy as part of BPBIOS. |
|||
MEMTOP EQU 0FFE0H - 1 ; Reserve memory above this for HBIOS |
|||
; interface (32 bytes) |
|||
ELSE |
|||
; NO use HBIOS Proxy in high RAM |
|||
; (already loaded) |
|||
HBLOC EQU 0FE00H ; Location of HBIOS proxy (if used) |
|||
MEMTOP EQU HBLOC - 1 ; Reserve memory above this for HBIOS |
|||
ENDIF |
|||
|
|||
;--- Memory configuration Section --- (Expansion Memory configured here) |
|||
|
|||
IBMOVS EQU NO ; Yes = Inter-bank Moves allowed (Z180/64180) |
|||
; No = Include Common RAM transfer buffer |
|||
|
|||
;--- Character Device Section --- |
|||
|
|||
MORDEV EQU NO ; YES = Include any extra Char Device Drivers |
|||
; NO = Only use the 4 defined Char Devices |
|||
|
|||
QSIZE EQU 32 ; size of interrupt typeahead buffers (if used) |
|||
; ..must be 2^n with n<8 |
|||
RTSCTS EQU no ; Include RTS/CTS code on Serial Outputs? |
|||
XONOFF EQU no ; Include Xon/Xoff handshaking in Serial lines? |
|||
|
|||
;--- Clock and Time Section --- |
|||
|
|||
CLOCK EQU YES ; Include ZSDOS Clock Driver Code? |
|||
CLKSET EQU YES ; Allow Clock Sets? (Error if No) |
|||
|
|||
;--- Floppy Diskette Section --- |
|||
|
|||
FLPYDSK EQU NO ; YES = Make Floppy-Disk Code, NO = No code made |
|||
BIOERM EQU yes ; Print BIOS error messages? |
|||
CALCSK EQU YES ; Calculate skew table? |
|||
AUTOSL EQU YES ; Auto select floppy formats? |
|||
; If AUTOSL=True, the next two are active... |
|||
FDDMA EQU no ; Use DMA Control for Floppy Drive Transfers? |
|||
FLOPYH EQU no ; Include "Hi-Density" Floppy Formats? |
|||
FLOPY8 EQU no ; Include 8" Floppy Formats? |
|||
MORDPB EQU NO ; Include additional Floppy DPB Formats? |
|||
|
|||
;;--- RAM Disk Section --- |
|||
; |
|||
;RAMDSK EQU YES ; YES = Make RAM-Disk Code, NO = No code made |
|||
|
|||
;--- Hard Disk Section --- |
|||
|
|||
HARDDSK EQU YES ; YES = Add Hard-disk Code, NO = Floppy Only |
|||
; (Pick 1 of 3 options below) |
|||
HBDSK EQU YES ; YES = Use HBIOS Disk Driver |
|||
HDDMA EQU NO ; Use DMA-Controlled Hard Disk Data Transfers? |
|||
; (DMA not implemented for GIDE) |
|||
UNIT_0 EQU YES ; Hard Disk Physical Unit 1 |
|||
UNIT_1 EQU YES ; Hard Disk Physical Unit 2 |
|||
UNIT_2 EQU YES ; Hard Disk Physical Unit 3 |
|||
|
|||
;--- Logical Drive Section --- |
|||
; |
|||
; Set each of these equates for the drive and partition complement of |
|||
; your system. Set equates to no if drive exists or is wanted. |
|||
|
|||
DRV_A EQU yes ; A is always RAMDSK on HBIOS Device 0. |
|||
DRV_B EQU yes ; B is always ROMDSK on HBIOS Device 1. |
|||
DRV_C EQU yes |
|||
DRV_D EQU yes |
|||
DRV_E EQU yes ; Default is C-J are Hard Disk Slices |
|||
DRV_F EQU yes ; on the first hard drive (room for |
|||
DRV_G EQU yes ; up to 8 Slices provided) e.g. CF card. |
|||
DRV_H EQU yes |
|||
DRV_I EQU yes |
|||
DRV_J EQU yes |
|||
DRV_K EQU yes ; Default is K-N are Hard Disk Slices |
|||
DRV_L EQU yes ; on a second hard drive (room for up to |
|||
DRV_M EQU yes ; 4 Slices provided) e.g. SD card |
|||
DRV_N EQU yes |
|||
if FLPYDSK |
|||
DRV_O EQU yes ; O & P are floppies |
|||
DRV_P EQU yes |
|||
else |
|||
DRV_O EQU no ; O & P are floppies |
|||
DRV_P EQU no |
|||
endif |
|||
|
|||
;========== Configuration Unique Equates =========== |
|||
;>>>>>>>>>>>>>>>>>>>>>>>>>>> W A R N I N G <<<<<<<<<<<<<<<<<<<<<<<<<<<<< |
|||
;>>> Do NOT Alter these unless you KNOW what you're doing <<< |
|||
;>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>><<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< |
|||
|
|||
REFRSH EQU NO ; Set to NO for only Static RAM, needed for |
|||
; systems with dynamic RAMs. |
|||
NOWAIT EQU NO ; Set to NO to use configured Wait States in |
|||
; Hard Disk Driver. Yes to eliminate Waits. |
|||
|
|||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
|||
; For Z-180/HD64180 systems, The Bank numbers should reflect Physical |
|||
; memory in 32k increments. In SBC V1&2, Zeta and Simh, RAM occupies the |
|||
; first 512k (16 32k banks). The upper 32k bank is fixed as the last 32k |
|||
; of 512k. HBIOS occupies bank 1. The upper |
|||
; memory bounds (BNKU, BNK3 and BNKM) should be set for your configuration. |
|||
|
|||
BNK0 EQU BID_USR ; First TPA Bank (switched in/out) 40000H |
|||
BNK1 EQU BID_HB ; Second TPA Bank (Common Bank) 48000H |
|||
BNK2 EQU BID_SYS ; System Bank (BIOS, DOS, CPR) 50000H |
|||
BNKU EQU 00H ; User Area Bank 58000H |
|||
; (set to 0 to disable) |
|||
BNK3 EQU BID_RAMD ; First Bank for RAM disk 60000H |
|||
BNKM EQU BID_RAMM ; Maximum Bank # F8000H |
|||
; With both on-board RAMs only (MEM1 or MEM2), |
|||
; the maximum Bank number is 11 (0BH). |
|||
|
|||
IF NO ; REMOVE CODE - NOT NEEDED WITH HBIOS makes a |
|||
; nice resource for Z180 programing in general |
|||
;=========== CPU-dependent Equates, Zilog Z-180/Hitachi HD64180 ========== |
|||
|
|||
CNTLA0 EQU 00H ; Control Port ASCI 0 |
|||
CNTLA1 EQU 01H ; Control Port ASCI 1 |
|||
STAT0 EQU 04H ; Serial port 0 Status |
|||
STAT1 EQU 05H ; Serial port 1 Status |
|||
TDR0 EQU 06H ; Serial port 0 Output Data |
|||
TDR1 EQU 07H ; Serial port 1 Output Data |
|||
RDR0 EQU 08H ; Serial port 0 Input Data |
|||
RDR1 EQU 09H ; Serial Port 1 Input Data |
|||
CNTR EQU 0AH ; HD64180 Counter port |
|||
TMDR0L EQU 0CH ; HD64180 DMA channel reg (low) |
|||
TMDR0H EQU 0DH ; HD64180 DMA channel reg (hi) |
|||
RLDR0L EQU 0EH ; CTC0 Reload Count, Low |
|||
RLDR0H EQU 0FH ; CTC0 Reload Count, High |
|||
TCR EQU 10H ; Interrupt Control Register |
|||
TMDR1L EQU 14H ; Timer Data Reg Ch1 (Low) |
|||
TMDR1H EQU 15H ; Timer Data Reg Ch1 (High) |
|||
RLDR1L EQU 16H ; Timer Reload Reg Ch1 (Low) |
|||
RLDR1H EQU 17H ; Timer Reload Reg Ch1 (High) |
|||
FRC EQU 18H ; Free-Running Counter |
|||
CCR EQU 1FH ; CPU Control Register (ZS8180/Z80182) |
|||
SAR0L EQU 20H ; DMA Channel 0 Register start (8 ports) |
|||
MAR1L EQU 28H ; DMA Channel 1 Register start (8 ports) |
|||
DSTAT EQU 30H ; DMA Status/Control port |
|||
DMODE EQU 31H ; DMA Mode Control port |
|||
DCNTL EQU 32H ; DMA/WAIT Control Register |
|||
IL EQU 33H ; Interrupt Segment Register |
|||
ITC EQU 34H ; Interrupt/Trap Control Register |
|||
RCR EQU 36H ; HD64180 Refresh Control register |
|||
CBR EQU 38H ; MMU Common Base Register |
|||
BBR EQU 39H ; MMU Bank Base Register |
|||
CBAR EQU 3AH ; MMU Common/Bank Area Register |
|||
OMCR EQU 3EH ; Operation Mode Control Reg |
|||
ICR EQU 3FH ; I/O Control Register |
|||
|
|||
; Some bit definitions used with the Z-180 on-chip peripherals: |
|||
|
|||
TDRE EQU 02H ; ACSI Transmitter Buffer Empty |
|||
RDRF EQU 80H ; ACSI Received Character available |
|||
|
|||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
|||
; Extended Features of Z80182 for P112 |
|||
|
|||
WSGCS EQU 0D8H ; Wait-State Generator CS |
|||
ENH182 EQU 0D9H ; Z80182 Enhancements Register |
|||
PINMUX EQU 0DFH ; Interrupt Edge/Pin Mux Register |
|||
RAMUBR EQU 0E6H ; RAM End Boundary |
|||
RAMLBR EQU 0E7H ; RAM Start Boundary |
|||
ROMBR EQU 0E8H ; ROM Boundary |
|||
FIFOCTL EQU 0E9H ; FIFO Control Register |
|||
RTOTC EQU 0EAH ; RX Time-Out Time Constant |
|||
TTOTC EQU 0EBH ; TX Time-Out Time Constant |
|||
FCR EQU 0ECH ; FIFO Register |
|||
SCR EQU 0EFH ; System Pin Control |
|||
RBR EQU 0F0H ; MIMIC RX Buffer Register (R) |
|||
THR EQU 0F0H ; MIMIN TX Holding Register (W) |
|||
IER EQU 0F1H ; Interrupt Enable Register |
|||
LCR EQU 0F3H ; Line Control Register |
|||
MCR EQU 0F4H ; Modem Control Register |
|||
LSR EQU 0F5H ; Line Status Register |
|||
MDMSR EQU 0F6H ; Modem Status Register |
|||
MSCR EQU 0F7H ; MIMIC Scratch Register |
|||
DLATL EQU 0F8H ; Divisor Latch (Low) |
|||
DLATM EQU 0F9H ; Divisor Latch (High) |
|||
TTCR EQU 0FAH ; TX Time Constant |
|||
RTCR EQU 0FBH ; RX Time Constant |
|||
IVEC EQU 0FCH ; MIMIC Interrupt Vector |
|||
MIMIE EQU 0FDH ; MIMIC Interrupt Enable Register |
|||
IUSIP EQU 0FEH ; MIMIC Interrupt Under-Service Register |
|||
MMCR EQU 0FFH ; MIMIC Master Control Register |
|||
|
|||
; Z80182 PIO Registers |
|||
|
|||
DDRA EQU 0EDH ; Data Direction Register A |
|||
DRA EQU 0EEH ; Port A Data |
|||
DDRB EQU 0E4H ; Data Direction Register B |
|||
DRB EQU 0E5H ; Data B Data |
|||
DDRC EQU 0DDH ; Data Direction Register C |
|||
DRC EQU 0DEH ; Data C Data |
|||
|
|||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
|||
; ESCC Registers on Z80182 |
|||
|
|||
SCCACNT EQU 0E0H ; ESCC Control Channel A |
|||
SCCAD EQU 0E1H ; ESCC Data Channel A |
|||
SCCBCNT EQU 0E2H ; ESCC Control Channel B |
|||
SCCBD EQU 0E3H ; ESCC Data Channel B |
|||
|
|||
; [E]SCC Internal Register Definitions |
|||
|
|||
RR0 EQU 00H |
|||
RR1 EQU 01H |
|||
RR2 EQU 02H |
|||
RR3 EQU 03H |
|||
RR6 EQU 06H |
|||
RR7 EQU 07H |
|||
RR10 EQU 0AH |
|||
RR12 EQU 0CH |
|||
RR13 EQU 0DH |
|||
RR15 EQU 0FH |
|||
|
|||
WR0 EQU 00H |
|||
WR1 EQU 01H |
|||
WR2 EQU 02H |
|||
WR3 EQU 03H |
|||
WR4 EQU 04H |
|||
WR5 EQU 05H |
|||
WR6 EQU 06H |
|||
WR7 EQU 07H |
|||
WR9 EQU 09H |
|||
WR10 EQU 0AH |
|||
WR11 EQU 0BH |
|||
WR12 EQU 0CH |
|||
WR13 EQU 0DH |
|||
WR14 EQU 0EH |
|||
WR15 EQU 0FH |
|||
|
|||
; FDC37C665/6 Parallel Port in Standard AT Mode |
|||
|
|||
DPORT EQU 8CH ; Data Port |
|||
SPORT EQU 8DH ; Status Port |
|||
CPORT EQU 8EH ; Control Port |
|||
|
|||
; FDC37C665/6 Configuration Control (access internal registers) |
|||
|
|||
CFCNTL EQU 90H ; Configuration control port |
|||
CFDATA EQU 91H ; Configuration data port |
|||
|
|||
; FDC37C665/6 Floppy Controller on P112 (Intel 80277 compatible) |
|||
|
|||
DCR EQU 92H ; Drive Control Register (Digital Output) |
|||
MSR EQU 94H ; Main Status Register |
|||
DR EQU 95H ; Data/Command Register |
|||
DRR EQU 97H ; Data Rate Register/Disk Changed Bit in B7 |
|||
|
|||
_DMA EQU 0A0H ; Diskette DMA Address |
|||
|
|||
; FDC37C665/6 Serial Port (National 16550 compatible) |
|||
|
|||
_RBR EQU 68H ;R Receiver Buffer |
|||
_THR EQU 68H ;W Transmit Holding Reg |
|||
_IER EQU 69H ;RW Interrupt-Enable Reg |
|||
_IIR EQU 6AH ;R Interrupt Ident. Reg |
|||
_FCR EQU 6AH ;W FIFO Control Reg |
|||
_LCR EQU 6BH ;RW Line Control Reg |
|||
_MCR EQU 6CH ;RW Modem Control Reg |
|||
_LSR EQU 6DH ;RW Line Status Reg |
|||
_MMSR EQU 6EH ;RW Modem Status Reg |
|||
_SCR EQU 6FH ;N/A Scratch Reg. (not avail in XT) |
|||
_DDL EQU 68H ;RW Divisor LSB | wih DLAB |
|||
_DLM EQU 69H ;RW Divisor MSB | set High |
|||
|
|||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
|||
; Equates for the National DP8490/NCR 5380 Prototype SCSI controller |
|||
|
|||
IF HARDDSK |
|||
NCR EQU 40H ; Base of NCR 5380 |
|||
|
|||
; 5380 Chip Registers |
|||
|
|||
NCRDAT EQU NCR ; Current SCSI Data (Read) |
|||
; Output Data Register (Write) |
|||
NCRCMD EQU NCR+1 ; Initiator Command Register (Read/Write) |
|||
NCRMOD EQU NCR+2 ; Mode Register (Read/Write) |
|||
NCRTGT EQU NCR+3 ; Target Command Register (Read/Write) |
|||
NCRBUS EQU NCR+4 ; Current SCSI Bus Status (Read) |
|||
NCRST EQU NCR+5 ; Bus & Status Register (Read) |
|||
; Start DMA Send (Write) |
|||
NCRINT EQU NCR+7 ; Reset Parity/Interrupt (Read) |
|||
; Start DMA Initiator Receive (Write) |
|||
DMAACK EQU NCR+8 ; SCSI Dack IO Port (Read/Write) |
|||
|
|||
; Bit Assignments for NCR 5380 Ports as indicated |
|||
|
|||
B_ARST EQU 10000000B ; Assert *RST (NCRCMD) |
|||
B_AACK EQU 00010000B ; Assert *ACK (NCRCMD) |
|||
B_ASEL EQU 00000100B ; Assert *SEL (NCRCMD) |
|||
B_ABUS EQU 00000001B ; Assert *Data Bus (NCRCMD) |
|||
|
|||
B_BSY EQU 01000000B ; *Busy (NCRBUS) |
|||
B_REQ EQU 00100000B ; *Request (NCRBUS) |
|||
B_MSG EQU 00010000B ; *Message (NCRBUS) |
|||
B_CD EQU 00001000B ; *Command/Data (NCRBUS) |
|||
B_IO EQU 00000100B ; *I/O (NCRBUS) |
|||
B_SEL EQU 00000010B ; *Select (NCRBUS) |
|||
|
|||
B_PHAS EQU 00001000B ; Phase Match (NCRST) |
|||
B_BBSY EQU 00000100B ; Bus Busy (NCRST) |
|||
|
|||
B_MBSY EQU 00000100B ; Monitor Busy Flag (NCRMOD) |
|||
B_DMA EQU 00000010B ; DMA Mode of transfer (NCRMOD) |
|||
ENDIF ;harddsk |
|||
|
|||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
|||
; Equates reflecting GIDE Base address from Address Jumpers (if GIDE added) |
|||
; Set the base GIDE equate to the jumper setting on the GIDE board. |
|||
|
|||
IF IDE |
|||
GIDE EQU 50H ; Set base of 16 byte address range |
|||
|
|||
IDEDOR EQU GIDE+6 ; Digital Output Register |
|||
IDEDat EQU GIDE+8 ; IDE Data Register (16-bit wide) |
|||
IDEErr EQU GIDE+9 ; IDE Error Register |
|||
IDESCnt EQU GIDE+0AH ; IDE Sector Count Register |
|||
IDESNum EQU GIDE+0BH ; IDE Sector Number Register |
|||
IDECLo EQU GIDE+0CH ; IDE Cylinder Number (Low) |
|||
IDECHi EQU GIDE+0DH ; IDE Cylinter Number (High) |
|||
IDESDH EQU GIDE+0EH ; IDE S-Drive-Head Register |
|||
IDECmd EQU GIDE+0FH ; IDE Command/Status Register |
|||
|
|||
CMDHOM EQU 10H ; Home Drive Heads |
|||
CMDRD EQU 20H ; Read Sector Command (w/retry) |
|||
CMDWR EQU 30H ; Write Sector Command (w/retry) |
|||
CMDVER EQU 40H ; Verify Sector(s) Command (w/retry) |
|||
CMDFMT EQU 50H ; Format Track Command |
|||
CMDDIAG EQU 90H ; Execute Diagnostics Command |
|||
CMDINIT EQU 91H ; Initialize Drive Params Command |
|||
CMDPW0 EQU 0E0H ; Low Range of Power Control Commands |
|||
CMDPW3 EQU 0E3H ; High Range of Power Control Commands |
|||
CMDPWQ EQU 0E5H ; Power Status Query Command |
|||
CMDID EQU 0ECH ; Read Drive Ident Data Command |
|||
ENDIF ;ide |
|||
;=================== End Unique Equates ======================= |
|||
ENDIF ; REMOVE CODE |
|||
@ -1,385 +0,0 @@ |
|||
;:::::::::::::::::::::::::::::::::::::::::::::::********************** |
|||
; B/P BIOS Configuration and Equate File. ** System Dependant ** |
|||
; - Retro-Brew boards /w RomWBW HBIOS - ********************** |
|||
; Tailored for a Fully-banked, internal HBIOS proxy System |
|||
; Custom tailor your system here. |
|||
; |
|||
; 02 May 18 - changes made to conform with HBIOS v 2.9.1p2 WW+LN |
|||
; 04 Sep 16 - Mods for RomWBW V 2.8 WW+LN |
|||
; 30 Apr 15 - changes made to conform with v 2.7.2 of RomWBW WW+LN |
|||
; 17 Jan 14 - Initial N8VEM release WW+LN |
|||
; 30 Aug 01 - Cleaned up for GPL release. HFB |
|||
; 11 May 97 - Added GIDE and adjusted HD equates. HFB |
|||
; 5 Jan 97 - Reformatted to Standard. HFB |
|||
; 10 Jun 96 - Initial Test Release. HFB |
|||
;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::: |
|||
; BIOS Configuration Equates and Macros |
|||
|
|||
DATE MACRO |
|||
DEFB '02 Aug 21' ; Date of this version |
|||
ENDM |
|||
AUTOCL MACRO |
|||
DEFB 8,'ZEX ZSTF',0 ; Autostart command line |
|||
ENDM |
|||
|
|||
;--- Basic System and Z-System Section --- |
|||
|
|||
MOVCPM EQU no ; Integrate into MOVCPM "type" loader? |
|||
IF MOVCPM |
|||
VERS EQU 13H ; Version number in BCD (Hex) (Major/Minor) |
|||
ELSE |
|||
VERS EQU 21H ; Version number w/Device Swapping permitted |
|||
ENDIF |
|||
BANKED EQU YES ; Is this a banked BIOS? |
|||
ZSDOS2 EQU YES ; Yes = Banked Dos, No = CP/M 2.2 Compatible |
|||
INROM EQU NO ; Alternate bank in ROM? |
|||
MHZ EQU 18 ; Set to Speed in MHZ (6/9/12/16/18/24) |
|||
FASTWB EQU YES ; Yes if restoring CPR from banked RAM |
|||
; ..No if restoring from Drive A |
|||
Z3 EQU YES ; Include ZCPR init code? |
|||
HAVIOP EQU NO ; Include IOP code into Jump table? |
|||
INTPXY EQU YES ; YES to use internal HBIOS proxy |
|||
; and load Proxy as part of BPBIOS. |
|||
; NO to use HBIOS Proxy in high RAM |
|||
; (already loaded) |
|||
IF INTPXY |
|||
; YES load Proxy as part of BPBIOS. |
|||
MEMTOP EQU 0FFE0H - 1 ; Reserve memory above this for HBIOS |
|||
; interface (32 bytes) |
|||
ELSE |
|||
; NO use HBIOS Proxy in high RAM |
|||
; (already loaded) |
|||
HBLOC EQU 0FE00H ; Location of HBIOS proxy (if used) |
|||
MEMTOP EQU HBLOC - 1 ; Reserve memory above this for HBIOS |
|||
ENDIF |
|||
|
|||
;--- Memory configuration Section --- (Expansion Memory configured here) |
|||
|
|||
IBMOVS EQU NO ; Yes = Inter-bank Moves allowed (Z180/64180) |
|||
; No = Include Common RAM transfer buffer |
|||
|
|||
;--- Character Device Section --- |
|||
|
|||
MORDEV EQU NO ; YES = Include any extra Char Device Drivers |
|||
; NO = Only use the 4 defined Char Devices |
|||
|
|||
QSIZE EQU 32 ; size of interrupt typeahead buffers (if used) |
|||
; ..must be 2^n with n<8 |
|||
RTSCTS EQU no ; Include RTS/CTS code on Serial Outputs? |
|||
XONOFF EQU no ; Include Xon/Xoff handshaking in Serial lines? |
|||
|
|||
;--- Clock and Time Section --- |
|||
|
|||
CLOCK EQU YES ; Include ZSDOS Clock Driver Code? |
|||
CLKSET EQU YES ; Allow Clock Sets? (Error if No) |
|||
|
|||
;--- Floppy Diskette Section --- |
|||
|
|||
FLPYDSK EQU NO ; YES = Make Floppy-Disk Code, NO = No code made |
|||
|
|||
BIOERM EQU yes ; Print BIOS error messages? |
|||
CALCSK EQU YES ; Calculate skew table? |
|||
AUTOSL EQU YES ; Auto select floppy formats? |
|||
; If AUTOSL=True, the next two are active... |
|||
FDDMA EQU no ; Use DMA Control for Floppy Drive Transfers? |
|||
FLOPYH EQU no ; Include "Hi-Density" Floppy Formats? |
|||
FLOPY8 EQU no ; Include 8" Floppy Formats? |
|||
MORDPB EQU NO ; Include additional Floppy DPB Formats? |
|||
|
|||
;;--- RAM Disk Section --- |
|||
; |
|||
;RAMDSK EQU YES ; YES = Make RAM-Disk Code, NO = No code made |
|||
; |
|||
|
|||
;--- Hard Disk Section --- |
|||
|
|||
HARDDSK EQU YES ; YES = Add Hard-disk Code, NO = Floppy Only |
|||
; (Pick 1 of 3 options below) |
|||
HBDSK EQU YES ; YES = Use HBIOS Disk Driver |
|||
HDDMA EQU NO ; Use DMA-Controlled Hard Disk Data Transfers? |
|||
; (DMA not implemented for GIDE) |
|||
UNIT_0 EQU YES ; Hard Disk Physical Unit 1 |
|||
UNIT_1 EQU YES ; Hard Disk Physical Unit 2 |
|||
UNIT_2 EQU YES ; Hard Disk Physical Unit 3 |
|||
|
|||
;--- Logical Drive Section --- |
|||
; |
|||
; Set each of these equates for the drive and partition complement of |
|||
; your system. Set equates to no if drive exists or is wanted. |
|||
|
|||
DRV_A EQU yes ; A is always RAMDSK on HBIOS Device 0. |
|||
DRV_B EQU yes ; B is always ROMDSK on HBIOS Device 1. |
|||
DRV_C EQU yes |
|||
DRV_D EQU yes |
|||
DRV_E EQU yes ; Default is C-J are Hard Disk Slices |
|||
DRV_F EQU yes ; on the first hard drive (room for |
|||
DRV_G EQU yes ; up to 8 Slices provided) e.g. CF card. |
|||
DRV_H EQU yes |
|||
DRV_I EQU yes |
|||
DRV_J EQU yes |
|||
DRV_K EQU yes ; Default is K-N are Hard Disk Slices |
|||
DRV_L EQU yes ; on a second hard drive (room for up to |
|||
DRV_M EQU yes ; 4 Slices provided) e.g. SD card |
|||
DRV_N EQU yes |
|||
if FLPYDSK |
|||
DRV_O EQU yes ; O & P are floppies |
|||
DRV_P EQU yes |
|||
else |
|||
DRV_O EQU no ; O & P are floppies |
|||
DRV_P EQU no |
|||
endif |
|||
|
|||
;========== Configuration Unique Equates =========== |
|||
;>>>>>>>>>>>>>>>>>>>>>>>>>>> W A R N I N G <<<<<<<<<<<<<<<<<<<<<<<<<<<<< |
|||
;>>> Do NOT Alter these unless you KNOW what you're doing <<< |
|||
;>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>><<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< |
|||
|
|||
REFRSH EQU NO ; Set to NO for only Static RAM, needed for |
|||
; systems with dynamic RAMs. |
|||
NOWAIT EQU NO ; Set to NO to use configured Wait States in |
|||
; Hard Disk Driver. Yes to eliminate Waits. |
|||
|
|||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
|||
; For Z-180/HD64180 systems, The Bank numbers should reflect Physical |
|||
; memory in 32k increments. In SBC V1&2, Zeta and Simh, RAM occupies the |
|||
; first 512k (16 32k banks). The upper 32k bank is fixed as the last 32k |
|||
; of 512k. HBIOS occupies bank 1. The upper |
|||
; memory bounds (BNKU, BNK3 and BNKM) should be set for your configuration. |
|||
|
|||
BNK0 EQU BID_USR ; First TPA Bank (switched in/out) 40000H |
|||
BNK1 EQU BID_HB ; Second TPA Bank (Common Bank) 48000H |
|||
BNK2 EQU BID_SYS ; System Bank (BIOS, DOS, CPR) 50000H |
|||
BNKU EQU 00H ; User Area Bank 58000H |
|||
; (set to 0 to disable) |
|||
BNK3 EQU BID_RAMD ; First Bank for RAM disk 60000H |
|||
BNKM EQU BID_RAMM ; Maximum Bank # F8000H |
|||
; With both on-board RAMs only (MEM1 or MEM2), |
|||
; the maximum Bank number is 11 (0BH). |
|||
|
|||
IF NO ; REMOVE CODE - NOT NEEDED WITH HBIOS makes a |
|||
; nice resource for Z180 programing in general |
|||
;=========== CPU-dependent Equates, Zilog Z-180/Hitachi HD64180 ========== |
|||
|
|||
CNTLA0 EQU 00H ; Control Port ASCI 0 |
|||
CNTLA1 EQU 01H ; Control Port ASCI 1 |
|||
STAT0 EQU 04H ; Serial port 0 Status |
|||
STAT1 EQU 05H ; Serial port 1 Status |
|||
TDR0 EQU 06H ; Serial port 0 Output Data |
|||
TDR1 EQU 07H ; Serial port 1 Output Data |
|||
RDR0 EQU 08H ; Serial port 0 Input Data |
|||
RDR1 EQU 09H ; Serial Port 1 Input Data |
|||
CNTR EQU 0AH ; HD64180 Counter port |
|||
TMDR0L EQU 0CH ; HD64180 DMA channel reg (low) |
|||
TMDR0H EQU 0DH ; HD64180 DMA channel reg (hi) |
|||
RLDR0L EQU 0EH ; CTC0 Reload Count, Low |
|||
RLDR0H EQU 0FH ; CTC0 Reload Count, High |
|||
TCR EQU 10H ; Interrupt Control Register |
|||
TMDR1L EQU 14H ; Timer Data Reg Ch1 (Low) |
|||
TMDR1H EQU 15H ; Timer Data Reg Ch1 (High) |
|||
RLDR1L EQU 16H ; Timer Reload Reg Ch1 (Low) |
|||
RLDR1H EQU 17H ; Timer Reload Reg Ch1 (High) |
|||
FRC EQU 18H ; Free-Running Counter |
|||
CCR EQU 1FH ; CPU Control Register (ZS8180/Z80182) |
|||
SAR0L EQU 20H ; DMA Channel 0 Register start (8 ports) |
|||
MAR1L EQU 28H ; DMA Channel 1 Register start (8 ports) |
|||
DSTAT EQU 30H ; DMA Status/Control port |
|||
DMODE EQU 31H ; DMA Mode Control port |
|||
DCNTL EQU 32H ; DMA/WAIT Control Register |
|||
IL EQU 33H ; Interrupt Segment Register |
|||
ITC EQU 34H ; Interrupt/Trap Control Register |
|||
RCR EQU 36H ; HD64180 Refresh Control register |
|||
CBR EQU 38H ; MMU Common Base Register |
|||
BBR EQU 39H ; MMU Bank Base Register |
|||
CBAR EQU 3AH ; MMU Common/Bank Area Register |
|||
OMCR EQU 3EH ; Operation Mode Control Reg |
|||
ICR EQU 3FH ; I/O Control Register |
|||
|
|||
; Some bit definitions used with the Z-180 on-chip peripherals: |
|||
|
|||
TDRE EQU 02H ; ACSI Transmitter Buffer Empty |
|||
RDRF EQU 80H ; ACSI Received Character available |
|||
|
|||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
|||
; Extended Features of Z80182 for P112 |
|||
|
|||
WSGCS EQU 0D8H ; Wait-State Generator CS |
|||
ENH182 EQU 0D9H ; Z80182 Enhancements Register |
|||
PINMUX EQU 0DFH ; Interrupt Edge/Pin Mux Register |
|||
RAMUBR EQU 0E6H ; RAM End Boundary |
|||
RAMLBR EQU 0E7H ; RAM Start Boundary |
|||
ROMBR EQU 0E8H ; ROM Boundary |
|||
FIFOCTL EQU 0E9H ; FIFO Control Register |
|||
RTOTC EQU 0EAH ; RX Time-Out Time Constant |
|||
TTOTC EQU 0EBH ; TX Time-Out Time Constant |
|||
FCR EQU 0ECH ; FIFO Register |
|||
SCR EQU 0EFH ; System Pin Control |
|||
RBR EQU 0F0H ; MIMIC RX Buffer Register (R) |
|||
THR EQU 0F0H ; MIMIN TX Holding Register (W) |
|||
IER EQU 0F1H ; Interrupt Enable Register |
|||
LCR EQU 0F3H ; Line Control Register |
|||
MCR EQU 0F4H ; Modem Control Register |
|||
LSR EQU 0F5H ; Line Status Register |
|||
MDMSR EQU 0F6H ; Modem Status Register |
|||
MSCR EQU 0F7H ; MIMIC Scratch Register |
|||
DLATL EQU 0F8H ; Divisor Latch (Low) |
|||
DLATM EQU 0F9H ; Divisor Latch (High) |
|||
TTCR EQU 0FAH ; TX Time Constant |
|||
RTCR EQU 0FBH ; RX Time Constant |
|||
IVEC EQU 0FCH ; MIMIC Interrupt Vector |
|||
MIMIE EQU 0FDH ; MIMIC Interrupt Enable Register |
|||
IUSIP EQU 0FEH ; MIMIC Interrupt Under-Service Register |
|||
MMCR EQU 0FFH ; MIMIC Master Control Register |
|||
|
|||
; Z80182 PIO Registers |
|||
|
|||
DDRA EQU 0EDH ; Data Direction Register A |
|||
DRA EQU 0EEH ; Port A Data |
|||
DDRB EQU 0E4H ; Data Direction Register B |
|||
DRB EQU 0E5H ; Data B Data |
|||
DDRC EQU 0DDH ; Data Direction Register C |
|||
DRC EQU 0DEH ; Data C Data |
|||
|
|||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
|||
; ESCC Registers on Z80182 |
|||
|
|||
SCCACNT EQU 0E0H ; ESCC Control Channel A |
|||
SCCAD EQU 0E1H ; ESCC Data Channel A |
|||
SCCBCNT EQU 0E2H ; ESCC Control Channel B |
|||
SCCBD EQU 0E3H ; ESCC Data Channel B |
|||
|
|||
; [E]SCC Internal Register Definitions |
|||
|
|||
RR0 EQU 00H |
|||
RR1 EQU 01H |
|||
RR2 EQU 02H |
|||
RR3 EQU 03H |
|||
RR6 EQU 06H |
|||
RR7 EQU 07H |
|||
RR10 EQU 0AH |
|||
RR12 EQU 0CH |
|||
RR13 EQU 0DH |
|||
RR15 EQU 0FH |
|||
|
|||
WR0 EQU 00H |
|||
WR1 EQU 01H |
|||
WR2 EQU 02H |
|||
WR3 EQU 03H |
|||
WR4 EQU 04H |
|||
WR5 EQU 05H |
|||
WR6 EQU 06H |
|||
WR7 EQU 07H |
|||
WR9 EQU 09H |
|||
WR10 EQU 0AH |
|||
WR11 EQU 0BH |
|||
WR12 EQU 0CH |
|||
WR13 EQU 0DH |
|||
WR14 EQU 0EH |
|||
WR15 EQU 0FH |
|||
|
|||
; FDC37C665/6 Parallel Port in Standard AT Mode |
|||
|
|||
DPORT EQU 8CH ; Data Port |
|||
SPORT EQU 8DH ; Status Port |
|||
CPORT EQU 8EH ; Control Port |
|||
|
|||
; FDC37C665/6 Configuration Control (access internal registers) |
|||
|
|||
CFCNTL EQU 90H ; Configuration control port |
|||
CFDATA EQU 91H ; Configuration data port |
|||
|
|||
; FDC37C665/6 Floppy Controller on P112 (Intel 80277 compatible) |
|||
|
|||
DCR EQU 92H ; Drive Control Register (Digital Output) |
|||
MSR EQU 94H ; Main Status Register |
|||
DR EQU 95H ; Data/Command Register |
|||
DRR EQU 97H ; Data Rate Register/Disk Changed Bit in B7 |
|||
|
|||
_DMA EQU 0A0H ; Diskette DMA Address |
|||
|
|||
; FDC37C665/6 Serial Port (National 16550 compatible) |
|||
|
|||
_RBR EQU 68H ;R Receiver Buffer |
|||
_THR EQU 68H ;W Transmit Holding Reg |
|||
_IER EQU 69H ;RW Interrupt-Enable Reg |
|||
_IIR EQU 6AH ;R Interrupt Ident. Reg |
|||
_FCR EQU 6AH ;W FIFO Control Reg |
|||
_LCR EQU 6BH ;RW Line Control Reg |
|||
_MCR EQU 6CH ;RW Modem Control Reg |
|||
_LSR EQU 6DH ;RW Line Status Reg |
|||
_MMSR EQU 6EH ;RW Modem Status Reg |
|||
_SCR EQU 6FH ;N/A Scratch Reg. (not avail in XT) |
|||
_DDL EQU 68H ;RW Divisor LSB | wih DLAB |
|||
_DLM EQU 69H ;RW Divisor MSB | set High |
|||
|
|||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
|||
; Equates for the National DP8490/NCR 5380 Prototype SCSI controller |
|||
|
|||
IF HARDDSK |
|||
NCR EQU 40H ; Base of NCR 5380 |
|||
|
|||
; 5380 Chip Registers |
|||
|
|||
NCRDAT EQU NCR ; Current SCSI Data (Read) |
|||
; Output Data Register (Write) |
|||
NCRCMD EQU NCR+1 ; Initiator Command Register (Read/Write) |
|||
NCRMOD EQU NCR+2 ; Mode Register (Read/Write) |
|||
NCRTGT EQU NCR+3 ; Target Command Register (Read/Write) |
|||
NCRBUS EQU NCR+4 ; Current SCSI Bus Status (Read) |
|||
NCRST EQU NCR+5 ; Bus & Status Register (Read) |
|||
; Start DMA Send (Write) |
|||
NCRINT EQU NCR+7 ; Reset Parity/Interrupt (Read) |
|||
; Start DMA Initiator Receive (Write) |
|||
DMAACK EQU NCR+8 ; SCSI Dack IO Port (Read/Write) |
|||
|
|||
; Bit Assignments for NCR 5380 Ports as indicated |
|||
|
|||
B_ARST EQU 10000000B ; Assert *RST (NCRCMD) |
|||
B_AACK EQU 00010000B ; Assert *ACK (NCRCMD) |
|||
B_ASEL EQU 00000100B ; Assert *SEL (NCRCMD) |
|||
B_ABUS EQU 00000001B ; Assert *Data Bus (NCRCMD) |
|||
|
|||
B_BSY EQU 01000000B ; *Busy (NCRBUS) |
|||
B_REQ EQU 00100000B ; *Request (NCRBUS) |
|||
B_MSG EQU 00010000B ; *Message (NCRBUS) |
|||
B_CD EQU 00001000B ; *Command/Data (NCRBUS) |
|||
B_IO EQU 00000100B ; *I/O (NCRBUS) |
|||
B_SEL EQU 00000010B ; *Select (NCRBUS) |
|||
|
|||
B_PHAS EQU 00001000B ; Phase Match (NCRST) |
|||
B_BBSY EQU 00000100B ; Bus Busy (NCRST) |
|||
|
|||
B_MBSY EQU 00000100B ; Monitor Busy Flag (NCRMOD) |
|||
B_DMA EQU 00000010B ; DMA Mode of transfer (NCRMOD) |
|||
ENDIF ;harddsk |
|||
|
|||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
|||
; Equates reflecting GIDE Base address from Address Jumpers (if GIDE added) |
|||
; Set the base GIDE equate to the jumper setting on the GIDE board. |
|||
|
|||
IF IDE |
|||
GIDE EQU 50H ; Set base of 16 byte address range |
|||
|
|||
IDEDOR EQU GIDE+6 ; Digital Output Register |
|||
IDEDat EQU GIDE+8 ; IDE Data Register (16-bit wide) |
|||
IDEErr EQU GIDE+9 ; IDE Error Register |
|||
IDESCnt EQU GIDE+0AH ; IDE Sector Count Register |
|||
IDESNum EQU GIDE+0BH ; IDE Sector Number Register |
|||
IDECLo EQU GIDE+0CH ; IDE Cylinder Number (Low) |
|||
IDECHi EQU GIDE+0DH ; IDE Cylinter Number (High) |
|||
IDESDH EQU GIDE+0EH ; IDE S-Drive-Head Register |
|||
IDECmd EQU GIDE+0FH ; IDE Command/Status Register |
|||
|
|||
CMDHOM EQU 10H ; Home Drive Heads |
|||
CMDRD EQU 20H ; Read Sector Command (w/retry) |
|||
CMDWR EQU 30H ; Write Sector Command (w/retry) |
|||
CMDVER EQU 40H ; Verify Sector(s) Command (w/retry) |
|||
CMDFMT EQU 50H ; Format Track Command |
|||
CMDDIAG EQU 90H ; Execute Diagnostics Command |
|||
CMDINIT EQU 91H ; Initialize Drive Params Command |
|||
CMDPW0 EQU 0E0H ; Low Range of Power Control Commands |
|||
CMDPW3 EQU 0E3H ; High Range of Power Control Commands |
|||
CMDPWQ EQU 0E5H ; Power Status Query Command |
|||
CMDID EQU 0ECH ; Read Drive Ident Data Command |
|||
ENDIF ;ide |
|||
;=================== End Unique Equates ======================= |
|||
ENDIF ; REMOVE CODE |
|||
@ -1,97 +0,0 @@ |
|||
;:::::::::::::::::::::::::::::::::::::::::::::::********************** |
|||
; B/P BIOS Configuration and Equate File. ** System Dependant ** |
|||
; - Retro-Brew Processors W/ RomWBW HBIOS - ********************** |
|||
; HBIOS specific customizations |
|||
;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::: |
|||
; BIOS Configuration Equates and Macros |
|||
; |
|||
; NOTE: Must make sure settings below match hardware and |
|||
; HBIOS configuration. |
|||
; |
|||
HBIOS EQU YES ; Use HBIOS functions |
|||
HBLOC EQU 0FE00H ; Location of HBIOS proxy (used if not INTPXY) |
|||
; |
|||
; Set exactly one of the following to YES to specify platform |
|||
; |
|||
SBC EQU NO |
|||
ZETA EQU NO |
|||
ZETA2 EQU NO |
|||
N8 EQU NO |
|||
MK4 EQU YES |
|||
; |
|||
; SIMH SUPPORT - only used with SBC |
|||
IF SBC |
|||
SIMH EQU YES ; Set yes if running on SimH |
|||
ELSE |
|||
SIMH EQU NO |
|||
ENDIF |
|||
; |
|||
; Set to YES FOR BIOS clock support else NO If no clock |
|||
; |
|||
HBCLK EQU YES ; HBIOS clock driver |
|||
; |
|||
; Set HB_IODEV to appropriate console device |
|||
; |
|||
HB_IODEV EQU 0 ; Assume we want to use first HBIOS serial device |
|||
; Change if using PROPIO etc. |
|||
; |
|||
; Set HB_HDDEV to appropriate hard disk driver |
|||
; |
|||
HB_HDDEV EQU 2 ; Assumes disk device #2 is first hard disk device |
|||
; |
|||
; Set HB_MDDEV to appropriate memory disk driver |
|||
; |
|||
HB_MDDEV EQU 0 ; Assumes disk device #0 is ROM disk device |
|||
; |
|||
; Floppy disk support |
|||
; |
|||
IF MK4 or SIMH |
|||
DRV_O SET NO ; YES if system has flopy drives |
|||
DRV_P SET NO ; YES if system has flopy drives |
|||
ENDIF ;MK4 or SIMH |
|||
; |
|||
; RAM/ROM disk sizes expressed as count of 2K blocks |
|||
; |
|||
HB_RAMBLKS EQU 192 ; 512K - 128K reserved / 2K per block |
|||
HB_ROMBLKS EQU 192 ; 512K - 128K reserved / 2K per block |
|||
;HB_ROMBLKS EQU 448 ; 1024K - 128K reserved / 2K per block |
|||
; |
|||
; Layout of RAM banks |
|||
; |
|||
IF SBC OR ZETA OR ZETA2 OR MK4 |
|||
BID_RAMD EQU 80H |
|||
BID_RAMM EQU 8BH |
|||
BID_SYS EQU 8CH |
|||
BID_HB EQU 8DH |
|||
BID_USR EQU 8EH |
|||
BID_COM EQU 8FH |
|||
ENDIF |
|||
IF N8 |
|||
BID_RAMD EQU 80H |
|||
BID_RAMM EQU 9BH |
|||
BID_SYS EQU 9CH |
|||
BID_HB EQU 9DH |
|||
BID_USR EQU 9EH |
|||
BID_COM EQU 9FH |
|||
ENDIF |
|||
; |
|||
IF INTPXY |
|||
MEMTOP EQU 0FFE0H - 1 ; Start of HBIOS 32 byte control block |
|||
ELSE |
|||
MEMTOP EQU HBLOC - 1 ; Start of HBIOS 512 byte proxy |
|||
ENDIF |
|||
|
|||
IF INTPXY |
|||
HB_EI MACRO |
|||
ENDM |
|||
HB_DI MACRO |
|||
ENDM |
|||
ELSE |
|||
HB_EI MACRO |
|||
EI |
|||
ENDM |
|||
HB_DI MACRO |
|||
DI |
|||
ENDM |
|||
ENDIF |
|||
|
|||
@ -1,82 +0,0 @@ |
|||
;:::::::::::::::::::::::::::::::::::::::::::::::********************** |
|||
; B/P BIOS Configuration and Equate File. ** System Dependant ** |
|||
; - D-X Designs Pty Ltd P112 CPU Board - ********************** |
|||
; HBIOS specific customizations |
|||
;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::: |
|||
; BIOS Configuration Equates and Macros |
|||
; |
|||
; NOTE: Must make sure settings below match hardware and |
|||
; HBIOS configuration. |
|||
; |
|||
HBIOS EQU YES ; Use HBIOS functions |
|||
HBLOC EQU 0FE00H ; Location of HBIOS proxy (used if not INTPXY) |
|||
; |
|||
; Set exactly one of the following to YES to specify platform |
|||
; |
|||
N8VEM EQU NO |
|||
ZETA EQU NO |
|||
ZETA2 EQU NO |
|||
N8 EQU NO |
|||
MK4 EQU YES |
|||
; |
|||
; Set either the following to YES (or both to NO for no clock code) |
|||
; |
|||
SIMHCLK EQU NO ; Direct SIMH clock access |
|||
HBCLK EQU YES ; HBIOS clock driver |
|||
; |
|||
; Set HB_IODEV to appropriate console device |
|||
; |
|||
HB_IODEV EQU 0 ; Assume we want to use first HBIOS serial device |
|||
; |
|||
; Set HB_HDDEV to the first (boot) hard disk device unit number |
|||
; |
|||
HB_HDDEV EQU 2 ; Assumes disk device #2 is first hard disk device |
|||
; |
|||
; Set HB_MDDEV to appropriate memory disk driver |
|||
; |
|||
HB_MDDEV EQU 0 ; Assumes disk device #0 is ROM disk device |
|||
; |
|||
; RAM/ROM disk sizes expressed as count of 2K blocks |
|||
; |
|||
HB_RAMBLKS EQU 192 ; 512K - 128K reserved / 2K per block |
|||
HB_ROMBLKS EQU 192 ; 512K - 128K reserved / 2K per block |
|||
;HB_ROMBLKS EQU 448 ; 1024K - 128K reserved / 2K per block |
|||
; |
|||
; Layout of RAM banks |
|||
; |
|||
IF N8VEM OR ZETA OR ZETA2 OR MK4 |
|||
BID_RAMD EQU 80H |
|||
BID_RAMM EQU 8BH |
|||
BID_SYS EQU 8CH |
|||
BID_HB EQU 8DH |
|||
BID_USR EQU 8EH |
|||
BID_COM EQU 8FH |
|||
ENDIF |
|||
IF N8 |
|||
BID_RAMD EQU 80H |
|||
BID_RAMM EQU 9BH |
|||
BID_SYS EQU 9CH |
|||
BID_HB EQU 9DH |
|||
BID_USR EQU 9EH |
|||
BID_COM EQU 9FH |
|||
ENDIF |
|||
; |
|||
IF INTPXY |
|||
MEMTOP EQU 0FFE0H - 1 ; Start of HBIOS 32 byte control block |
|||
ELSE |
|||
MEMTOP EQU HBLOC - 1 ; Start of HBIOS 512 byte proxy |
|||
ENDIF |
|||
|
|||
IF INTPXY |
|||
HB_EI MACRO |
|||
ENDM |
|||
HB_DI MACRO |
|||
ENDM |
|||
ELSE |
|||
HB_EI MACRO |
|||
EI |
|||
ENDM |
|||
HB_DI MACRO |
|||
DI |
|||
ENDM |
|||
ENDIF |
|||
@ -1,97 +0,0 @@ |
|||
;:::::::::::::::::::::::::::::::::::::::::::::::********************** |
|||
; B/P BIOS Configuration and Equate File. ** System Dependant ** |
|||
; - Retro-Brew Processors W/ RomWBW HBIOS - ********************** |
|||
; HBIOS specific customizations |
|||
;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::: |
|||
; BIOS Configuration Equates and Macros |
|||
; |
|||
; NOTE: Must make sure settings below match hardware and |
|||
; HBIOS configuration. |
|||
; |
|||
HBIOS EQU YES ; Use HBIOS functions |
|||
HBLOC EQU 0FE00H ; Location of HBIOS proxy (used if not INTPXY) |
|||
; |
|||
; Set exactly one of the following to YES to specify platform |
|||
; |
|||
SBC EQU YES |
|||
ZETA EQU NO |
|||
ZETA2 EQU NO |
|||
N8 EQU NO |
|||
MK4 EQU NO |
|||
; |
|||
; SIMH SUPPORT - only used with SBC |
|||
IF SBC |
|||
SIMH EQU YES ; Set yes if running on SimH |
|||
ELSE |
|||
SIMH EQU NO |
|||
ENDIF |
|||
; |
|||
; Set to YES FOR BIOS clock support else NO If no clock |
|||
; |
|||
HBCLK EQU YES ; HBIOS clock driver |
|||
; |
|||
; Set HB_IODEV to appropriate console device |
|||
; |
|||
HB_IODEV EQU 0 ; Assume we want to use first HBIOS serial device |
|||
; Change if using PROPIO etc. |
|||
; |
|||
; Set HB_HDDEV to appropriate hard disk driver |
|||
; |
|||
HB_HDDEV EQU 2 ; Assumes disk device #2 is first hard disk device |
|||
; |
|||
; Set HB_MDDEV to appropriate memory disk driver |
|||
; |
|||
HB_MDDEV EQU 0 ; Assumes disk device #0 is ROM disk device |
|||
; |
|||
; Floppy disk support |
|||
; |
|||
IF MK4 or SIMH |
|||
DRV_O SET NO ; YES if system has flopy drives |
|||
DRV_P SET NO ; YES if system has flopy drives |
|||
ENDIF ;MK4 or SIMH |
|||
; |
|||
; RAM/ROM disk sizes expressed as count of 2K blocks |
|||
; |
|||
HB_RAMBLKS EQU 192 ; 512K - 128K reserved / 2K per block |
|||
HB_ROMBLKS EQU 192 ; 512K - 128K reserved / 2K per block |
|||
;HB_ROMBLKS EQU 448 ; 1024K - 128K reserved / 2K per block |
|||
; |
|||
; Layout of RAM banks |
|||
; |
|||
IF SBC OR ZETA OR ZETA2 OR MK4 |
|||
BID_RAMD EQU 80H |
|||
BID_RAMM EQU 8BH |
|||
BID_SYS EQU 8CH |
|||
BID_HB EQU 8DH |
|||
BID_USR EQU 8EH |
|||
BID_COM EQU 8FH |
|||
ENDIF |
|||
IF N8 |
|||
BID_RAMD EQU 80H |
|||
BID_RAMM EQU 9BH |
|||
BID_SYS EQU 9CH |
|||
BID_HB EQU 9DH |
|||
BID_USR EQU 9EH |
|||
BID_COM EQU 9FH |
|||
ENDIF |
|||
; |
|||
IF INTPXY |
|||
MEMTOP EQU 0FFE0H - 1 ; Start of HBIOS 32 byte control block |
|||
ELSE |
|||
MEMTOP EQU HBLOC - 1 ; Start of HBIOS 512 byte proxy |
|||
ENDIF |
|||
|
|||
IF INTPXY |
|||
HB_EI MACRO |
|||
ENDM |
|||
HB_DI MACRO |
|||
ENDM |
|||
ELSE |
|||
HB_EI MACRO |
|||
EI |
|||
ENDM |
|||
HB_DI MACRO |
|||
DI |
|||
ENDM |
|||
ENDIF |
|||
|
|||
@ -1,82 +0,0 @@ |
|||
;:::::::::::::::::::::::::::::::::::::::::::::::********************** |
|||
; B/P BIOS Configuration and Equate File. ** System Dependant ** |
|||
; - D-X Designs Pty Ltd P112 CPU Board - ********************** |
|||
; HBIOS specific customizations |
|||
;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::: |
|||
; BIOS Configuration Equates and Macros |
|||
; |
|||
; NOTE: Must make sure settings below match hardware and |
|||
; HBIOS configuration. |
|||
; |
|||
HBIOS EQU YES ; Use HBIOS functions |
|||
HBLOC EQU 0FE00H ; Location of HBIOS proxy (used if not INTPXY) |
|||
; |
|||
; Set exactly one of the following to YES to specify platform |
|||
; |
|||
N8VEM EQU YES |
|||
ZETA EQU NO |
|||
ZETA2 EQU NO |
|||
N8 EQU NO |
|||
MK4 EQU NO |
|||
; |
|||
; Set either the following to YES (or both to NO for no clock code) |
|||
; |
|||
SIMHCLK EQU NO ; Direct SIMH clock access |
|||
HBCLK EQU YES ; HBIOS clock driver |
|||
; |
|||
; Set HB_IODEV to appropriate console device |
|||
; |
|||
HB_IODEV EQU 0 ; Assume we want to use first HBIOS serial device |
|||
; |
|||
; Set HB_HDDEV to the first (boot) hard disk device unit number |
|||
; |
|||
HB_HDDEV EQU 2 ; Assumes disk device #2 is first hard disk device |
|||
; |
|||
; Set HB_MDDEV to appropriate memory disk driver |
|||
; |
|||
HB_MDDEV EQU 0 ; Assumes disk device #0 is ROM disk device |
|||
; |
|||
; RAM/ROM disk sizes expressed as count of 2K blocks |
|||
; |
|||
HB_RAMBLKS EQU 192 ; 512K - 128K reserved / 2K per block |
|||
HB_ROMBLKS EQU 192 ; 512K - 128K reserved / 2K per block |
|||
;HB_ROMBLKS EQU 448 ; 1024K - 128K reserved / 2K per block |
|||
; |
|||
; Layout of RAM banks |
|||
; |
|||
IF N8VEM OR ZETA OR ZETA2 OR MK4 |
|||
BID_RAMD EQU 80H |
|||
BID_RAMM EQU 8BH |
|||
BID_SYS EQU 8CH |
|||
BID_HB EQU 8DH |
|||
BID_USR EQU 8EH |
|||
BID_COM EQU 8FH |
|||
ENDIF |
|||
IF N8 |
|||
BID_RAMD EQU 80H |
|||
BID_RAMM EQU 9BH |
|||
BID_SYS EQU 9CH |
|||
BID_HB EQU 9DH |
|||
BID_USR EQU 9EH |
|||
BID_COM EQU 9FH |
|||
ENDIF |
|||
; |
|||
IF INTPXY |
|||
MEMTOP EQU 0FFE0H - 1 ; Start of HBIOS 32 byte control block |
|||
ELSE |
|||
MEMTOP EQU HBLOC - 1 ; Start of HBIOS 512 byte proxy |
|||
ENDIF |
|||
|
|||
IF INTPXY |
|||
HB_EI MACRO |
|||
ENDM |
|||
HB_DI MACRO |
|||
ENDM |
|||
ELSE |
|||
HB_EI MACRO |
|||
EI |
|||
ENDM |
|||
HB_DI MACRO |
|||
DI |
|||
ENDM |
|||
ENDIF |
|||
@ -1,152 +0,0 @@ |
|||
; z3base.fp -- B/P Bios System Z3 Definition File for a fully |
|||
; banked system with 32 byte external HBIOS proxy and |
|||
; internal proxy. |
|||
|
|||
; This file is adapted from the basic Z3BASE.LIB configuration file used for |
|||
; most ZCPR33 systems. It has added the new definitions for the Resident |
|||
; User Space defined in B/P Bios descriptions. |
|||
;========================================================================= |
|||
;== NOTE: The Starting Address of the User Space marks the lower == |
|||
;== base of memory and MUST be entered. B/P Bios Utilities use == |
|||
;== this address to locate many portions of the operating system. == |
|||
;========================================================================= |
|||
; To change your systems definition, first sketch out the memory map in the |
|||
; comment table, then set the equates to reflect the memory map, doing any |
|||
; required calculations for element sizes and required spaces. As an |
|||
; alternative, just leave this file alone and configure everything with |
|||
; the utilities provided. For example reserve top 1k for HBIOS and no IOP. |
|||
|
|||
; FFE0 - FFFF 32 Bytes HBIOS RESERVED AREA (mini proxy) |
|||
; FFB0 - FFDF 48 Bytes ZCPR3 External Stack (must be 48 bytes) |
|||
; FE00 - FFAF 432 Bytes Named Directory Buffer |
|||
; FD00 - FDFF 256 Bytes Multiple Command Line Buffer |
|||
; FC00 - FCFF 256 Bytes Environment Descriptor |
|||
; Bytes 00H-7FH: Z3 Parameters |
|||
; Bytes 80H-FFH: Z3 TCAP |
|||
; FBFF 1 Byte Wheel byte |
|||
; FBF4 - FAFE 11 Bytes Path (5 elements) |
|||
; FBD0 - FAF3 36 Bytes ZCPR3 External FCB |
|||
; FB80 - FACF 80 Bytes ZCPR3 Message Buffers |
|||
; FB00 - FA7F 128 Bytes ZCPR3 Shell Stack |
|||
; F900 - FAFF 512 Bytes Flow Command Package |
|||
; F900 - F900 0 KBytes Resident Command Package |
|||
; F900 - F900 0 KBytes IO Package - no IOP |
|||
; F900 - F900 0 KBytes Resident User Space (no clk drvr needed) |
|||
|
|||
; The remainder is for the Operating System. Exact sizes vary depending |
|||
; primarily on the Number and sizes of Hard Drive Partitions, typically: |
|||
|
|||
; EF00 - F8FF 2.75 KBytes B/P BIOS (unbanked version) |
|||
; E580 - EEFF 3.375 KBytes ZSDOS 2.0 BDOS |
|||
; DD80 - E47F 2 KBytes ZCPR 4.1 Command Processor |
|||
; 0100 - C5FF ~50 KBytes Transient Program Area |
|||
; 0000 - 00FF 256 Bytes Standard CP/M Buffers |
|||
;======================================================================== |
|||
|
|||
FALSE EQU 0 |
|||
TRUE EQU NOT FALSE |
|||
|
|||
YES EQU TRUE |
|||
NO EQU FALSE |
|||
|
|||
; The External Stack is placed in the very top position in memory. It is |
|||
; mandatory for B/P Bios and ZCPR 3.3. |
|||
|
|||
; FFB0 - FFDF 48 Bytes ZCPR3 External Stack (must be 48 bytes) |
|||
;EXTSTK EQU 0FBD0H ; ZCPR3 External Stack |
|||
EXTSTK EQU MEMTOP+1-48 ; ZCPR3 External Stack |
|||
EXTSTKS EQU YES |
|||
|
|||
; ZCPR3 Named Directory Buffer definition. |
|||
; FE00 - FFAF 432 Bytes Named Directory Buffer -23 names |
|||
Z3NDIRS EQU 23 ; Number of Named Directory Elements |
|||
; F800 - F8FF 256 Bytes Named Directory Buffer - 14 NAMES |
|||
NDIRSZ EQU Z3NDIRS * 18 + 1 |
|||
; (NDIR Size = Z3NDIRS * 18 + 1 = 433 Bytes) |
|||
Z3NDIR EQU ((EXTSTK-NDIRSZ)/256)*256 ; Start of Named Directory Buffer |
|||
|
|||
; The Multiple Command Line Buffer is placed in the Top Page of Memory to |
|||
; place it above the Environment. It is mandatory for ZCPR 3.3. |
|||
; FD00 - FDFF 256 Bytes |
|||
;Z3CL EQU 0FB00H ; ZCPR3 Command Line Buffer |
|||
;Z3CLS EQU 208-5 ; Size of Command Line Buffer-5 |
|||
Z3CLS EQU 256-5 ; Size of Command Line Buffer-5 |
|||
Z3CL EQU Z3NDIR-Z3CLS-5 ; ZCPR3 Command Line Buffer |
|||
|
|||
; The ZCPR3 External Environment Descriptor is mandatory B/P Bios & ZCPR 3.3. |
|||
; The Environment Descriptor MUST begin on an even Page Boundary (xx00H). |
|||
|
|||
; FC00 - FCFF 256 Bytes Environment Descriptor |
|||
Z3ENVS EQU 2 ; Size of Env Descriptor in 128-Byte Blks |
|||
Z3ENV EQU (Z3CL-Z3ENVS*128) and 0FF00H |
|||
|
|||
; The ZCPR3 Wheel Byte is mandatory for ZCPR 3.3. |
|||
|
|||
; FBFF 1 Byte Wheel byte |
|||
Z3WHLS EQU YES |
|||
Z3WHL EQU Z3ENV-1 ; Wheel Byte Address |
|||
|
|||
; The Path is mandatory for ZCPR 3.3. |
|||
|
|||
; FBF4 - FBFE 11 Bytes Path (5 elements) |
|||
EXPATHS EQU 5 ; (Path Size = EXPATHS*2 + 1 = 11 bytes) |
|||
; This defines 5 2-byte Path Elements |
|||
EXPATH EQU Z3WHL-EXPATHS*2-1 ; External Path starting Address |
|||
|
|||
; The ZCPR3 External FCB is mandatory for ZCPR 3.3. |
|||
|
|||
; FBD0 - FBF3 36 Bytes ZCPR3 External FCB |
|||
EXTFCBS EQU YES |
|||
EXFCBSZ EQU 36 |
|||
EXTFCB EQU EXPATH-EXFCBSZ ; 36-Byte ZCPR3 External FCB |
|||
|
|||
; The ZCPR3 Message Buffers are mandatory for ZCPR 3.3. |
|||
|
|||
; FB80 - FBCF 80 Bytes ZCPR3 Message Buffers |
|||
Z3MSGS EQU YES |
|||
Z3MSGSZ EQU 80 ; size of buffer |
|||
Z3MSG EQU EXTFCB-Z3MSGSZ ; 80-Byte ZCPR3 Message Buffer |
|||
|
|||
; Shell Stack definition. Set SHSTKS to 0 to eliminate Shell Stack |
|||
|
|||
; FB00 - FB7F 128 Bytes ZCPR3 Shell Stack |
|||
SHSTKS EQU 4 ; Number of SHSIZE-Byte Shell Stack entries |
|||
SHSIZE EQU 32 ; (Stack Size = SHSTKS * SHSIZE = 128 Bytes) |
|||
SHSTK EQU Z3MSG-SHSTKS*SHSIZE ; Shell Stack Starting Address |
|||
|
|||
; Flow Command Package definition. Set FCPS to 0 to eliminate FCP |
|||
|
|||
; F900 - FAFF 512 Bytes Flow Command Package |
|||
FCPS EQU 4 ; (FCP Size = 128 * FCPS = 512 Bytes) |
|||
;FCPS EQU 0 ; (FCP Size = 128 * FCPS = 512 Bytes) |
|||
FCP EQU SHSTK-FCPS*128 ; Start of Flow Command Package |
|||
|
|||
; Resident Command Processor Definition. Set RCPS to 0 to eliminate RCP |
|||
|
|||
; F900 - F900 0 KBytes Resident Command Package |
|||
;RCPS EQU 16 ; (RCP Size = 128 * RCPS = 2 kBytes) |
|||
RCPS EQU 0 ; (RCP Size = 128 * RCPS = 2 kBytes) |
|||
RCP EQU FCP-RCPS*128 ; Start of Resident Command Processor |
|||
|
|||
; IO Package definition. Set IOPS to 0 to eliminate IOP |
|||
|
|||
;IOP EQU 0EC00H ; Start of IO Package |
|||
; F900 - F900 0 KBytes IO Package |
|||
IOPS DEFL 0 ; (IOP Size = 128 * IOPS = 0 kBytes) |
|||
;IOPS DEFL 12 ; (IOP Size = 128 * IOPS = 1.5 kBytes) |
|||
;IOPS DEFL 10 ; (IOP Size = 128 * IOPS = 1.25 kBytes) |
|||
;OPS DEFL 3 ; (IOP Size = 128 * IOPS = 1.25 kBytes) |
|||
IOP EQU RCP-IOPS*128 ; Start of IO Package |
|||
|
|||
;========================================================================= |
|||
; Resident User Space Definition. Set USPCS to 0 to eliminate USPC. |
|||
; The USPC Value marks the Lower Limit of Reserved Common High Memory and |
|||
; MUST BE PRESENT! |
|||
|
|||
USPCS EQU 0 ; (USPC Size = 128 * USPCS = 0 kBytes) |
|||
;USPCS EQU 6 ; (USPC Size = 128 * USPCS = 0.75 kBytes) |
|||
; F900 - F900 0.75 KBytes Resident User Space |
|||
USPC EQU IOP-USPCS*128 ; Start of Resident User Space (MANDATORY) |
|||
|
|||
;--- End of Z3BASE.LIB --- |
|||
|
|||
@ -1,152 +0,0 @@ |
|||
; z3base.fp -- B/P Bios System Z3 Definition File for not or partially |
|||
; banked system with 32 byte external HBIOS proxy and |
|||
; internal proxy. |
|||
|
|||
; This file is adapted from the basic Z3BASE.LIB configuration file used for |
|||
; most ZCPR33 systems. It has added the new definitions for the Resident |
|||
; User Space defined in B/P Bios descriptions. |
|||
;========================================================================= |
|||
;== NOTE: The Starting Address of the User Space marks the lower == |
|||
;== base of memory and MUST be entered. B/P Bios Utilities use == |
|||
;== this address to locate many portions of the operating system. == |
|||
;========================================================================= |
|||
; To change your systems definition, first sketch out the memory map in the |
|||
; comment table, then set the equates to reflect the memory map, doing any |
|||
; required calculations for element sizes and required spaces. As an |
|||
; alternative, just leave this file alone and configure everything with |
|||
; the utilities provided. For example reserve top 1k for HBIOS and no IOP. |
|||
|
|||
; FFE0 - FFFF 32 Bytes HBIOS RESERVED AREA (mini proxy) |
|||
; FFB0 - FFDF 48 Bytes ZCPR3 External Stack (must be 48 bytes) |
|||
; FE00 - FFAF 432 Bytes Named Directory Buffer |
|||
; FD00 - FDFF 256 Bytes Multiple Command Line Buffer |
|||
; FC00 - FCFF 256 Bytes Environment Descriptor |
|||
; Bytes 00H-7FH: Z3 Parameters |
|||
; Bytes 80H-FFH: Z3 TCAP |
|||
; FBFF 1 Byte Wheel byte |
|||
; FBF4 - FAFE 11 Bytes Path (5 elements) |
|||
; FBD0 - FAF3 36 Bytes ZCPR3 External FCB |
|||
; FB80 - FACF 80 Bytes ZCPR3 Message Buffers |
|||
; FB00 - FA7F 128 Bytes ZCPR3 Shell Stack |
|||
; F900 - FAFF 512 Bytes Flow Command Package |
|||
; F100 - F8FF 2.0 KBytes Resident Command Package |
|||
; F100 - F100 0 KBytes IO Package - no IOP |
|||
; EE00 - F0FF 768 Bytes Resident User Space (room for clock driver) |
|||
|
|||
; The remainder is for the Operating System. Exact sizes vary depending |
|||
; primarily on the Number and sizes of Hard Drive Partitions, typically: |
|||
|
|||
; DC00 - EDFF 4.5 KBytes B/P BIOS (banked version) |
|||
; CE00 - DBFF 3.5 KBytes ZSDOS 1.0 BDOS |
|||
; C600 - CDFF 2 KBytes ZCPR 3.3 Command Processor |
|||
; 0100 - C5FF ~50 KBytes Transient Program Area |
|||
; 0000 - 00FF 256 Bytes Standard CP/M Buffers |
|||
;======================================================================== |
|||
|
|||
FALSE EQU 0 |
|||
TRUE EQU NOT FALSE |
|||
|
|||
YES EQU TRUE |
|||
NO EQU FALSE |
|||
|
|||
; The External Stack is placed in the very top position in memory. It is |
|||
; mandatory for B/P Bios and ZCPR 3.3. |
|||
|
|||
; FFB0 - FFDF 48 Bytes ZCPR3 External Stack (must be 48 bytes) |
|||
;EXTSTK EQU 0FBD0H ; ZCPR3 External Stack |
|||
EXTSTK EQU MEMTOP+1-48 ; ZCPR3 External Stack |
|||
EXTSTKS EQU YES |
|||
|
|||
; ZCPR3 Named Directory Buffer definition. |
|||
; FE00 - FFAF 432 Bytes Named Directory Buffer -23 names |
|||
Z3NDIRS EQU 23 ; Number of Named Directory Elements |
|||
; F800 - F8FF 256 Bytes Named Directory Buffer - 14 NAMES |
|||
NDIRSZ EQU Z3NDIRS * 18 + 1 |
|||
; (NDIR Size = Z3NDIRS * 18 + 1 = 433 Bytes) |
|||
Z3NDIR EQU ((EXTSTK-NDIRSZ)/256)*256 ; Start of Named Directory Buffer |
|||
|
|||
; The Multiple Command Line Buffer is placed in the Top Page of Memory to |
|||
; place it above the Environment. It is mandatory for ZCPR 3.3. |
|||
; FD00 - FDFF 256 Bytes |
|||
;Z3CL EQU 0FB00H ; ZCPR3 Command Line Buffer |
|||
;Z3CLS EQU 208-5 ; Size of Command Line Buffer-5 |
|||
Z3CLS EQU 256-5 ; Size of Command Line Buffer-5 |
|||
Z3CL EQU Z3NDIR-Z3CLS-5 ; ZCPR3 Command Line Buffer |
|||
|
|||
; The ZCPR3 External Environment Descriptor is mandatory B/P Bios & ZCPR 3.3. |
|||
; The Environment Descriptor MUST begin on an even Page Boundary (xx00H). |
|||
|
|||
; FC00 - FCFF 256 Bytes Environment Descriptor |
|||
Z3ENVS EQU 2 ; Size of Env Descriptor in 128-Byte Blks |
|||
Z3ENV EQU (Z3CL-Z3ENVS*128) and 0FF00H |
|||
|
|||
; The ZCPR3 Wheel Byte is mandatory for ZCPR 3.3. |
|||
|
|||
; FBFF 1 Byte Wheel byte |
|||
Z3WHLS EQU YES |
|||
Z3WHL EQU Z3ENV-1 ; Wheel Byte Address |
|||
|
|||
; The Path is mandatory for ZCPR 3.3. |
|||
|
|||
; FBF4 - FBFE 11 Bytes Path (5 elements) |
|||
EXPATHS EQU 5 ; (Path Size = EXPATHS*2 + 1 = 11 bytes) |
|||
; This defines 5 2-byte Path Elements |
|||
EXPATH EQU Z3WHL-EXPATHS*2-1 ; External Path starting Address |
|||
|
|||
; The ZCPR3 External FCB is mandatory for ZCPR 3.3. |
|||
|
|||
; FBD0 - FBF3 36 Bytes ZCPR3 External FCB |
|||
EXTFCBS EQU YES |
|||
EXFCBSZ EQU 36 |
|||
EXTFCB EQU EXPATH-EXFCBSZ ; 36-Byte ZCPR3 External FCB |
|||
|
|||
; The ZCPR3 Message Buffers are mandatory for ZCPR 3.3. |
|||
|
|||
; FB80 - FBCF 80 Bytes ZCPR3 Message Buffers |
|||
Z3MSGS EQU YES |
|||
Z3MSGSZ EQU 80 ; size of buffer |
|||
Z3MSG EQU EXTFCB-Z3MSGSZ ; 80-Byte ZCPR3 Message Buffer |
|||
|
|||
; Shell Stack definition. Set SHSTKS to 0 to eliminate Shell Stack |
|||
|
|||
; FB00 - FB7F 128 Bytes ZCPR3 Shell Stack |
|||
SHSTKS EQU 4 ; Number of SHSIZE-Byte Shell Stack entries |
|||
SHSIZE EQU 32 ; (Stack Size = SHSTKS * SHSIZE = 128 Bytes) |
|||
SHSTK EQU Z3MSG-SHSTKS*SHSIZE ; Shell Stack Starting Address |
|||
|
|||
; Flow Command Package definition. Set FCPS to 0 to eliminate FCP |
|||
|
|||
; F900 - FAFF 512 Bytes Flow Command Package |
|||
FCPS EQU 4 ; (FCP Size = 128 * FCPS = 512 Bytes) |
|||
;FCPS EQU 0 ; (FCP Size = 128 * FCPS = 512 Bytes) |
|||
FCP EQU SHSTK-FCPS*128 ; Start of Flow Command Package |
|||
|
|||
; Resident Command Processor Definition. Set RCPS to 0 to eliminate RCP |
|||
|
|||
; F100 - F8FF 2.0 KBytes Resident Command Package |
|||
RCPS EQU 16 ; (RCP Size = 128 * RCPS = 2 kBytes) |
|||
;RCPS EQU 0 ; (RCP Size = 128 * RCPS = 2 kBytes) |
|||
RCP EQU FCP-RCPS*128 ; Start of Resident Command Processor |
|||
|
|||
; IO Package definition. Set IOPS to 0 to eliminate IOP |
|||
|
|||
;IOP EQU 0EC00H ; Start of IO Package |
|||
; F100 - F100 0 KBytes IO Package |
|||
IOPS DEFL 0 ; (IOP Size = 128 * IOPS = 0 kBytes) |
|||
;IOPS DEFL 12 ; (IOP Size = 128 * IOPS = 1.5 kBytes) |
|||
;IOPS DEFL 10 ; (IOP Size = 128 * IOPS = 1.25 kBytes) |
|||
;OPS DEFL 3 ; (IOP Size = 128 * IOPS = 1.25 kBytes) |
|||
IOP EQU RCP-IOPS*128 ; Start of IO Package |
|||
|
|||
;========================================================================= |
|||
; Resident User Space Definition. Set USPCS to 0 to eliminate USPC. |
|||
; The USPC Value marks the Lower Limit of Reserved Common High Memory and |
|||
; MUST BE PRESENT! |
|||
|
|||
;USPCS EQU 0 ; (USPC Size = 128 * USPCS = 0 kBytes) |
|||
USPCS EQU 6 ; (USPC Size = 128 * USPCS = 0.75 kBytes) |
|||
; EE00 - F0FF 0.75 KBytes Resident User Space |
|||
USPC EQU IOP-USPCS*128 ; Start of Resident User Space (MANDATORY) |
|||
|
|||
;--- End of Z3BASE.LIB --- |
|||
|
|||
@ -1,149 +0,0 @@ |
|||
; z3base.fp -- B/P Bios System Z3 Definition File for not or partially |
|||
; banked system with 512 byte external HBIOS proxy (no |
|||
; internal proxy). |
|||
|
|||
; This file is adapted from the basic Z3BASE.LIB configuration file used for |
|||
; most ZCPR33 systems. It has added the new definitions for the Resident |
|||
; User Space defined in B/P Bios descriptions and modified for an HBIOS |
|||
; implementation with a full external HBIOS proxy (i.e. proxy not internal |
|||
; to BPBIOS). |
|||
; |
|||
;========================================================================= |
|||
;== NOTE: The Starting Address of the User Space marks the lower == |
|||
;== base of memory and MUST be entered. B/P Bios Utilities use == |
|||
;== this address to locate many portions of the operating system. == |
|||
;========================================================================= |
|||
; To change your systems definition, first sketch out the memory map in the |
|||
; comment table, then set the equates to reflect the memory map, doing any |
|||
; required calculations for element sizes and required spaces. As an |
|||
; alternative, just leave this file alone and configure everything with |
|||
; the utilities provided. |
|||
|
|||
; FE00 - FFFF 512 Bytes HBIOS proxy AREA in the top of ram |
|||
; FD00 - FDFF 256 Bytes Multiple Command Line Buffer |
|||
; FC00 - FCFF 256 Bytes Environment Descriptor |
|||
; Bytes 00H-7FH: Z3 Parameters |
|||
; Bytes 80H-FFH: Z3 TCAP |
|||
; FBFF 1 Byte Wheel byte |
|||
; FBF4 - FBFE 11 Bytes Path (5 elements) |
|||
; FBD0 - FBF3 36 Bytes ZCPR3 External FCB |
|||
; FB80 - FBCF 80 Bytes ZCPR3 Message Buffers |
|||
; FB00 - FB7F 128 Bytes ZCPR3 Shell Stack (4x32) |
|||
; FAD0 - FAFF 48 Bytes ZCPR3 External Stack (must be 48 bytes) |
|||
; F900 - FACF 464 Bytes Named Directory Buffer (25 entries) |
|||
; F700 - F9FF 512 Bytes Flow Command Package |
|||
; EF00 - F6FF 2.0 KBytes Resident Command Package |
|||
; EF00 - EF00 0 KBytes IO Package - no IOP |
|||
; EC00 - EEFF 768 Bytes Resident User Space (room for clock driver) |
|||
|
|||
; The remainder is for the Operating System. Exact sizes vary depending |
|||
; primarily on the Number and sizes of Hard Drive Partitions, typically: |
|||
|
|||
; E100 - EBFF 4.5 KBytes B/P BIOS (banked version) |
|||
; D300 - E0FF 3.5 KBytes ZSDOS 1.0 BDOS |
|||
; CB00 - D2FF 2 KBytes ZCPR 3.4 Command Processor |
|||
; 0100 - C5FF ~50 KBytes Transient Program Area |
|||
; 0000 - 00FF 256 Bytes Standard CP/M Buffers |
|||
;======================================================================== |
|||
|
|||
FALSE EQU 0 |
|||
TRUE EQU NOT FALSE |
|||
|
|||
YES EQU TRUE |
|||
NO EQU FALSE |
|||
|
|||
; The Multiple Command Line Buffer is mandatory for ZCPR 3.3. 3.4 & 4.1. |
|||
; FD00 - FDCF 208 Bytes |
|||
;Z3CL EQU 0FB00H ; ZCPR3 Command Line Buffer |
|||
Z3CLS EQU 256-5 ; Size of Command Line Buffer-5 |
|||
Z3CL EQU MEMTOP+1-Z3CLS-5 ; ZCPR3 Command Line Buffer |
|||
|
|||
; The ZCPR3 External Environment Descriptor is mandatory B/P Bios & ZCPR 3.3. |
|||
; The Environment Descriptor MUST begin on an even Page Boundary (xx00H). |
|||
; FC00 - FCFF 256 Bytes Environment Descriptor |
|||
Z3ENVS EQU 2 ; Size of Env Descriptor in 128-Byte Blks |
|||
Z3ENV EQU (Z3CL-Z3ENVS*128) and 0FF00H |
|||
|
|||
; The ZCPR3 Wheel Byte is mandatory for ZCPR 3.3. |
|||
|
|||
; FBFF 1 Byte Wheel byte |
|||
Z3WHLS EQU YES |
|||
Z3WHL EQU Z3ENV-1 ; Wheel Byte Address |
|||
|
|||
; The Path is mandatory for ZCPR 3.3. |
|||
|
|||
; FBF4 - FBFE 11 Bytes Path (5 elements) |
|||
EXPATHS EQU 5 ; (Path Size = EXPATHS*2 + 1 = 11 bytes) |
|||
; This defines 5 2-byte Path Elements |
|||
EXPATH EQU Z3WHL-EXPATHS*2-1 ; External Path starting Address |
|||
|
|||
; The ZCPR3 External FCB is mandatory for ZCPR 3.3. |
|||
|
|||
; FBD0 - FBF3 36 Bytes ZCPR3 External FCB |
|||
EXTFCBS EQU YES |
|||
EXFCBSZ EQU 36 |
|||
EXTFCB EQU EXPATH-EXFCBSZ ; 36-Byte ZCPR3 External FCB |
|||
|
|||
; The ZCPR3 Message Buffers are mandatory for ZCPR 3.3. |
|||
|
|||
; FB80 - FBCF 80 Bytes ZCPR3 Message Buffers |
|||
Z3MSGS EQU YES |
|||
Z3MSGSZ EQU 80 ; size of buffer |
|||
Z3MSG EQU EXTFCB-Z3MSGSZ ; 80-Byte ZCPR3 Message Buffer |
|||
|
|||
; Shell Stack definition. Set SHSTKS to 0 to eliminate Shell Stack |
|||
|
|||
; FB00 - FB7F 128 Bytes ZCPR3 Shell Stack |
|||
SHSTKS EQU 4 ; Number of SHSIZE-Byte Shell Stack entries |
|||
SHSIZE EQU 32 ; (Stack Size = SHSTKS * SHSIZE = 128 Bytes) |
|||
SHSTK EQU Z3MSG-SHSTKS*SHSIZE ; Shell Stack Starting Address |
|||
|
|||
; The External Stack is mandatory for B/P Bios and ZCPR 3.3, 3.4 & 4.1 |
|||
; FAD0 - FAFF 48 Bytes ; ZCPR3 External Stack (must be 48 bytes) |
|||
;EXTSTK EQU 0FAD0H ; ZCPR3 External Stack |
|||
EXTSTK EQU SHSTK-48 ; ZCPR3 External Stack |
|||
EXTSTKS EQU YES |
|||
|
|||
; ZCPR3 Named Directory Buffer definition. Set Z3NDIRS to 0 to eliminate |
|||
; the named directory buffer. |
|||
; F900 - FACF 464 Bytes ; Named Directory Buffer - 25 NAMES |
|||
Z3NDIRS EQU 25 ; Number of Named Directory Elements |
|||
NDIRSZ EQU Z3NDIRS * 18 + 1 |
|||
; (NDIR Size = Z3NDIRS * 18 + 1 = 451 Bytes) |
|||
Z3NDIR EQU SHSTK-(NDIRSZ/256+1)*256 ; Start of Named Directory Buffer |
|||
|
|||
; Flow Command Package definition. Set FCPS to 0 to eliminate FCP |
|||
|
|||
; F700 - F8FF 512 Bytes Flow Command Package |
|||
FCPS EQU 4 ; (FCP Size = 128 * FCPS = 512 Bytes) |
|||
;FCPS EQU 0 ; (FCP Size = 128 * FCPS = 0 Bytes) |
|||
FCP EQU Z3NDIR-FCPS*128 ; Start of Flow Command Package |
|||
|
|||
; Resident Command Processor Definition. Set RCPS to 0 to eliminate RCP |
|||
|
|||
; EF00 - F6FF 2.0 KBytes Resident Command Package |
|||
RCPS EQU 16 ; (RCP Size = 128 * RCPS = 2 kBytes) |
|||
;RCPS EQU 0 ; (RCP Size = 128 * RCPS = 0 kBytes) |
|||
RCP EQU FCP-RCPS*128 ; Start of Resident Command Processor |
|||
|
|||
; IO Package definition. Set IOPS to 0 which eliminates IOP |
|||
|
|||
;IOP EQU 0EC00H ; Start of IO Package |
|||
; EF00 - EF00 0 KBytes IO Package |
|||
IOPS DEFL 0 ; (IOP Size = 128 * IOPS = 0 kBytes) |
|||
;IOPS DEFL 12 ; (IOP Size = 128 * IOPS = 1.5 kBytes) |
|||
;IOPS DEFL 10 ; (IOP Size = 128 * IOPS = 1.25 kBytes) |
|||
IOP EQU RCP-IOPS*128 ; Start of IO Package |
|||
|
|||
;========================================================================= |
|||
; Resident User Space Definition. Set USPCS to 0 to eliminate USPC. |
|||
; The USPC Value marks the Lower Limit of Reserved Common High Memory and |
|||
; MUST BE PRESENT! |
|||
|
|||
;USPCS EQU 0 ; (USPC Size = 128 * USPCS = 0 kBytes) |
|||
USPCS EQU 6 ; (USPC Size = 128 * USPCS = 0.75 kBytes) |
|||
; EC00 - EEFF 0.75 KBytes Resident User Space |
|||
USPC EQU IOP-USPCS*128 ; Start of Resident User Space (MANDATORY) |
|||
|
|||
;--- End of Z3BASE.LIB --- |
|||
|
|||
@ -0,0 +1,16 @@ |
|||
;; Set the ZCPR and ZSDOS paths |
|||
C15:ZPATH $$$$ A0 B0 C15 C0 /D=$$$$ C15 C0 |
|||
;; Load ZCPR segments |
|||
jetldr RCP-16H.ZRL,FCP-4T.ZRL,BPBIO.NDR,NZDEC23D.Z3T |
|||
;; Load date/time extension |
|||
ldtimec |
|||
;; Initialize the RAM disk if needed and copy some useful file there |
|||
if ~EX A0:-RAM.000 |
|||
putds -d=A: |
|||
fileattr a0:*.dat /nd |
|||
save 0 a:-ram.000 |
|||
rcopy ramfiles.txt A0: /Q |
|||
fi |
|||
;; Load the command history shell and editor |
|||
lsh |
|||
|
|||
@ -1,16 +1,16 @@ |
|||
;; set the Zsystem and ZSDOS paths |
|||
;; Set the ZCPR and ZSDOS paths |
|||
C15:ZPATH $$$$ A0 B0 C15 C0 /D=$$$$ C15 C0 |
|||
;; enable clock and turn off last access stamping |
|||
;; Enable clock and turn off last access stamping |
|||
zscfg2 cb +a- |
|||
;; load Zsystem segments |
|||
jetldr BPBIO.NDR,nzdec23d.z3t,fcp-4t.zrl |
|||
;; initialize the RAM disk if needed and copy some useful file there |
|||
if ~EX A0:-ram.000 |
|||
;; Load ZCPR segments |
|||
jetldr FCP-4T.ZRL,BPBIO.NDR,NZDEC23D.Z3T |
|||
;; Initialize the RAM disk if needed and copy some useful file there |
|||
if ~EX A0:-RAM.000 |
|||
putds -d=A: |
|||
fileattr a0:*.dat /nd |
|||
save 0 a0:-ram.000 |
|||
RCOPY RAMFILES.TXT A0: /Q |
|||
rcopy ramfiles.txt A0: /Q |
|||
fi |
|||
;; load the command history shell and editor |
|||
LSH |
|||
|
|||
;; Load the command history shell and editor |
|||
lsh |
|||
|
|||
@ -1,13 +0,0 @@ |
|||
C15:ZPATH $$$$ A0 B0 C15 C0 /D=$$$$ C15 C0 |
|||
jetldr RCP-16H.ZRL,FCP-4T.ZRL,BPBIO.NDR,nzdec23d.z3t |
|||
ldtimee |
|||
;; initialize ram drive if needed |
|||
IF ~EX A0:-RAM.000 |
|||
putds -d=A: |
|||
fileattr a0:*.dat /nd |
|||
save 0 a:-ram.000 |
|||
RCOPY RAMFILES.TXT A0: /Q |
|||
FI |
|||
;; load command history shell and editor |
|||
LSH |
|||
|
|||
@ -1,13 +0,0 @@ |
|||
C15:ZPATH $$$$ A0 B0 C15 C0 /D=$$$$ C15 C0 |
|||
jetldr RCP-16H.ZRL,FCP-4T.ZRL,BPBIO.NDR,nzdec23d.z3t |
|||
ldtimec |
|||
;; initialize ram drive if needed |
|||
IF ~EX A0:-RAM.000 |
|||
putds -d=A: |
|||
fileattr a0:*.dat /nd |
|||
save 0 a:-ram.000 |
|||
RCOPY RAMFILES.TXT A0: /Q |
|||
FI |
|||
;; load command history shell and editor |
|||
LSH |
|||
|
|||
Binary file not shown.
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Reference in new issue