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Dynamic DS-1302 Detection

pull/48/head
Wayne Warthen 6 years ago
parent
commit
341c55945c
  1. 2
      Doc/ChangeLog.txt
  2. 429
      Doc/Contrib/FdTst.txt
  3. 2
      Doc/Contrib/ZSystem.txt
  4. 2
      ReadMe.txt
  5. 2
      Source/CBIOS/ver.inc
  6. 2
      Source/HBIOS/Config/RCZ180_ext.asm
  7. 2
      Source/HBIOS/Config/RCZ180_nat.asm
  8. 2
      Source/HBIOS/Config/RCZ80_kio.asm
  9. 2
      Source/HBIOS/Config/RCZ80_std.asm
  10. 2
      Source/HBIOS/cfg_ezz80.asm
  11. 2
      Source/HBIOS/cfg_rcz180.asm
  12. 2
      Source/HBIOS/cfg_rcz80.asm
  13. 134
      Source/HBIOS/dsrtc.asm
  14. 17
      Source/HBIOS/hbios.asm
  15. 2
      Source/HBIOS/ver.inc
  16. BIN
      Source/ZSDOS/Distribution/ZCAL.COM

2
Doc/ChangeLog.txt

@ -19,6 +19,8 @@ Version 2.9.2
- WBW: Fix floppy I/O error on slow CPUs w/ ints active (credit Jorge Rodrigues) - WBW: Fix floppy I/O error on slow CPUs w/ ints active (credit Jorge Rodrigues)
- WBW: Support for KIO chip (based on board by Tom Szolyga) - WBW: Support for KIO chip (based on board by Tom Szolyga)
- N?B: Made ZCAL Y2K compliant - N?B: Made ZCAL Y2K compliant
- WBW: Show disk activity on diagnostic LEDs
- WBW: DSRTC now detects DS-1302 presence dynamically
Version 2.9.1 Version 2.9.1
------------- -------------

429
Doc/Contrib/FdTst.txt

@ -1,429 +0,0 @@
================================================================
FDTST v3.1 for N8VEM DISKIO / DISKIO V3 / ZETA / DIDE / N8
================================================================
Updated JuLY 1, 2012
by Wayne Warthen (wwarthen@gmail.com)
Application to test the hardware functionality of the Floppy Disk
Controller (FDC) on the ECB DISK I/O, DISK I/O V3, ZETA SBC,
Dual IDE w/ Floppy, or N8 board.
The intent is to provide a testbed that allows direct testing
of all possible media types and modes of access. The application
supports read, write, and format by sector, track, and disk as
well as a random read/write test.
The application supports access modes of polling, interrupt,
INT/WAIT, and DRQ/WAIT. At present, it supports 3.5" media at DD (720KB) and
HD (1.44MB) capacities. It also now supports 5.25" media (720KB and 1.2MB)
and 8" media (1.11MB) as well. Additonal media will be added when I have
time and access to required hardware. Not all modes are supported
on all platforms and some modes are experimental in all cases.
In many ways this application is merely reinventing the wheel and
performs functionality similer to existing applications, but I have
not seen any other applications for DISK I/O that provide this range
of functionality.
While the application is now almost entirely new code, I would like to
acknowledge that much was derived from the previous work of Andrew Lynch
and Dan Werner. I also want to credit Sergio Gimenez with testing the 5.25"
drive support and Jim Harre with testing the 8" drive support. Thanks!
General Usage
-------------
In general, usage is self explanatory. The main menu allows you to set
the unit, media, and mode to test. These settings MUST match your
situation. Read, write, format, and verify functions are provided. A sub-menu
will allow you to choose sector, track, disk, or random tests.
The verify function requires a little explanation. It will take the contents
of the buffer, save it, and compare it to the selected sectors. So, you
must ensure that the sectors to be verified already have been written
with the same pattern as the buffer contains. I typically init the buffer
to a pattern, write the pattern to the entire disk, then verify the entire
disk.
Another submenu is provided for FDC commands. This sub-menu allows you to
send low-level commands directly to FDC. You MUST know what you are doing
to use this sub-menu. For example, in order to read a sector using this
sub-menu, you will need to perform specify, seek, sense int, and read
commands specifying correct values (nothing is value checked in this menu).
Required Hardware/BIOS
----------------------
Of course, the starting point is one of the support hardware platforms.
You need to start with either an N8VEM SBC, backplane, and ECB DISK I/O
card or a Zeta SBC. Additionally, a floppy drive connected via an
appropriate cable:
DISKIO - no twist in cable, drive unit 0/1 must be selected by jumper on drive
ZETA - cable with twist, unit 0 after twist, unit 1 before twist
DIDE/N8 - cable with twist, unit 0 before twist, unit 1 after twist
It is preferable that the BIOS you use does not have DISK I/O support
enabled since the application assumes it has complete control of the
DISK I/O hardware.
The DISK I/O should be jumpered as follows:
J1: depends on use of interrupt modes (see interrupt modes below)
J2: pins 1-2, & 3-4 jumpered
J3: hardware dependent timing for DMA mode (see DMA modes below)
J4: pins 2-3 jumpered
J5: off
J6: pins 2-3 jumpered
J7: pins 2-3 jumpered
J8: off
J9: off
J10: off
J11: off
J12: off
Note that J1 can be left on even when not using interrupt modes. As
long as the BIOS is OK with it, that is fine. Note also that J3 is
only relevant for DMA modes, but also can be left in place when
using other modes.
The DISK I/O V3 should be jumpered at the default settings:
JP2: 3-4
JP3: 1-2 for int mode support, otherwise no jumper
JP4: 1-2, 3-4
JP5: 1-2
JP6: 1-2
JP7: 1-2, 3-4
Zeta does not have any relevant jumper settings.
DIDE should be jumpered as follows:
K3 (DT/R or /RD): /RD
P5 (bd ID): 1-2, 3-4 (for $20-$3F port range)
There are no specific N8 jumper settings, but the default
I/O range starting at $80 is assumed in the published code.
Modes of Operation
------------------
You can select the following test modes. Please refer to the chart
that follows to determine which modes should work with combinations
of Z80 CPU speed and media format.
Polling: Traditional polled input/output. Works well and very reliable
including timeouts and good error recovery. Also, the slowest performance
which precludes it from being used with 1.44MB floppy on a 4MHz Z80.
This is definitely the mode you want to get working before any others.
It does not require J1 (interrupt enable) on DISK I/O and does not care about
the setting of J3.
Interrupt: Input/output is interrupt driven. Works pretty well, but
is not able to recover from some errors. For example, if there is
no disk in the drive, this mode will just hang until a disk is inserted.
This mode REQUIRES that interrupts be enabled on the DISK I/O via
jumper at J1. On Zeta it requires the INT/NMI jumper be set for
INT. Mode not supported on DIDE or N8. Some BIOS variants will not
handle interrupts during boot.
Fast Interrupt: As above, but sacrifices additional reliability for
faster operation. This mode will allow a 1.44MB floppy to work
with a 4MHz Z80 CPU. However, if any errors occur (even a transient
read error which is not unusual), this mode will hang. As above
you MUST have the appropriate jumpers for DISKIO and Zeta. DIDE
does not support this mode.
INT/WAIT: Same as Fast Interrupt, but uses CPU wait instead of
actual interrupt. Subject to all the same issues as Fast
Interrupt, but does not need J1 shorted. J3 is irrelevant.
This mode is available on only on DISKIO (and not DISKIO V3).
DRQ/WAIT: Uses pseudo DMA to handle input/output. Does not require that
interrupts (J1) be enabled on the DISK I/O. However, it is subject to
all of the same reliability issues as "Fast Interrupt". This
mode is known to not work on N8VEM DISKIO!!! It is included
for testing only. It is dependent on setting of J3. This
mode is NOT available on Zeta, DIDE, N8, or DISKIO V3.
The chart below attempts to describe the combinations that
work for me. By far, the most reliable mode is Polling,
but it requires 8MHz CPU for HD disks.
DRQ/WAIT --------------------------------+
INT/WAIT -----------------------------+ |
Fast Interrupt --------------------+ | |
Interrupt ----------------------+ | | |
Polling ---------------------+ | | | |
| | | | |
CPU Speed --------------+ | | | | |
| | | | | |
| | | | | |
3.5" DD (720K) ------ 4MHz Y Y Y Y X
8MHz+ Y Y Y Y X
3.5" HD (1.44M) ----- 4MHz N N Y Y X
8MHz+ Y Y Y Y X
5.25" DD (360K) ----- 4MHz Y Y Y Y X
8MHz+ Y Y Y Y X
5.25" HD (1.2M) ----- 4MHz N N Y Y X
8MHz+ Y Y Y Y X
8" DD (1.11M) ------- 4MHz N N Y Y X
8MHz+ Y Y Y Y X
Y = Yes, works
N = No, does not work
X = Experimental, probably won't work
Tracing
-------
Command/result activity to/from the FDC will be written out
if the trace setting is changed from '00' to '01' in setup.
Additionally, if a command failure is detected on any
command, that specific comand and results are written
regardless of the trace setting.
The format of the line written is:
<OPERATION>: <COMMAND BYTES> --> <RESULT BYTES> [<RESULT>]
For example, this is the output of a normal read operation:
READ: 46 01 00 00 01 02 09 1B FF --> 01 00 00 00 00 02 02 [OK]
Please refer to the i8272 data sheet for information on the
command and result bytes.
Note that the sense interrupt command can return a non-OK
result. This is completely normal in some cases. It is
necessary to "poll" the drive for seek status using
sense interrupt. If there is nothing to report, then
the result will be INVALID COMMAND. Additionally,
during a recalibrate operation, it may be necessary to
issue the command twice because the command will only step
the drive 77 times looking for track 0, but the head may be
up to 80 tracks away. In this case, the first recalibrate
fails, but the second should succeed. Here is what this
would look like if trace is turned on:
RECALIBRATE: 07 01 --> <EMPTY> [OK]
SENSE INTERRUPT: 08 --> 80 [INVALID COMMAND]
...
...
...
SENSE INTERRUPT: 08 --> 80 [INVALID COMMAND]
SENSE INTERRUPT: 08 --> 71 00 [ABNORMAL TERMINATION]
RECALIBRATE: 07 01 --> <EMPTY> [OK]
SENSE INTERRUPT: 08 --> 21 00 [OK]
Another example is when the FDC has just been reset. In
this case, you will see up to 4 disk change errors. Again
these are not a real problem and to be expected.
When tracing is turned off, the application tries to be
intelligent about error reporting. The specific errors
from sense interrupt documented above will be suppressed
because they are not a real problem. All other
errors will be displayed.
Error Handling
--------------
There is no automated error retry logic. This is very
intentional since the point is to expose the controller
and drive activity. Any error detected will result in
a prompt to abort, retry, or continue. Note that some
number of errors is considered normal for this
technology. An occasional error would not necessarily
be considered a problem.
CPU Speed
---------
I distribute the binary version of the application optimized for
20MHz CPUs. There is a configuration variable called CPUFREQ
at the top of the source file. Ideally, you should build
with that set appropriately. However, I have found that the
default build setting of 20MHz seems to work for 4-20MHz CPUs.
Interleave
----------
The format command now allows the specification of a sector
interleave. It is almost always the case that the optimal
interleave will be 2 (meaning 2:1).
360K Media
----------
The 360K media definition should work well for true 360K
drives. However, it will generally not work
with 1.2M drives. This is because these drives spin at 360RPM
instead of the 300RPM speed of true 360K drives. Additionally,
1.2M drives are 80 tracks and 360K drives are 40 tracks and, so
far, there is no mechanism in FDTST to "double step" as a way
to use 40 track media in 80 track drives.
With this said, it is possible to configure some 1.2M 5.25" drives
to automatically spin down to 300RPM based on a density select
signal (DENSEL). This signal is asserted by FDTST for 360K
media, so IF you have configured your drive to react to this
signal correctly, you will be able to use the 360K media defintion.
Most 1.2M 5.25" drives are NOT configured this way by default.
TEAC drives are generally easy to modify and have been tested by
the author and do work in this manner. Note that this does not
address the issue of double stepping above; you will just be
using the first 40 of 80 tracks.
Support
-------
I am happy to answer questions as fast and well as I am able.
Best contact is wwarthen@gmail.com or post something on the
N8VEM Google Group https://groups.google.com/forum/#!forum/n8vem.
Changes
-------
WW 8/12/2011
Removed call to pulse TC in the FDC initialization
after determining that it periodically caused the FDC to write
bad sectors. I am mystified by this, but definitely found it
to be true. Will revisit at some point -- probably a timing
issue between puslsing TC and whatever happens next.
Non-DMA mode was being set incorrectly for FAST-DMA mode.
It was set for non-DMA even though we were doing DMA. It is
interesting that it worked fine anyway. Fixed it anyway.
DIO_SETMEDIA was not clearing DCD_DSKRDY as it should. Fixed.
WW 8/26/2011: v1.1
Added support for Zeta. Note that INT/WAIT and DRQ/WAIT are
not available on Zeta. Note that Zeta provides the ability
to perform a reset of the FDC independent of a full CPU
reset. This is VERY useful and the FDC is reset anytime
a drive reset is required.
Added INT/WAIT support.
WW 8/28/2011: V1.2
All changes in this version are Zeta specific. Fixed FDC reset
logic and motor status display for Zeta (code from Sergey).
Modified Zeta disk change display to include it in the
command output line. This makes more sense because a command
must be issued to select the desired drive first. You can
use the SENSE INT command id you want to check the disk
change value at any time. It will also be displayed with
any other command output display.
WW 9/1/2011: V1.3
Added CPUFREQ configuration setting to tune
delays based on cpu speed. The build app
is set for 8MHz which also seems to work well
for 4MHz CPU's. Faster CPU speeds will
probably require tuning this setting.
WW 9/5/2011: V1.4
Changed the polling execution routines to utilize CPUFREQ
variable to optimize timeout counter. Most importantly,
this should allow the use of faster CPUs (like 20MHz).
WW 9/19/2011: V1.5
Zeta changes only. Added a call to FDC RESET after any
command failure. This solves an issue where the drive
remains selected if a command error occurs. Also
added FDC RESET to FDC CONTROL menu.
WW 10/7/2011: V2.0
Added support for DIDE. Only supports polling IO and it
does not appear any other modes are possible given the
hardware constraints.
WW 10/13/2011: V2.1
Modified to support N8. N8 is essentially identical to
Dual IDE. The only real change is the IO addresses. In
theory, I should be able to support true DMA on N8 and
will work on that.
WW 10/20/2011: v2.2
I had some problems with the results being read were
sometimes missing a byte. Fixed this by taking a more
strict approach to watching the MSR for the exact
bits that are expected.
WW 10/22/2011: V2.3
After spending a few days trying to track down an
intermittent data corruption issue with my Dual IDE
board, I added a verify function. This helped
me isolate the problem very nicely (turned out to
be interference from the bus monitor).
WW 11/25/2011: V2.4
Preliminary support for DISKIO V3. Basically just
assumed that it operates just like the Zeta. Needs
to be verified with real hardware as soon as I can.
WW 1/9/2012: V2.5
Modified program termination to use CP/M reset
call so that a warm start is done and all
drives are logged out. This is important
because media may have been formatted during
the program execution.
WW 2/6/2012: v2.6
Added support for 5.25" drives as tested by
Sergio.
WW 4/5/2012: v2.7
Added support for 8" drives as tested by
Jim Harre.
WW 4/6/2012: v2.7a
Fixed issue with media selection menu to remove
duplicate entries.
WW 4/8/2012: v2.7b
Corrected the handling of the density select
signal.
WW 5/22/2012: v2.8
Added new media definitions (5.25", 320K)
WW 6/1/2012: v2.9
Added interleave capability on format
WW 6/5/2012: v3.0
Documentation cleanup
WW 7/1/2012: v3.1
Modified head load time (HLT) for 8" media based on
YD-180 spec. Now set to 50ms.

2
Doc/Contrib/ZSystem.txt

@ -32,6 +32,8 @@ The remainder of this document details the changes I made as I went along. In a
6. Updated FILEATTR to v1.6A. Original FILEATTR.CFG was invalid. FILEATTR.CFG replaced with FA16.CFG. Added associated files FA16.DOC, FA16A.FOR, FA16CFG.TXT. 6. Updated FILEATTR to v1.6A. Original FILEATTR.CFG was invalid. FILEATTR.CFG replaced with FA16.CFG. Added associated files FA16.DOC, FA16A.FOR, FA16CFG.TXT.
7. ZCAL patched to be Y2K compliant. Contributed by Nick Brok.
Usage Notes Usage Notes
----------- -----------

2
ReadMe.txt

@ -7,7 +7,7 @@
*********************************************************************** ***********************************************************************
Wayne Warthen (wwarthen@gmail.com) Wayne Warthen (wwarthen@gmail.com)
Version 2.9.2-pre.11, 2019-09-20
Version 2.9.2-pre.12, 2019-09-29
https://www.retrobrewcomputers.org/ https://www.retrobrewcomputers.org/
RomWBW is a ROM-based implementation of CP/M-80 2.2 and Z-System for RomWBW is a ROM-based implementation of CP/M-80 2.2 and Z-System for

2
Source/CBIOS/ver.inc

@ -2,4 +2,4 @@
#DEFINE RMN 9 #DEFINE RMN 9
#DEFINE RUP 2 #DEFINE RUP 2
#DEFINE RTP 0 #DEFINE RTP 0
#DEFINE BIOSVER "2.9.2-pre.11"
#DEFINE BIOSVER "2.9.2-pre.12"

2
Source/HBIOS/Config/RCZ180_ext.asm

@ -32,8 +32,6 @@ Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3) Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3)
Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
; ;
DSRTCENABLE .SET FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
;
ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)

2
Source/HBIOS/Config/RCZ180_nat.asm

@ -32,8 +32,6 @@ Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3) Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3)
Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
; ;
DSRTCENABLE .SET FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
;
ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)

2
Source/HBIOS/Config/RCZ80_kio.asm

@ -33,8 +33,6 @@ KIOENABLE .SET TRUE ; ENABLE ZILOG KIO SUPPORT
CTCENABLE .SET TRUE ; ENABLE ZILOG CTC SUPPORT CTCENABLE .SET TRUE ; ENABLE ZILOG CTC SUPPORT
CTCBASE .SET KIOBASE+$04 ; CTC BASE I/O ADDRESS CTCBASE .SET KIOBASE+$04 ; CTC BASE I/O ADDRESS
; ;
DSRTCENABLE .SET FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
;
ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
SIOCNT .SET 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP SIOCNT .SET 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP

2
Source/HBIOS/Config/RCZ80_std.asm

@ -27,8 +27,6 @@
CPUOSC .SET 7372800 ; CPU OSC FREQ IN MHZ CPUOSC .SET 7372800 ; CPU OSC FREQ IN MHZ
DEFSERCFG .SET SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) DEFSERCFG .SET SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
; ;
DSRTCENABLE .SET FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
;
ACIAENABLE .SET TRUE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) ACIAENABLE .SET TRUE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
; ;

2
Source/HBIOS/cfg_ezz80.asm

@ -56,7 +56,7 @@ ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT
SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
; ;
DSRTCENABLE .EQU FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
DSRTCENABLE .EQU TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC] DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
; ;

2
Source/HBIOS/cfg_rcz180.asm

@ -60,7 +60,7 @@ ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT
SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
; ;
DSRTCENABLE .EQU FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
DSRTCENABLE .EQU TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC] DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
; ;

2
Source/HBIOS/cfg_rcz80.asm

@ -55,7 +55,7 @@ ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT
SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
; ;
DSRTCENABLE .EQU FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
DSRTCENABLE .EQU TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC] DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
; ;

134
Source/HBIOS/dsrtc.asm

@ -122,6 +122,34 @@ DSRTC_IDLE .EQU %00101000 ; QUIESCENT STATE
; ;
DSRTC_BUFSIZ .EQU 7 ; 7 BYTE BUFFER (YYMMDDHHMMSSWW) DSRTC_BUFSIZ .EQU 7 ; 7 BYTE BUFFER (YYMMDDHHMMSSWW)
; ;
; RTC DEVICE PRE-INITIALIZATION ENTRY
;
DSRTC_PREINIT:
;
; SET RELEVANT BITS IN RTC LATCH SHADOW REGISTER
; TO THEIR QUIESENT STATE
LD A,(RTCVAL) ; GET CURRENT SHADOW REG VAL
AND DSRTC_MASK ; CLEAR OUR BITS
OR DSRTC_IDLE ; SET OUR IDLE BITS
LD (RTCVAL),A ; SAVE IT
;
CALL DSRTC_DETECT ; HARDWARE DETECTION
LD (DSRTC_STAT),A ; SAVE RESULT
RET NZ ; ABORT IF ERROR
;
; CHECK FOR CLOCK HALTED
CALL DSRTC_TSTCLK
JR Z,DSRTC_PREINIT1
;PRTS(" INIT CLOCK $")
LD HL,DSRTC_TIMDEF
CALL DSRTC_TIM2CLK
LD HL,DSRTC_BUF
CALL DSRTC_WRCLK
;
DSRTC_PREINIT1:
XOR A ; SIGNAL SUCCESS
RET ; DONE
;
; RTC DEVICE INITIALIZATION ENTRY ; RTC DEVICE INITIALIZATION ENTRY
; ;
DSRTC_INIT: DSRTC_INIT:
@ -135,21 +163,16 @@ DSRTC_INIT:
PRTS("MFPIC$") PRTS("MFPIC$")
#ENDIF #ENDIF
; ;
; SET RELEVANT BITS IN RTC LATCH SHADOW REGISTER
; TO THEIR QUIESENT STATE
LD A,(RTCVAL)
AND DSRTC_MASK
OR DSRTC_IDLE
LD (RTCVAL),A
LD A,(DSRTC_STAT)
OR A
JR Z,DSRTC_INIT0
; ;
; CHECK FOR CLOCK HALTED
CALL DSRTC_TSTCLK
JR Z,DSRTC_INIT1
PRTS(" INIT CLOCK $")
LD HL,DSRTC_TIMDEF
CALL DSRTC_TIM2CLK
LD HL,DSRTC_BUF
CALL DSRTC_WRCLK
; HARDWARE NOT PRESENT
PRTS(" NOT PRESENT$")
OR $FF ; SIGNAL FAILURE
RET
;
DSRTC_INIT0:
; ;
DSRTC_INIT1: DSRTC_INIT1:
; DISPLAY CURRENT TIME ; DISPLAY CURRENT TIME
@ -214,8 +237,6 @@ DSRTC_DISPATCH:
; ;
; NVRAM FUNCTIONS ARE NOT AVAILABLE IN SIMULATOR ; NVRAM FUNCTIONS ARE NOT AVAILABLE IN SIMULATOR
; ;
DSRTC_GETBYT:
DSRTC_SETBYT:
DSRTC_GETBLK: DSRTC_GETBLK:
DSRTC_SETBLK: DSRTC_SETBLK:
CALL PANIC CALL PANIC
@ -289,6 +310,56 @@ DSRTC_SETTIM:
XOR A ; SIGNAL SUCCESS XOR A ; SIGNAL SUCCESS
RET ; AND RETURN RET ; AND RETURN
; ;
; RTC GET NVRAM BYTE
; C: INDEX
; E: VALUE (OUTPUT)
;
DSRTC_GETBYT:
LD A,C ; INDEX
SLA A ; SHIFT TO INDEX BITS
ADD A,$C1 ; CMD OFFSET
LD E,A
CALL DSRTC_CMD
CALL DSRTC_GET
CALL DSRTC_END
XOR A
RET
;
; RTC SET NVRAM BYTE
; C: INDEX
; E: VALUE
;
DSRTC_SETBYT:
PUSH DE ; SAVE INCOMING INDEX
;
; TURN OFF WRITE PROTECT
LD E,$8E ; ACCESS WRITE PROT REG
CALL DSRTC_CMD ;
LD E,$00 ; WRITE PROTECT OFF
CALL DSRTC_PUT ;
CALL DSRTC_END ; FINISH CMD
;
; SET REGISTER VALUE
LD A,C ; INDEX
SLA A ; SHIFT TO INDEX BITS
ADD A,$C0 ; CMD OFFSET
LD E,A ; INTO E
CALL DSRTC_CMD
POP DE
CALL DSRTC_PUT
CALL DSRTC_END
;
; TURN ON WRITE PROTECT
LD E,$8E ; ACCESS WRITE PROT REG
CALL DSRTC_CMD ;
LD E,$80 ; WRITE PROTECT ON
CALL DSRTC_PUT ;
CALL DSRTC_END ; FINISH CMD
;
; SIGNAL SUCCESS
XOR A
RET
;
; CONVERT DATA IN CLOCK BUFFER TO TIME BUFFER AT HL ; CONVERT DATA IN CLOCK BUFFER TO TIME BUFFER AT HL
; ;
DSRTC_CLK2TIM: DSRTC_CLK2TIM:
@ -350,6 +421,34 @@ DSRTC_TSTCHG:
CP %10100000 ; ENABLED FLAG CP %10100000 ; ENABLED FLAG
RET RET
; ;
; DETECT RTC HARDWARE PRESENCE
;
DSRTC_DETECT:
LD C,31 ; NVRAM INDEX 31
CALL DSRTC_GETBYT ; GET VALUE
LD A,E ; TO ACCUM
LD (DSRTC_TEMP),A ; SAVE IT
XOR $FF ; FLIP ALL BITS
LD E,A ; TO E
LD C,31 ; NVRAM INDEX 31
CALL DSRTC_SETBYT ; WRITE IT
LD C,31 ; NVRAM INDEX 31
CALL DSRTC_GETBYT ; GET VALUE
LD A,(DSRTC_TEMP) ; GET SAVED VALUE
XOR $FF ; FLIP ALL BITS
CP E ; COMPARE WITH VALUE READ
LD A,0 ; ASSUME OK
JR Z,DSRTC_DETECT1 ; IF MATCH, GO AHEAD
LD A,$FF ; ELSE STATUS IS ERROR
DSRTC_DETECT1:
PUSH AF ; SAVE STATUS
LD A,(DSRTC_TEMP) ; GET SAVED VALUE
LD C,31 ; NVRAM INDEX 31
CALL DSRTC_SETBYT ; SAVE IT
POP AF ; RECOVER STATUS
OR A ; SET FLAGS
RET ; DONE
;
; TEST CLOCK FOR VALID DATA ; TEST CLOCK FOR VALID DATA
; READ CLOCK HALT BIT AND RETURN ZF BASED ON BIT VALUE ; READ CLOCK HALT BIT AND RETURN ZF BASED ON BIT VALUE
; 0 = RUNNING ; 0 = RUNNING
@ -524,6 +623,9 @@ DSRTC_END:
; ;
; WORKING VARIABLES ; WORKING VARIABLES
; ;
DSRTC_STAT .DB 0 ; DEVICE STATUS (0=OK)
DSRTC_TEMP .DB 0 ; TEMP VALUE STORAGE
;
; DSRTC_BUF IS USED FOR BURST READ/WRITE OF CLOCK DATA TO DS-1302 ; DSRTC_BUF IS USED FOR BURST READ/WRITE OF CLOCK DATA TO DS-1302
; FIELDS BELOW MATCH ORDER OF DS-1302 FIELDS (BCD) ; FIELDS BELOW MATCH ORDER OF DS-1302 FIELDS (BCD)
; ;

17
Source/HBIOS/hbios.asm

@ -1273,6 +1273,10 @@ HB_CPU1:
; ;
#ENDIF #ENDIF
; ;
#IF (DSRTCENABLE)
CALL DSRTC_PREINIT
#ENDIF
;
#IF (CPUFAM == CPU_Z180) #IF (CPUFAM == CPU_Z180)
; ;
; AT BOOT, Z180 PHI IS OSC / 2 ; AT BOOT, Z180 PHI IS OSC / 2
@ -1351,7 +1355,6 @@ HB_CPU2:
; ;
; PRE-CONSOLE INITIALIZATION ; PRE-CONSOLE INITIALIZATION
; ;
LD A,FORCECON ; CALCULATE PRE-INIT TABLE ; A IS INDEX OF CONSOLE DEVICE ENTRY LD A,FORCECON ; CALCULATE PRE-INIT TABLE ; A IS INDEX OF CONSOLE DEVICE ENTRY
RLCA ; ENTRY THAT WE WANT TO ; A IS OFFSET OF CONSOLE DEVICE ENTRY RLCA ; ENTRY THAT WE WANT TO ; A IS OFFSET OF CONSOLE DEVICE ENTRY
LD DE,(PC_INITTBL) ; EXECUTE FIRST ; DE IS VALUE OF TOP ENTRY LD DE,(PC_INITTBL) ; EXECUTE FIRST ; DE IS VALUE OF TOP ENTRY
@ -3195,15 +3198,9 @@ HB_CPUSPD:
; ;
#IF (DSRTCENABLE) #IF (DSRTCENABLE)
; ;
CALL DSRTC_TSTCLK ; IS CLOCK RUNNING?
JR Z,HB_CPUSPD1 ; YES, CONTINUE
; MAKE SURE CLOCK IS RUNNING
LD HL,DSRTC_TIMDEF
CALL DSRTC_TIM2CLK
LD HL,DSRTC_BUF
CALL DSRTC_WRCLK
CALL DSRTC_TSTCLK ; NOW IS CLOCK RUNNING?
RET NZ
LD A,(DSRTC_STAT) ; GET RTC STATUS
OR A ; SET FLAGS
RET NZ ; NOT ZERO IS ERROR
; ;
HB_CPUSPD1: HB_CPUSPD1:
#IF (CPUFAM == CPU_Z180) #IF (CPUFAM == CPU_Z180)

2
Source/HBIOS/ver.inc

@ -2,4 +2,4 @@
#DEFINE RMN 9 #DEFINE RMN 9
#DEFINE RUP 2 #DEFINE RUP 2
#DEFINE RTP 0 #DEFINE RTP 0
#DEFINE BIOSVER "2.9.2-pre.11"
#DEFINE BIOSVER "2.9.2-pre.12"

BIN
Source/ZSDOS/Distribution/ZCAL.COM

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