mirror of https://github.com/wwarthen/RomWBW.git
drj113
1 year ago
13 changed files with 1026 additions and 72 deletions
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; |
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;================================================================================================== |
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; STD Z180 STANDARD CONFIGURATION |
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;================================================================================================== |
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; |
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; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE |
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; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS |
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; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE |
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; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS. |
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; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY |
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; YOUR FILE IN THE BUILD PROCESS. |
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; |
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; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM. |
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; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO |
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; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON |
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; SETTINGS. |
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; |
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; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE, |
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; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING |
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; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS! |
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; |
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; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO |
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; DIRECTORIES ABOVE THIS ONE). |
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; |
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#DEFINE PLATFORM_NAME "GM STD BUS Z180", " [", CONFIG, "]" |
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; |
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#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT |
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; |
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#include "cfg_GMZ180.asm" |
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; |
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CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ |
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CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP |
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; |
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Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2 |
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Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3) |
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Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) |
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; |
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LEDENABLE .SET FALSE ; ENABLE STATUS LED (SINGLE LED) |
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LEDMODE .SET LEDMODE_STD ; LEDMODE_[STD|SC|RTC|NABU] |
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; |
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FPLED_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL LEDS |
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FPLED_IO .SET $00 ; FP: PORT ADDRESS FOR FP LEDS |
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; |
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DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) |
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INTRTCENABLE .SET TRUE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) |
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; |
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UARTENABLE .SET FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) |
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ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) |
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ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) |
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SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) |
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; |
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TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) |
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TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) |
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TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO] |
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MKYENABLE .SET FALSE ; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER) |
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EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) |
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VDAEMU_SERKBD .SET 0 ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD |
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; |
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AY38910ENABLE .SET FALSE ; AY: AY-3-8910 / YM2149 SOUND DRIVER |
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AYMODE .SET AYMODE_RCZ180 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC] |
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SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER |
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; |
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FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) |
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FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC] |
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; |
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IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) |
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PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) |
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SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) |
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SDMODE .SET SDMODE_GM ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR] |
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SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY |
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; |
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PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) |
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@ -0,0 +1,358 @@ |
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; |
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;================================================================================================== |
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; ROMWBW 3.X CONFIGURATION DEFAULTS FOR GENESIS MODULES STD BUS BASED Z180 VARIANTS |
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;================================================================================================== |
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; |
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; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM |
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; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD |
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; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY |
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; UNDER THIS DIRECTORY. |
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; |
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; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS |
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; FOR THE PLATFORM. |
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; |
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#DEFINE PLATFORM_NAME "GM STD BUS Z180", " [", CONFIG, "]" |
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; |
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#INCLUDE "hbios.inc" |
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; |
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PLATFORM .EQU PLT_GMZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON] |
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CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280] |
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BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] |
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BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE |
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HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) |
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USELZSA2 .EQU TRUE ; ENABLE FONT COMPRESSION |
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TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ) |
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; |
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BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE |
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BOOT_DELAY .EQU 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT |
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AUTOCON .EQU TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT |
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; |
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CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO |
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CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW |
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CPUOSC .EQU 18432000 ; CPU OSC FREQ IN MHZ |
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INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) |
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DEFSERCFG .EQU SER_115200_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) |
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; |
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RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) |
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ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) |
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APP_BNKS .EQU $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING) |
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MEMMGR .EQU MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON] |
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RAMBIAS .EQU ROMSIZE ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE |
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MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY) |
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MPGSEL_1 .EQU $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY) |
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MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY) |
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MPGSEL_3 .EQU $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY) |
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MPGENA .EQU $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY) |
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; |
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Z180_BASE .EQU $C0 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS |
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Z180_CLKDIV .EQU 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2 |
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Z180_MEMWAIT .EQU 0 ; Z180: MEMORY WAIT STATES (0-3) |
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Z180_IOWAIT .EQU 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) |
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Z180_TIMER .EQU TRUE ; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER |
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; |
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RTCIO .EQU $84 ; RTC LATCH REGISTER ADR |
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; |
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KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT |
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KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS |
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; |
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CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT |
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CTCDEBUG .EQU FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT |
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CTCBASE .EQU $88 ; CTC BASE I/O ADDRESS |
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CTCTIMER .EQU FALSE ; ENABLE CTC PERIODIC TIMER |
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; |
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PCFENABLE .EQU FALSE ; ENABLE PCF8584 I2C CONTROLLER |
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PCFBASE .EQU $F0 ; PCF8584 BASE I/O ADDRESS |
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; |
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EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION |
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; |
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SKZENABLE .EQU FALSE ; ENABLE SERGEY'S Z80-512K FEATURES |
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; |
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WDOGMODE .EQU WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ] |
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; |
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FPLED_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL LEDS |
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FPLED_IO .EQU $00 ; FP: PORT ADDRESS FOR FP LEDS |
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FPLED_INV .EQU FALSE ; FP: LED BITS ARE INVERTED |
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FPLED_DSKACT .EQU FALSE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS |
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FPSW_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL SWITCHES |
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FPSW_IO .EQU $00 ; FP: PORT ADDRESS FOR FP SWITCHES |
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FPSW_INV .EQU FALSE ; FP: SWITCH BITS ARE INVERTED |
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; |
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DIAGLVL .EQU DL_CRITICAL ; ERROR LEVEL REPORTING |
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; |
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LEDENABLE .EQU FALSE ; ENABLES STATUS LED (SINGLE LED) |
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LEDMODE .EQU LEDMODE_STD ; LEDMODE_[STD|SC|RTC|NABU] |
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LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS |
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LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED |
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; |
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DSKYENABLE .EQU FALSE ; ENABLES DSKY FUNCTIONALITY |
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DSKYDSKACT .EQU FALSE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY |
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ICMENABLE .EQU FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218) |
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ICMPPIBASE .EQU $60 ; BASE I/O ADDRESS OF ICM PPI |
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PKDENABLE .EQU FALSE ; ENABLES DSKY NG PKD DRIVER (8259) |
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PKDPPIBASE .EQU $60 ; BASE I/O ADDRESS OF PKD PPI |
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PKDOSC .EQU 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ) |
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H8PENABLE .EQU FALSE ; ENABLES HEATH H8 FRONT PANEL |
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LCDENABLE .EQU FALSE ; ENABLE LCD DISPLAY |
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LCDBASE .EQU $DA ; BASE I/O ADDRESS OF LCD CONTROLLER |
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LCDDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY |
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; |
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BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE |
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SECCON .EQU $FF ; SECONDARY CONSOLE DEVICE |
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CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP |
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VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI] |
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VDAEMU_SERKBD .EQU $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD |
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ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
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PPKTRACE .EQU 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
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KBDTRACE .EQU 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
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PPKKBLOUT .EQU KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE] |
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KBDKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] |
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MKYKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] |
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; |
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DSRTCENABLE .EQU TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) |
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DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W] |
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DSRTCCHG .EQU TRUE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) |
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; |
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DS1501RTCENABLE .EQU FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM) |
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DS1501RTC_BASE .EQU $50 ; DS1501RTC: I/O BASE ADDRESS |
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; |
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BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM) |
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BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS |
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; |
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INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) |
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; |
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RP5RTCENABLE .EQU FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM) |
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; |
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HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT |
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SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) |
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; |
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DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM) |
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DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF] |
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; |
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DS5RTCENABLE .EQU FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM) |
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; |
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SSERENABLE .EQU FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM) |
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SSERCFG .EQU SER_9600_8N1 ; SSER: SERIAL LINE CONFIG |
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SSERSTATUS .EQU $FF ; SSER: STATUS PORT |
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SSERDATA .EQU $FF ; SSER: DATA PORT |
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SSERIRDY .EQU %00000001 ; SSER: INPUT READY BIT MASK |
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SSERIINV .EQU FALSE ; SSER: INPUT READY BIT INVERTED |
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SSERORDY .EQU %00000010 ; SSER: OUTPUT READY BIT MASK |
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SSEROINV .EQU FALSE ; SSER: OUTPUT READY BIT INVERTED |
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; |
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DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) |
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DUARTCNT .EQU 1 ; DUART: NUMBER OF CHIPS TO DETECT (1-2) |
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DUART0BASE .EQU $A0 ; DUART 0: BASE ADDRESS OF CHIP |
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DUART0ACFG .EQU DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG |
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DUART0BCFG .EQU DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG |
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DUART1BASE .EQU $40 ; DUART 1: BASE ADDRESS OF CHIP |
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DUART1ACFG .EQU DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG |
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DUART1BCFG .EQU DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG |
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; |
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UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) |
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UARTCNT .EQU 1 ; UART: NUMBER OF CHIPS TO DETECT (1-8) |
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UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ |
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UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 |
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UART4UART .EQU FALSE ; UART: SUPPORT 4UART ECB BOARD |
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UART4UARTBASE .EQU $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD |
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UART0BASE .EQU $80 ; UART 0: REGISTERS BASE ADR |
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UART0CFG .EQU DEFSERCFG ; UART 0: SERIAL LINE CONFIG |
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UART1BASE .EQU $88 ; UART 1: REGISTERS BASE ADR |
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UART1CFG .EQU DEFSERCFG ; UART 1: SERIAL LINE CONFIG |
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UART2BASE .EQU $A0 ; UART 2: REGISTERS BASE ADR |
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UART2CFG .EQU DEFSERCFG ; UART 2: SERIAL LINE CONFIG |
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UART3BASE .EQU $A8 ; UART 3: REGISTERS BASE ADR |
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UART3CFG .EQU DEFSERCFG ; UART 3: SERIAL LINE CONFIG |
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UART4BASE .EQU $FF ; UART 4: REGISTERS BASE ADR |
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UART4CFG .EQU DEFSERCFG ; UART 4: SERIAL LINE CONFIG |
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UART5BASE .EQU $FF ; UART 5: REGISTERS BASE ADR |
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UART5CFG .EQU DEFSERCFG ; UART 5: SERIAL LINE CONFIG |
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UART6BASE .EQU $FF ; UART 6: REGISTERS BASE ADR |
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UART6CFG .EQU DEFSERCFG ; UART 6: SERIAL LINE CONFIG |
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UART7BASE .EQU $FF ; UART 7: REGISTERS BASE ADR |
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UART7CFG .EQU DEFSERCFG ; UART 7: SERIAL LINE CONFIG |
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; |
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ASCIENABLE .EQU TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) |
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ASCIINTS .EQU TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 |
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ASCISWAP .EQU FALSE ; ASCI: SWAP CHANNELS |
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ASCIBOOT .EQU 0 ; ASCI: REBOOT ON RCV CHAR (0=DISABLED) |
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ASCI0CFG .EQU DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG |
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ASCI1CFG .EQU DEFSERCFG ; ASCI 1: SERIAL LINE CONFIG |
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; |
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Z2UENABLE .EQU FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) |
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; |
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ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) |
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; |
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SIOENABLE .EQU TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) |
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SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT |
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SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) |
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SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP |
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SIOINTS .EQU TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3 |
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SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] |
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SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR |
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SIO0ACLK .EQU 7372800 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 |
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SIO0ACFG .EQU SER_115200_8N1 ; SIO 0A: SERIAL LINE CONFIG |
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SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE |
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SIO0BCLK .EQU 7372800 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 |
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SIO0BCFG .EQU SER_115200_8N1 ; SIO 0B: SERIAL LINE CONFIG |
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SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE |
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SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] |
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SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR |
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SIO1ACLK .EQU 7372800 ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 |
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SIO1ACFG .EQU SER_115200_8N1 ; SIO 1A: SERIAL LINE CONFIG |
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SIO1ACTCC .EQU -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE |
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SIO1BCLK .EQU 7372800 ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 |
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SIO1BCFG .EQU SER_115200_8N1 ; SIO 1B: SERIAL LINE CONFIG |
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SIO1BCTCC .EQU -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE |
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; |
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XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG |
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; |
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VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) |
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CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM) |
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GDCENABLE .EQU FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM) |
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TMSENABLE .EQU FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) |
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TMSMODE .EQU TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU] |
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TMS80COLS .EQU FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958 |
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TMSTIMENABLE .EQU FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) |
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VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) |
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VRCENABLE .EQU FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) |
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SCONENABLE .EQU FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) |
|||
EFENABLE .EQU FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) |
|||
; |
|||
MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) |
|||
MDROM .EQU TRUE ; MD: ENABLE ROM DISK |
|||
MDRAM .EQU TRUE ; MD: ENABLE RAM DISK |
|||
MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
|||
MDFFENABLE .EQU FALSE ; MD: ENABLE FLASH FILE SYSTEM |
|||
; |
|||
FDENABLE .EQU FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) |
|||
FDMODE .EQU FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] |
|||
FDCNT .EQU 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2) |
|||
FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL) |
|||
FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS |
|||
FD0TYPE .EQU FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] |
|||
FD1TYPE .EQU FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] |
|||
; |
|||
RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER |
|||
; |
|||
IDEENABLE .EQU TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) |
|||
IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
|||
IDECNT .EQU 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH |
|||
IDE0MODE .EQU IDEMODE_GIDE ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] |
|||
IDE0BASE .EQU $20 ; IDE 0: IO BASE ADDRESS |
|||
IDE0DATLO .EQU $20 ; IDE 0: DATA LO PORT FOR 16-BIT I/O |
|||
IDE0DATHI .EQU $28 ; IDE 0: DATA HI PORT FOR 16-BIT I/O |
|||
IDE0A8BIT .EQU TRUE ; IDE 0A (MASTER): 8 BIT XFER |
|||
IDE0B8BIT .EQU TRUE ; IDE 0B (MASTER): 8 BIT XFER |
|||
IDE1MODE .EQU IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] |
|||
IDE1BASE .EQU $00 ; IDE 1: IO BASE ADDRESS |
|||
IDE1DATLO .EQU $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O |
|||
IDE1DATHI .EQU $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O |
|||
IDE1A8BIT .EQU TRUE ; IDE 1A (MASTER): 8 BIT XFER |
|||
IDE1B8BIT .EQU TRUE ; IDE 1B (MASTER): 8 BIT XFER |
|||
IDE2MODE .EQU IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] |
|||
IDE2BASE .EQU $00 ; IDE 2: IO BASE ADDRESS |
|||
IDE2DATLO .EQU $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O |
|||
IDE2DATHI .EQU $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O |
|||
IDE2A8BIT .EQU TRUE ; IDE 2A (MASTER): 8 BIT XFER |
|||
IDE2B8BIT .EQU TRUE ; IDE 2B (MASTER): 8 BIT XFER |
|||
; |
|||
PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) |
|||
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
|||
PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP |
|||
PPIDE0BASE .EQU $20 ; PPIDE 0: PPI REGISTERS BASE ADR |
|||
PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER |
|||
PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER |
|||
PPIDE1BASE .EQU $00 ; PPIDE 1: PPI REGISTERS BASE ADR |
|||
PPIDE1A8BIT .EQU FALSE ; PPIDE 1A (MASTER): 8 BIT XFER |
|||
PPIDE1B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER |
|||
PPIDE2BASE .EQU $00 ; PPIDE 2: PPI REGISTERS BASE ADR |
|||
PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER |
|||
PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER |
|||
; |
|||
SDENABLE .EQU TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) |
|||
SDMODE .EQU SDMODE_GM ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM] |
|||
SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE |
|||
SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY |
|||
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
|||
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE |
|||
SDMTSWAP .EQU FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011 |
|||
; |
|||
CHENABLE .EQU FALSE ; CH: ENABLE CH375/376 USB SUPPORT |
|||
CHTRACE .EQU 1 ; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
|||
CHUSBTRACE .EQU 1 ; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
|||
CHSDTRACE .EQU 1 ; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
|||
CHCNT .EQU 2 ; CH: NUMBER OF BOARDS TO DETECT (1-2) |
|||
CH0BASE .EQU $3E ; CH 0: BASE I/O ADDRESS |
|||
CH0USBENABLE .EQU TRUE ; CH 0: ENABLE USB DISK |
|||
CH0SDENABLE .EQU FALSE ; CH 0: ENABLE SD DISK |
|||
CH1BASE .EQU $3C ; CH 1: BASE I/O ADDRESS |
|||
CH1USBENABLE .EQU TRUE ; CH 1: ENABLE USB DISK |
|||
CH1SDENABLE .EQU FALSE ; CH 1: ENABLE SD DISK |
|||
; |
|||
PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) |
|||
PRPSDENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT |
|||
PRPSDTRACE .EQU 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
|||
PRPCONENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT |
|||
; |
|||
PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) |
|||
; |
|||
ESPENABLE .EQU FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM) |
|||
; |
|||
HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) |
|||
; |
|||
PIOENABLE .EQU FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM) |
|||
PIOCNT .EQU 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP |
|||
PIO0BASE .EQU $B8 ; PIO 0: REGISTERS BASE ADR |
|||
PIO1BASE .EQU $BC ; PIO 1: REGISTERS BASE ADR |
|||
; |
|||
LPTENABLE .EQU FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) |
|||
LPTMODE .EQU LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014] |
|||
LPTCNT .EQU 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2) |
|||
LPTTRACE .EQU 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
|||
LPT0BASE .EQU $18 ; LPT 0: REGISTERS BASE ADR |
|||
LPT1BASE .EQU $00 ; LPT 1: REGISTERS BASE ADR |
|||
; |
|||
PPAENABLE .EQU FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM) |
|||
PPACNT .EQU 1 ; PPA: NUMBER OF PPA DEVICES (1-2) |
|||
PPATRACE .EQU 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
|||
PPAMODE .EQU PPAMODE_MG014 ; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014] |
|||
PPA0BASE .EQU LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA |
|||
PPA1BASE .EQU LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA |
|||
; |
|||
IMMENABLE .EQU FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM) |
|||
IMMCNT .EQU 1 ; IMM: NUMBER OF IMM DEVICES (1-2) |
|||
IMMTRACE .EQU 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
|||
IMMMODE .EQU IMMMODE_MG014 ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014] |
|||
IMM0BASE .EQU LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM |
|||
IMM1BASE .EQU LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM |
|||
; |
|||
SYQENABLE .EQU FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM) |
|||
SYQCNT .EQU 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2) |
|||
SYQTRACE .EQU 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
|||
SYQMODE .EQU IMMMODE_MG014 ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014] |
|||
SYQ0BASE .EQU LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ |
|||
SYQ1BASE .EQU LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ |
|||
; |
|||
PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD |
|||
PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) |
|||
PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP |
|||
; |
|||
UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) |
|||
; |
|||
SN76489ENABLE .EQU FALSE ; SN: ENABLE SN76489 SOUND DRIVER |
|||
AUDIOTRACE .EQU FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER |
|||
SN7CLK .EQU 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD |
|||
SNMODE .EQU SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM] |
|||
; |
|||
AY38910ENABLE .EQU FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER |
|||
AY_CLK .EQU 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD |
|||
AYMODE .EQU AYMODE_RCZ180 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] |
|||
; |
|||
SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) |
|||
; |
|||
DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM) |
|||
DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS |
|||
DMAMODE .EQU DMAMODE_Z180 ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO) |
|||
; |
|||
YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER |
|||
VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC) |
|||
@ -0,0 +1,449 @@ |
|||
; |
|||
;================================================================================================== |
|||
; HDSK DISK DRIVER |
|||
;================================================================================================== |
|||
; |
|||
; IO PORT ADDRESSES |
|||
; |
|||
HDSK_IO .EQU $FD |
|||
; |
|||
HDSK_CMDNONE .EQU 0 |
|||
HDSK_CMDRESET .EQU 1 |
|||
HDSK_CMDREAD .EQU 2 |
|||
HDSK_CMDWRITE .EQU 3 |
|||
HDSK_CMDPARAM .EQU 4 |
|||
; |
|||
; HDSK DEVICE CONFIGURATION |
|||
; |
|||
HDSK_DEVCNT .EQU 2 ; NUMBER OF HDSK DEVICES SUPPORTED |
|||
HDSK_CFGSIZ .EQU 6 ; SIZE OF CFG TBL ENTRIES |
|||
; |
|||
HDSK_DEV .EQU 0 ; OFFSET OF DEVICE NUMBER (BYTE) |
|||
HDSK_STAT .EQU 1 ; OFFSET OF STATUS (BYTE) |
|||
HDSK_LBA .EQU 2 ; OFFSET OF LBA (DWORD) |
|||
; |
|||
DEVECHO "HDSK: IO=" |
|||
DEVECHO HDSK_IO |
|||
DEVECHO ", DEVICE COUNT=" |
|||
DEVECHO HDSK_DEVCNT |
|||
DEVECHO "\n" |
|||
; |
|||
HDSK_CFGTBL: |
|||
; DEVICE 0 |
|||
.DB 0 ; DRIVER DEVICE NUMBER |
|||
.DB 0 ; DEVICE STATUS |
|||
.DW 0,0 ; CURRENT LBA |
|||
#IF (HDSK_DEVCNT >= 2) |
|||
; DEVICE 1 |
|||
.DB 1 ; DEVICE NUMBER |
|||
.DB 0 ; DEVICE STATUS |
|||
.DW 0,0 ; CURRENT LBA |
|||
#ENDIF |
|||
; |
|||
#IF ($ - HDSK_CFGTBL) != (HDSK_DEVCNT * HDSK_CFGSIZ) |
|||
.ECHO "*** INVALID HDSK CONFIG TABLE ***\n" |
|||
#ENDIF |
|||
; |
|||
.DB $FF ; END MARKER |
|||
; |
|||
; STATUS |
|||
; |
|||
HDSK_STOK .EQU 0 ; OK |
|||
HDSK_STNOTRDY .EQU -1 ; NOT READY |
|||
; |
|||
; |
|||
; |
|||
HDSK_INIT: |
|||
CALL NEWLINE ; FORMATTING |
|||
PRTS("HDSK:$") |
|||
PRTS(" DEVICES=$") |
|||
LD A,HDSK_DEVCNT |
|||
CALL PRTDECB |
|||
; |
|||
; SETUP THE DISPATCH TABLE ENTRIES |
|||
; |
|||
XOR A ; ZERO ACCUM |
|||
LD (HDSK_CURDEV),A ; INIT CURRENT DEVICE NUM |
|||
LD IY,HDSK_CFGTBL ; START OF DEV CFG TABLE |
|||
HDSK_INIT0: |
|||
CALL HDSK_PROBE ; HARDWARE PROBE |
|||
JR NZ,HDSK_INIT1 ; SKIP DEVICE IF NOT PRESENT |
|||
LD BC,HDSK_FNTBL ; BC := DRIVER FUNC TABLE ADDRESS |
|||
PUSH IY ; CFG ENTRY POINTER |
|||
POP DE ; ... TO DE |
|||
CALL DIO_ADDENT ; ADD ENTRY TO GLOBAL DISK TABLE |
|||
CALL HDSK_INITDEV ; PERFORM DEVICE INITIALIZATION |
|||
HDSK_INIT1: |
|||
LD BC,HDSK_CFGSIZ ; SIZE OF CFG ENTRY |
|||
ADD IY,BC ; BUMP IY TO NEXT ENTRY |
|||
LD HL,HDSK_CURDEV ; POINT TO CURRENT DEVICE |
|||
INC (HL) ; AND INCREMENT IT |
|||
LD A,(IY) ; GET FIRST BYTE OF ENTRY |
|||
INC A ; TEST FOR END OF TABLE ($FF) |
|||
JR NZ,HDSK_INIT0 ; IF NOT, LOOP |
|||
; |
|||
XOR A ; INIT SUCCEEDED |
|||
RET ; RETURN |
|||
; |
|||
; PROBE FOR DEVICE EXISTENCE |
|||
; |
|||
HDSK_PROBE: |
|||
XOR A ; SIGNAL SUCCESS |
|||
RET ; AND DONE |
|||
; |
|||
; INITIALIZE DEVICE |
|||
; |
|||
HDSK_INITDEV: |
|||
LD (IY+HDSK_STAT),HDSK_STNOTRDY ; STATUS := NOT READY |
|||
XOR A ; CLEAR ACCUM |
|||
LD (IY+HDSK_LBA+0),A ; ZERO LBA |
|||
LD (IY+HDSK_LBA+1),A ; ... |
|||
LD (IY+HDSK_LBA+2),A ; ... |
|||
LD (IY+HDSK_LBA+3),A ; ... |
|||
XOR A ; SIGNAL SUCCESS (REDUNDANT) |
|||
RET ; AND DONE |
|||
; |
|||
; DRIVER FUNCTION TABLE |
|||
; |
|||
HDSK_FNTBL: |
|||
.DW HDSK_STATUS |
|||
.DW HDSK_RESET |
|||
.DW HDSK_SEEK |
|||
.DW HDSK_READ |
|||
.DW HDSK_WRITE |
|||
.DW HDSK_VERIFY |
|||
.DW HDSK_FORMAT |
|||
.DW HDSK_DEVICE |
|||
.DW HDSK_MEDIA |
|||
.DW HDSK_DEFMED |
|||
.DW HDSK_CAP |
|||
.DW HDSK_GEOM |
|||
#IF (($ - HDSK_FNTBL) != (DIO_FNCNT * 2)) |
|||
.ECHO "*** INVALID HDSK FUNCTION TABLE ***\n" |
|||
#ENDIF |
|||
; |
|||
; |
|||
; |
|||
HDSK_VERIFY: |
|||
HDSK_FORMAT: |
|||
HDSK_DEFMED: |
|||
SYSCHKERR(ERR_NOTIMPL) ; INVALID SUB-FUNCTION |
|||
RET |
|||
; |
|||
; |
|||
; |
|||
HDSK_STATUS: |
|||
LD A,(IY+HDSK_STAT) ; LOAD STATUS |
|||
OR A ; SET FLAGS |
|||
RET |
|||
; |
|||
; |
|||
; |
|||
HDSK_RESET: |
|||
JP HDSK_DSKRESET |
|||
; |
|||
; GET DISK CAPACITY |
|||
; RETURN DE:HL=BLOCK COUNT, BC=BLOCK SIZE |
|||
; ASSUME 1GB MEDIA SIZE, SO 1GB / 512B |
|||
; IS $200000 SECTORS |
|||
; |
|||
HDSK_CAP: |
|||
LD DE,$20 ; BLOCK COUNT MSW |
|||
LD HL,0 ; BLOCK COUNT LSW |
|||
LD BC,512 ; 512 BYTE SECTOR |
|||
XOR A ; SIGNAL SUCCESS |
|||
RET |
|||
; |
|||
; |
|||
; |
|||
HDSK_GEOM: |
|||
; FOR LBA, WE SIMULATE CHS ACCESS USING 16 HEADS AND 16 SECTORS |
|||
; RETURN HS:CC -> DE:HL, SET HIGH BIT OF D TO INDICATE LBA CAPABLE |
|||
CALL HDSK_CAP ; GET TOTAL BLOCKS IN DE:HL, BLOCK SIZE TO BC |
|||
LD L,H ; DIVIDE BY 256 FOR # TRACKS |
|||
LD H,E ; ... HIGH BYTE DISCARDED, RESULT IN HL |
|||
LD D,$80 | 16 ; HEADS / CYL = 16, SET LBA BIT |
|||
LD E,16 ; SECTORS / TRACK = 16 |
|||
XOR A ; SIGNAL SUCCESS |
|||
RET |
|||
; |
|||
; |
|||
; |
|||
HDSK_DEVICE: |
|||
LD D,DIODEV_HDSK ; D := DEVICE TYPE |
|||
LD E,(IY+HDSK_DEV) ; E := PHYSICAL DEVICE NUMBER |
|||
LD C,%00110000 ; C := ATTRIBUTES, NON-REMOVABLE HARD DISK |
|||
LD H,0 ; H := 0, DRIVER HAS NO MODES |
|||
LD L,HDSK_IO ; L := BASE I/O ADDRESS |
|||
XOR A ; SIGNAL SUCCESS |
|||
RET |
|||
; |
|||
; |
|||
; |
|||
HDSK_MEDIA: |
|||
LD E,MID_HD ; HARD DISK MEDIA |
|||
LD D,0 ; D:0=0 MEANS NO MEDIA CHANGE |
|||
XOR A ; SIGNAL SUCCESS |
|||
RET |
|||
; |
|||
; |
|||
; |
|||
HDSK_SEEK: |
|||
BIT 7,D ; CHECK FOR LBA FLAG |
|||
CALL Z,HB_CHS2LBA ; CLEAR MEANS CHS, CONVERT TO LBA |
|||
RES 7,D ; CLEAR FLAG REGARDLESS (DOES NO HARM IF ALREADY LBA) |
|||
LD (IY+HDSK_LBA+0),L ; SAVE NEW LBA |
|||
LD (IY+HDSK_LBA+1),H ; ... |
|||
LD (IY+HDSK_LBA+2),E ; ... |
|||
LD (IY+HDSK_LBA+3),D ; ... |
|||
XOR A ; SIGNAL SUCCESS |
|||
RET ; AND RETURN |
|||
; |
|||
; |
|||
; |
|||
HDSK_READ: |
|||
CALL HB_DSKREAD ; HOOK HBIOS DISK READ SUPERVISOR |
|||
LD A,HDSK_CMDREAD |
|||
JR HDSK_RW |
|||
; |
|||
; |
|||
; |
|||
HDSK_WRITE: |
|||
CALL HB_DSKWRITE ; HOOK HBIOS DISK WRITE SUPERVISOR |
|||
LD A,HDSK_CMDWRITE |
|||
JR HDSK_RW |
|||
; |
|||
; |
|||
; |
|||
HDSK_RW: |
|||
LD (HDSK_CMD),A ; SET COMMAND BYTE |
|||
LD (HDSK_DMA),HL ; SAVE INITIAL DMA |
|||
LD A,E ; SECTOR COUNT TO A |
|||
OR A ; SET FLAGS |
|||
RET Z ; ZERO SECTOR I/O, RETURN W/ E=0 & A=0 |
|||
LD B,A ; INIT SECTOR DOWNCOUNTER |
|||
LD C,0 ; INIT SECTOR READ/WRITE COUNT |
|||
LD A,(IY+HDSK_DEV) ; GET DEVICE NUMBER |
|||
LD (HDSK_DRV),A ; ... AND SET FIELD IN HDSK PARM BLOCK |
|||
|
|||
; RESET HDSK INTERFACE IF NEEDED |
|||
LD A,(IY+HDSK_STAT) ; GET CURRENT STATUS |
|||
OR A ; SET FLAGS |
|||
PUSH BC ; SAVE COUNTERS |
|||
CALL NZ,HDSK_DSKRESET ; RESET IF NOT READY |
|||
POP BC ; RESTORE COUNTERS |
|||
JR NZ,HDSK_RW6 ; ABORT ON FAILURE |
|||
|
|||
HDSK_RW0: |
|||
PUSH BC ; SAVE COUNTERS |
|||
XOR A ; A = 0 |
|||
LD (HDSK_RC),A ; CLEAR RETURN CODE |
|||
; |
|||
#IF (DSKYENABLE) |
|||
#IF (DSKYDSKACT) |
|||
LD A,HDSK_LBA |
|||
CALL LDHLIYA |
|||
CALL HB_DSKACT ; SHOW ACTIVITY |
|||
#ENDIF |
|||
#ENDIF |
|||
; |
|||
; CONVERT LBA HHHH:LLLL (4 BYTES) |
|||
; TO HDSK TRACK/SECTOR TTTT:SS (3 BYTES) |
|||
; SAVING TO HDSK PARM BLOCK |
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; (IY+HDSK_LBA+0) ==> (HDSK_SEC) |
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LD A,(IY+HDSK_LBA+0) |
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LD (HDSK_SEC),A |
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; (IY+HDSK_LBA+1) ==> (HDSK_TRK+0) |
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LD A,(IY+HDSK_LBA+1) |
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LD (HDSK_TRK+0),A |
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; (IY+HDSK_LBA+2) ==> (HDSK_TRK+1) |
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LD A,(IY+HDSK_LBA+2) |
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LD (HDSK_TRK+1),A |
|||
|
|||
; EXECUTE COMMAND |
|||
LD B,7 ; SIZE OF PARAMETER BLOCK |
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LD HL,HDSK_PARMBLK ; ADDRESS OF PARAMETER BLOCK |
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LD C,$FD ; HDSK CMD PORT |
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OTIR ; SEND IT |
|||
|
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; GET RESULT |
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IN A,(C) ; GET RESULT CODE |
|||
LD (HDSK_RC),A ; SAVE IT |
|||
OR A ; SET FLAGS |
|||
|
|||
#IF (HDSKTRACE > 0) |
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PUSH AF ; SAVE RETURN CODE |
|||
#IF (HDSKTRACE == 1) |
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CALL NZ,HDSK_PRT ; DIAGNOSE ERRORS ONLY |
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#ENDIF |
|||
#IF (HDSKTRACE >= 2) |
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CALL HDSK_PRT ; DISPLAY ALL READ/WRITE RESULTS |
|||
#ENDIF |
|||
POP AF ; RESTORE RETURN CODE |
|||
#ENDIF |
|||
|
|||
JR NZ,HDSK_RW5 ; BAIL OUT ON ERROR |
|||
|
|||
; INCREMENT LBA |
|||
LD A,HDSK_LBA ; LBA OFFSET IN CFG ENTRY |
|||
CALL LDHLIYA ; HL := IY + A, REG A TRASHED |
|||
CALL INC32HL ; INCREMENT THE VALUE |
|||
|
|||
; INCREMENT DMA |
|||
LD HL,HDSK_DMA+1 ; POINT TO MSB OF DMA |
|||
INC (HL) ; BUMP DMA BY |
|||
INC (HL) ; ... 512 BYTES |
|||
|
|||
XOR A ; A := 0 SIGNALS SUCCESS |
|||
|
|||
HDSK_RW5: |
|||
POP BC ; RECOVER COUNTERS |
|||
JR NZ,HDSK_RW6 ; IF ERROR, GET OUT |
|||
|
|||
INC C ; RECORD SECTOR COMPLETED |
|||
DJNZ HDSK_RW0 ; LOOP AS NEEDED |
|||
|
|||
HDSK_RW6: |
|||
; RETURN WITH SECTORS READ IN E AND UPDATED DMA ADDRESS IN HL |
|||
LD E,C ; SECTOR READ COUNT TO E |
|||
LD HL,(HDSK_DMA) ; CURRENT DMA TO HL |
|||
OR A ; SET FLAGS BASED ON RETURN CODE |
|||
RET Z ; RETURN IF SUCCESS |
|||
LD A,ERR_IO ; SIGNAL IO ERROR |
|||
OR A ; SET FLAGS |
|||
RET ; AND DONE |
|||
; |
|||
; |
|||
; |
|||
HDSK_DSKRESET: |
|||
; |
|||
#IF (HDSKTRACE >= 2) |
|||
CALL NEWLINE |
|||
LD DE,HDSKSTR_PREFIX |
|||
CALL WRITESTR |
|||
CALL PC_SPACE |
|||
LD DE,HDSKSTR_RESET |
|||
CALL WRITESTR |
|||
#ENDIF |
|||
; |
|||
LD B,32 |
|||
LD A,HDSK_CMDRESET |
|||
HDSK_DSKRESET1: |
|||
OUT ($FD),A |
|||
DJNZ HDSK_DSKRESET1 |
|||
|
|||
XOR A ; STATUS = OK |
|||
LD (IY+HDSK_STAT),A ; SAVE IT |
|||
|
|||
RET |
|||
; |
|||
; |
|||
; |
|||
HDSK_PRT: |
|||
CALL NEWLINE |
|||
|
|||
LD DE,HDSKSTR_PREFIX |
|||
CALL WRITESTR |
|||
|
|||
CALL PC_SPACE |
|||
LD DE,HDSKSTR_CMD |
|||
CALL WRITESTR |
|||
LD A,(HDSK_CMD) |
|||
CALL PRTHEXBYTE |
|||
|
|||
CALL PC_SPACE |
|||
CALL PC_LBKT |
|||
LD A,(HDSK_CMD) |
|||
LD DE,HDSKSTR_NONE |
|||
CP HDSK_CMDNONE |
|||
JP Z,HDSK_PRTCMD |
|||
LD DE,HDSKSTR_RESET |
|||
CP HDSK_CMDRESET |
|||
JP Z,HDSK_PRTCMD |
|||
LD DE,HDSKSTR_READ |
|||
CP HDSK_CMDREAD |
|||
JP Z,HDSK_PRTCMD |
|||
LD DE,HDSKSTR_WRITE |
|||
CP HDSK_CMDWRITE |
|||
JP Z,HDSK_PRTCMD |
|||
LD DE,HDSKSTR_PARAM |
|||
CP HDSK_CMDPARAM |
|||
JP Z,HDSK_PRTCMD |
|||
LD DE,HDSKSTR_UNKCMD |
|||
HDSK_PRTCMD: |
|||
CALL WRITESTR |
|||
CALL PC_RBKT |
|||
|
|||
LD A,(HDSK_CMD) |
|||
CP HDSK_CMDREAD |
|||
JR Z,HDSK_PRTRW |
|||
CP HDSK_CMDWRITE |
|||
JR Z,HDSK_PRTRW |
|||
RET |
|||
|
|||
HDSK_PRTRW: |
|||
CALL PC_SPACE |
|||
LD A,(HDSK_DRV) |
|||
CALL PRTHEXBYTE |
|||
CALL PC_SPACE |
|||
LD BC,(HDSK_TRK) |
|||
CALL PRTHEXWORD |
|||
CALL PC_SPACE |
|||
LD A,(HDSK_SEC) |
|||
CALL PRTHEXBYTE |
|||
CALL PC_SPACE |
|||
LD BC,(HDSK_DMA) |
|||
CALL PRTHEXWORD |
|||
|
|||
CALL PC_SPACE |
|||
LD DE,HDSKSTR_ARROW |
|||
CALL WRITESTR |
|||
|
|||
CALL PC_SPACE |
|||
LD DE,HDSKSTR_RC |
|||
CALL WRITESTR |
|||
LD A,(HDSK_RC) |
|||
CALL PRTHEXBYTE |
|||
|
|||
CALL PC_SPACE |
|||
CALL PC_LBKT |
|||
LD A,(HDSK_RC) |
|||
LD DE,HDSKSTR_STOK |
|||
CP HDSK_STOK |
|||
JP Z,HDSK_PRTRC |
|||
LD DE,HDSKSTR_STUNK |
|||
|
|||
HDSK_PRTRC: |
|||
CALL WRITESTR |
|||
CALL PC_RBKT |
|||
|
|||
RET |
|||
; |
|||
; |
|||
; |
|||
HDSKSTR_PREFIX .TEXT "HDSK:$" |
|||
HDSKSTR_CMD .TEXT "CMD=$" |
|||
HDSKSTR_RC .TEXT "RC=$" |
|||
HDSKSTR_ARROW .TEXT "-->$" |
|||
HDSKSTR_NONE .TEXT "NONE$" |
|||
HDSKSTR_RESET .TEXT "RESET$" |
|||
HDSKSTR_READ .TEXT "READ$" |
|||
HDSKSTR_WRITE .TEXT "WRITE$" |
|||
HDSKSTR_PARAM .TEXT "PARAM$" |
|||
HDSKSTR_UNKCMD .TEXT "UNKCMD$" |
|||
HDSKSTR_STOK .TEXT "OK$" |
|||
HDSKSTR_STUNK .TEXT "UNKNOWN ERROR$" |
|||
; |
|||
;================================================================================================== |
|||
; HDSK DISK DRIVER - DATA |
|||
;================================================================================================== |
|||
; |
|||
HDSK_RC .DB 0 ; CURRENT RETURN CODE |
|||
HDSK_CURDEV .DB 0 ; CURRENT DEVICE NUMBER |
|||
; |
|||
HDSK_PARMBLK: |
|||
HDSK_CMD .DB 0 ; COMMAND (HDSK_READ, HDSK_WRITE, ...) |
|||
HDSK_DRV .DB 0 ; 0..7, HDSK DRIVE NUMBER |
|||
HDSK_SEC .DB 0 ; 0..255 SECTOR |
|||
HDSK_TRK .DW 0 ; 0..2047 TRACK |
|||
HDSK_DMA .DW 0 ; ADDRESS FOR SECTOR DATA EXCHANGE |
|||
Loading…
Reference in new issue