mirror of
https://github.com/wwarthen/RomWBW.git
synced 2026-02-06 14:11:48 -06:00
Minor Cosmetic Cleanup
Primarily fixed the Z280 config files to display the correct CPU speed in boot messages.
This commit is contained in:
@@ -2412,6 +2412,13 @@ MD_INIT:
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; UDPATE THE RAM/ROM DPB STRUCTURES BASED ON HARDWARE
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;
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#IFDEF PLTWBW
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; TODO: HANDLE DISABLED RAM/ROM DISK BETTER.
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; IF RAM OR ROM DISK ARE DISABLED, BELOW WILL STILL
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; TRY TO ADJUST THE DPB BASED ON RAM BANK CALCULATIONS.
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; IT SHOULD NOT MATTER BECAUSE THE DPB SHOULD NEVER BE
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; USED. IT WOULD BE BETTER TO GET RAMD0/ROMD0 AND
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; RAMDN/ROMDN FROM THE HCB AND USE THOSE TO CALC THE
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; DPB ADJUSTMENT. IF DN-D0=0, BYPASS ADJUSTMENT.
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LD A,(HCB + HCB_ROMBANKS) ; ROM BANK COUNT
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SUB 4 ; REDUCE BANK COUNT BY RESERVED PAGES
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LD IX,DPB_ROM ; ADDRESS OF DPB
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@@ -355,6 +355,13 @@ dpb$hdnew: ; 8MB Hard Disk Drive (new format)
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; called for first time initialization.
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dsk$init:
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; TODO: Handle disabled RAM/ROM disk better.
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; If RAM or ROM disk are disabled, below will still
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; try to adjust the DPB based on RAM bank calculations.
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; It should not matter because the DPB should never be
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; used. It would be better to get RAMD0/ROMD0 and
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; RAMDN/ROMDN from the HCB and use those to calc the
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; DPB adjustment. If DN-D0=0, bypass adjustment.
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ld b,0FAh ; HBIOS Peek Function
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ld a,(@hbbio) ; HBIOS bank id
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ld d,a ; ... goes in D
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@@ -28,7 +28,7 @@
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;
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CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
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;
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CPUOSC .SET 24000000 ; CPU OSC FREQ IN MHZ
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CPUOSC .SET 12000000 ; CPU OSC FREQ IN MHZ
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;
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MEMMGR .SET MM_Z280 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
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;
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@@ -28,7 +28,7 @@
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;
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#include "Config/RCZ280_nat.asm"
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;
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CPUOSC .SET 29491200 ; CPU OSC FREQ IN MHZ
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CPUOSC .SET 14745600 ; CPU OSC FREQ IN MHZ
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;
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RAMSIZE .SET 256 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
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ROMSIZE_CHK .SET 256 ; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
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@@ -39,4 +39,6 @@ RAMBIAS .SET (1 << (RAMLOC - 10)) ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS
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MDROM .SET TRUE ; MD: ENABLE ROM DISK
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MDRAM .SET FALSE ; MD: ENABLE RAM DISK
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;
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Z2U0HFC .SET TRUE ; Z2U 0: ENABLE HARDWARE FLOW CONTROL
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;
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Z2UOSC .SET (CPUOSC / 8) ; Z2U: OSC FREQUENCY IN MHZ
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Z2U0HFC .SET TRUE ; Z2U0: ENABLE HARDWARE FLOW CONTROL
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@@ -27,7 +27,7 @@ BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMED
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;
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CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
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CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
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CPUOSC .EQU 24000000 ; CPU OSC FREQ IN MHZ
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CPUOSC .EQU 12000000 ; CPU OSC FREQ IN MHZ
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INTMODE .EQU 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
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DEFSERCFG .EQU SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
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;
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@@ -528,7 +528,18 @@ BID_IMG2 .EQU BID_ROM0 + 3 ; NETWORK BOOT -+ ROM BANKS
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BID_ROMD0 .EQU BID_ROM0 + 4 ; FIRST ROM DRIVE BANK | ROM
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BID_ROMDN .EQU BID_ROMN ; LAST ROM DRIVE BANK V DRIVE
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;
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#IF FALSE
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#IF (!MDRAM)
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BID_RAMD0 .SET $FF ; RAM DRIVE DISABLED
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BID_RAMDN .SET $FF ; RAM DRIVE DISABLED
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#ENDIF
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;
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#IF (!MDROM)
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BID_ROMD0 .SET $FF ; ROM DRIVE DISABLED
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BID_ROMDN .SET $FF ; ROM DRIVE DISABLED
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#ENDIF
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;
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;
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#IF TRUE
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.ECHO "BID_AUX: " \ .ECHO BID_AUX \ .ECHO "\n"
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.ECHO "BID_BIOS: " \ .ECHO BID_BIOS \ .ECHO "\n"
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.ECHO "BID_USR: " \ .ECHO BID_USR \ .ECHO "\n"
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@@ -1,19 +1,32 @@
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ZZRCC has no real ROM. It has a single 512K RAM chip. The first
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256K of the RAM chip is loaded from the CF card. This 256K is
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treated like ROM by RomWBW. The remainder of the RAM (256K) is
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treated like RAM by RomWBW.
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Because of the memory constraints, notice that there is no RAM Disk,
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only a ROM disk. If you perform a ROM boot to an OS, the A: drive
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will be the ROM disk and will not be writable. Booting a ROM OS
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on this system is not typical since the system has a CF card by
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definition.
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Bank ROM RAM RAM
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---- --- --- ---
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0 HBIOS (IMG) RAMDISK RAMDISK
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1 ROMLDR+MON+CP/M2+ZSYS RAMDISK RAMDISK
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2 FTH+BAS+TBAS+PLAY+USR RAMDISK RAMDISK
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3 RESERVED RAMDISK RAMDISK
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4 ROMDISK RAMDISK RAMDISK
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5 ROMDISK RAMDISK RAMDISK
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6 ROMDISK RAMDISK RAMDISK
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7 ROMDISK RAMDISK RAMDISK
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0 HBIOS (IMG)
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1 ROMLDR+MON+CP/M2+ZSYS
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2 FTH+BAS+TBAS+PLAY+USR
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3 RESERVED
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4 ROMDISK
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5 ROMDISK
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6 ROMDISK
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7 ROMDISK
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8 ROMDISK BUF (CPM3) BUF (CPM3)
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9 ROMDISK BUF (CPM3) BUF (CPM3)
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A ROMDISK BUF (CPM3) BUF (CPM3)
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B ROMDISK BUF (CPM3) BUF (CPM3)
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C ROMDISK AUX (CPM3) TPA (CPM3)
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D ROMDISK HBIOS (EXEC) HBIOS (EXEC)
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E ROMDISK TPA-LO OS (CPM3)
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F ROMDISK COMMON (TPA-HI) COMMON (TPA-HI)
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8 BUF (CPM3) BUF (CPM3)
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9 BUF (CPM3) BUF (CPM3)
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A BUF (CPM3) BUF (CPM3)
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B BUF (CPM3) BUF (CPM3)
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C AUX (CPM3) TPA (CPM3)
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D HBIOS (EXEC) HBIOS (EXEC)
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E TPA-LO OS (CPM3)
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F COMMON (TPA-HI) COMMON (TPA-HI)
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--WBW 6:40 PM 2/16/2022
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@@ -1,7 +1,27 @@
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@echo off
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setlocal
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if not exist ..\..\Binary\RCZ280_nat_zzr.rom goto :eof
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set ROMFILE=..\..\Binary\RCZ280_nat_zzr.rom
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set ROMSIZE=262144
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if not exist %ROMFILE% goto :eof
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::
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:: The ROM image *must* be exactly 256K or the resulting disk
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:: image produced below will be invalid. Check for the proper size.
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::
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call :filesize %ROMFILE%
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if "%FILESIZE%" neq "%ROMSIZE%" (
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echo.
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echo.
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echo ERROR: "%ROMFILE%" is not exactly %ROMSIZE% bytes as required!!!
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echo You must specify a ROMSIZE of "256" when building the ZZRCC ROM image.
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echo.
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echo.
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exit /b 1
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)
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rem ..\..\Tools\srecord\srec_cat.exe ..\..\Binary\RCZ280_nat_zzr.rom -Binary -Exclude 0x5000 0x7000 zzr_romldr.hex -Intel -Output ..\..\Binary\RCZ280_nat_zzr.hex -Intel || exit /b
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@@ -13,4 +33,10 @@ rem copy /b zzr_cfldr.bin + zzr_ptbl.bin + zzr_fill_1.bin + zzr_mon.bin + zzr_fi
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copy /b zzr_cfldr.bin + zzr_ptbl.bin + zzr_fill_1.bin + zzr_mon.bin + zzr_fill_2.bin + ..\..\Binary\RCZ280_nat_zzr.rom + zzr_fill_3.bin ..\..\Binary\hd1024_zzr_prefix.dat || exit /b
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copy /b ..\..\Binary\hd1024_zzr_prefix.dat + ..\..\Binary\hd1024_cpm22.img + ..\..\Binary\hd1024_zsdos.img + ..\..\Binary\hd1024_nzcom.img + ..\..\Binary\hd1024_cpm3.img + ..\..\Binary\hd1024_zpm3.img + ..\..\Binary\hd1024_ws4.img ..\..\Binary\hd1024_zzr_combo.img || exit /b
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copy /b ..\..\Binary\hd1024_zzr_prefix.dat + ..\..\Binary\hd1024_cpm22.img + ..\..\Binary\hd1024_zsdos.img + ..\..\Binary\hd1024_nzcom.img + ..\..\Binary\hd1024_cpm3.img + ..\..\Binary\hd1024_zpm3.img + ..\..\Binary\hd1024_ws4.img ..\..\Binary\hd1024_zzr_combo.img || exit /b
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goto :eof
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:filesize
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set FILESIZE=%~z1
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goto :eof
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@@ -1,17 +1,15 @@
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HD1024ZZRPREFIX = hd1024_zzr_prefix.dat
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HD1024ZZZROMBOIMG = hd1024_zzr_combo.img
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ZZRROM = ../../Binary/RCZ280_nat_zzr.rom
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ZZRLDRROM = RCZ280_nat_zzr_ldr.rom
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ZZRROMHEX = RCZ280_nat_zzr.hex
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HD1024IMGS = ../../Binary/hd1024_cpm22.img ../../Binary/hd1024_zsdos.img ../../Binary/hd1024_nzcom.img \
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../../Binary/hd1024_cpm3.img ../../Binary/hd1024_zpm3.img ../../Binary/hd1024_ws4.img
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ZZRROMSIZE = 262144
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OBJECTS :=
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ifneq ($(wildcard $(ZZRROM)),)
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# OBJECTS += $(ZZRROMHEX) $(ZZRLDRROM) $(HD1024ZZRPREFIX) $(HD1024ZZZROMBOIMG)
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OBJECTS += $(ZZRROMHEX) $(HD1024ZZRPREFIX) $(HD1024ZZZROMBOIMG)
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OBJECTS += $(ZZRROMHEX) $(HD1024ZZRPREFIX) $(HD1024ZZZROMBOIMG)
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endif
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DEST=../../Binary
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@@ -22,16 +20,14 @@ include $(TOOLS)/Makefile.inc
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DIFFPATH = $(DIFFTO)/Binary
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$(HD1024ZZRPREFIX):
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# cat zzr_cfldr.bin zzr_ptbl.bin zzr_fill_1.bin zzr_mon.bin zzr_fill_2.bin $(ZZRLDRROM) zzr_fill_3.bin >$@
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zzrromchk:
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[ `stat -c%s $(ZZRROM)` = $(ZZRROMSIZE) ]
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$(HD1024ZZRPREFIX): zzrromchk
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cat zzr_cfldr.bin zzr_ptbl.bin zzr_fill_1.bin zzr_mon.bin zzr_fill_2.bin $(ZZRROM) zzr_fill_3.bin >$@
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$(HD1024ZZZROMBOIMG): $(HD1024ZZRPREFIX) $(HD1024IMGS)
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cat $^ > $@
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$(HD1024ZZZROMBOIMG): zzrromchk $(HD1024ZZRPREFIX) $(HD1024IMGS)
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cat $(HD1024ZZRPREFIX) $(HD1024IMGS) > $@
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$(ZZRROMHEX): $(ZZRROM)
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# srec_cat $(ZZRROM) -Binary -Exclude 0x5000 0x7000 zzr_romldr.hex -Intel -Output $(ZZRROMHEX) -Intel
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$(ZZRROMHEX): zzrromchk $(ZZRROM)
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srec_cat $(ZZRROM) -Binary -Output $(ZZRROMHEX) -Intel -CRLF
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$(ZZRLDRROM): $(ZZRROMHEX)
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srec_cat $(ZZRROMHEX) -Intel -Output $(ZZRLDRROM) -Binary
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@@ -2,4 +2,4 @@
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#DEFINE RMN 1
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#DEFINE RUP 1
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#DEFINE RTP 0
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#DEFINE BIOSVER "3.1.1-pre.157"
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#DEFINE BIOSVER "3.1.1-pre.158"
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@@ -3,5 +3,5 @@ rmn equ 1
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rup equ 1
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rtp equ 0
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biosver macro
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db "3.1.1-pre.157"
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db "3.1.1-pre.158"
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endm
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