mirror of
https://github.com/wwarthen/RomWBW.git
synced 2026-02-06 14:11:48 -06:00
eZ80: hbios io out operations now managed through a expected feature in the eZ80 on-chip rom
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@@ -351,6 +351,14 @@ RTCDEF .SET RTCDEF | %00001000 ; INITIAL SPEED LOW
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DEVECHO "\n"
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#ENDIF
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;
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; EMIT PREFIX REQUIRED BY EZ80 TO ENSURE CORRECT 16 BIT IO OPERATION
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;
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#IF (CPUFAM == CPU_EZ80)
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#DEFINE EZ80_IO .DB $49 $CF
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#ELSE
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#DEFINE EZ80_IO
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#ENDIF
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;
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;==================================================================================================
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; Z80 PAGE ZERO, VECTORS, ETC.
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;==================================================================================================
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@@ -623,21 +631,13 @@ HBX_ROM:
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;
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HBX_ROM:
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RLCA ; TIMES 2 - GET 16K PAGE INSTEAD OF 32K
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#IF (CPUFAM == CPU_EZ80)
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EXX
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LD BC,EZ80IOBASE<<8+MPGSEL_0
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OUT (C),A ; BANK_0: 0K - 16K
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INC A
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INC BC ; BC = MPGSEL_0
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OUT (C),A ; BANK_1: 16K - 32K
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EXX
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#ELSE
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EZ80_IO()
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OUT (MPGSEL_0),A ; BANK_0: 0K - 16K
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INC A ;
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EZ80_IO()
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OUT (MPGSEL_1),A ; BANK_1: 16K - 32K
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#IF (CPUFAM == CPU_Z280)
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#IF (CPUFAM == CPU_Z280)
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PCACHE
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#ENDIF
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#ENDIF
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RET ; DONE
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#ENDIF
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@@ -1407,12 +1407,8 @@ BOOTWAIT:
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;
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;LD A,(RTCDEFVAL) ; GET DEFAULT VALUE
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LD A,RTCDEF ; DEFAULT VALUE
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#IF (CPUFAM == CPU_EZ80)
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LD BC,EZ80IOBASE << 8 + RTCIO
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OUT (C),A ; BC IS THE APPLIED IO ADDRESS
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#ELSE
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EZ80_IO()
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OUT (RTCIO),A ; SET IT
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#ENDIF
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;
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#IF (PLATFORM == PLT_N8)
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LD A,N8_DEFACR ; ENSURE N8 ACR
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@@ -1436,12 +1432,8 @@ BOOTWAIT:
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LD A,DIAG_01
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#ENDIF
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;
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#IF (CPUFAM == CPU_EZ80)
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LD BC,EZ80IOBASE << 8 + FPLED_IO
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OUT (C),A ; BC IS THE APPLIED IO ADDRESS
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#ELSE
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EZ80_IO
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OUT (FPLED_IO),A
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#ENDIF
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#ENDIF
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;
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@@ -1710,27 +1702,7 @@ ROMRESUME:
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;
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#IF (MEMMGR == MM_Z2)
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;
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#IF (CPUFAM == CPU_EZ80)
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XOR A
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LD BC,EZ80IOBASE << 8 + MPGSEL_0
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OUT (C),A ; BC IS THE APPLIED IO ADDRESS
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INC A
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INC BC ; BC = MPGSEL_1
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OUT (C),A ; OUT (MPGSEL_1), $01
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LD A,64 - 2
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INC BC ; BC = MPGSEL_2
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OUT (C),A ; PROG THIRD 16K MMU REGISTER
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INC A
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INC BC ; BC = MPGSEL_3
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OUT (C),A ; PROG FOURTH 16K MMU REGISTER
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; ENABLE PAGING
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LD A,1
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INC BC ; BC = MPGENA
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OUT (C),A ; ENABLE MMU NOW
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#ELSE
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#IFDEF ROMBOOT
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#IFDEF ROMBOOT
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; IF THIS IS A ROM BOOT, SETUP THE FIRST 2 16K MMU REGISTERS
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; TO MAP THE LOWEST 32K OF PHYSICAL ROM TO THE LOW 32K OF
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; CPU ADDRESS SPACE (BANKING AREA). THE FIRST 16K MAPPING IS
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@@ -1739,28 +1711,32 @@ ROMRESUME:
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; MMU REGISTERS WILL BE 0 AT RESET!
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XOR A
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EZ80_IO()
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OUT (MPGSEL_0),A ; PROG FIRST 16K MMU REGISTER
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INC A
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EZ80_IO()
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OUT (MPGSEL_1),A ; PROG SECOND 16K MMU REGISTER
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#ENDIF
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#ENDIF
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;
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#IF (PLATFORM == PLT_DUO)
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#IF (PLATFORM == PLT_DUO)
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; DUO HAS VARIABLE RAM SIZE. RAM ALWAYS STARTS AT 2048K.
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; SETUP COMMON RAM FOR HIGHEST 32K OF RAM BASED ON TOTAL RAM.
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LD A,128 + (RAMSIZE / 16) - 2
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#ELSE
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#ELSE
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; NORMAL ZETA 2 SYSTEM HAS FIXED 512K OF RAM. SETUP COMMON
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; FOR TOP 32K OF THIS.
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LD A,64 - 2
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#ENDIF
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#ENDIF
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;
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EZ80_IO()
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OUT (MPGSEL_2),A ; PROG THIRD 16K MMU REGISTER
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INC A
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EZ80_IO()
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OUT (MPGSEL_3),A ; PROG FOURTH 16K MMU REGISTER
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; ENABLE PAGING
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LD A,1
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EZ80_IO()
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OUT (MPGENA),A ; ENABLE MMU NOW
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#ENDIF
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#ENDIF
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;
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@@ -1853,19 +1829,11 @@ S100MON_SKIP:
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; SEE COMMENTS ABOVE REGARDING THE FUNKY WAY THAT THE RTCDEFVAL IS
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; CREATED.
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;
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#IF (CPUFAM == CPU_EZ80)
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#DEFINE OUTA(p) PUSH BC
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#DEFCONT \ LD BC,EZ80IOBASE << 8 + p
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#DEFCONT \ OUT (C),A
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#DEFCONT \ POP BC
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#ELSE
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#DEFINE OUTA(P) OUT (RTCIO),A
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#ENDIF
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LD A,(RTCDEFVAL)
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LD (HB_RTCVAL),A
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OUTA(RTCIO) ; SET IT
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EZ80_IO()
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OUT (RTCIO),A ; SET IT
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DIAG(1) ; REAPPLY CURRENT DIAG LED SETUP
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;
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;--------------------------------------------------------------------------------------------------
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@@ -7183,14 +7151,8 @@ FP_SETLEDS:
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XOR $FF ; INVERT BITS IF NEEDED
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#ENDIF
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#IF (CPUFAM == CPU_EZ80)
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PUSH BC
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LD BC,EZ80IOBASE << 8 + FPLED_IO
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OUT (C),A ; BC IS THE APPLIED IO ADDRESS
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POP BC
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#ELSE
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EZ80_IO
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OUT (FPLED_IO),A ; WRITE
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#ENDIF
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FP_SETLEDS1:
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POP HL ; RESTORE HL
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RET ; DONE
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