mirror of https://github.com/wwarthen/RomWBW.git
Browse Source
- Refined sd, ide, and ppide drivers to improve hardware compatibility - Improved BPBIOS build processpull/3/head
Wayne Warthen
10 years ago
63 changed files with 7096 additions and 910 deletions
@ -0,0 +1,12 @@ |
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@echo off |
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set ROM=Output\SBC_simh.rom |
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if not "%1"=="" set ROM=Output\%1.rom |
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if not exist %ROM% goto romerr |
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rem start C:\Users\WWarthen\Bin\putty.exe -load "SIMH Telnet" |
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start /w tools\altairz80.exe sim.cfg %ROM% |
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goto :eof |
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|
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:romerr |
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echo ROM Image %ROM% Not Found! |
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pause |
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goto :eof |
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@ -0,0 +1,8 @@ |
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This directory contains the official ZCPR 3.3 source with minor customizations |
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to support the BPBIOS build in the parent directory: |
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|
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- Modified to produce a relocatable image compatibile with BPBUILD |
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- Build process (Build.cmd) creates ZCPR33T.REL and ZCPR33N.REL based |
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on Z3BASET.LIB and B3BASEN.LIB from parent directory. |
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|
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See "@WBW Z3ENV.txt" file in parent directory for more information. |
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@ -1,128 +1,226 @@ |
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; B/P Bios System Z3 Definition File. |
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|
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; This file is adapted from the basic Z3BASE.LIB configuration file used for |
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; most ZCPR33 systems. It has added the new definitions for the Resident |
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; User Space defined in B/P Bios descriptions. |
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;========================================================================= |
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;== NOTE: The Starting Address of the User Space marks the lower == |
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;== base of memory and MUST be entered. B/P Bios Utilities use == |
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;== this address to locate many portions of the operating system. == |
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;========================================================================= |
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; To change your systems definition, first sketch out the memory map in the |
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; comment table, then set the equates to reflect the memory map, doing any |
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; required calculations for element sizes and required spaces. As an |
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; alternative, just leave this file alone and configure everything with |
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; the utilities provided. |
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|
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; FFE0 - FFFF 32 Bytes HBIOS Reserved |
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; FFB0 - FFDF 48 Bytes ZCPR3 External Stack |
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; FF00 - FFAF 176 Bytes Multiple Command Line Buffer |
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; FE00 - FEFF 256 Bytes Environment Descriptor |
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; Bytes 00H-7FH: Z3 Parameters |
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; Bytes 80H-FFH: Z3 TCAP |
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; FDFF 1 Byte Wheel byte |
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; FDF4 - FDFE 11 Bytes Path (5 elements) |
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; FDD0 - FDF3 36 Bytes ZCPR3 External FCB |
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; FD80 - FDCF 80 Bytes ZCPR3 Message Buffers |
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; FD00 - FD7F 128 Bytes ZCPR3 Shell Stack |
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; FC00 - FCFF 256 Bytes Named Directory Buffer |
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; FA00 - FBFF 512 Bytes Flow Command Package |
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; F200 - F9FF 2.0 KBytes Resident Command Package |
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; EC00 - F1FF 1.5 KBytes IO Package |
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; E900 - EBFF .75 KBytes Resident User Space |
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|
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; The remainder is for the Operating System. Exact sizes vary depending |
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; primarily on the Number and sizes of Hard Drive Partitions, but may be: |
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|
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; D100 - EBFF 5.0 KBytes B/P BIOS (unbanked version) |
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; C300 - D0FF 3.5 KBytes ZSDOS 1.0 BDOS |
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; BB00 - C2FF 2 KBytes ZCPR 3.3 Command Processor |
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; 0100 - BAFF ~46 KBytes Transient Program Area |
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; 0000 - 00FF 256 Bytes Standard CP/M Buffers |
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;======================================================================== |
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|
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FALSE EQU 0 |
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TRUE EQU NOT FALSE |
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|
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YES EQU TRUE |
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NO EQU FALSE |
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|
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; The External Stack is placed in the very top position in memory. It is |
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; mandatory for B/P Bios and ZCPR 3.3. |
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|
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;EXTSTK EQU 0FFD0H ; ZCPR3 External Stack |
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EXTSTK EQU 0FFB0H ; ZCPR3 External Stack |
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EXTSTKS EQU YES |
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|
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; The Multiple Command Line Buffer is placed in the Top Page of Memory to |
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; place it above the Environment. It is mandatory for ZCPR 3.3. |
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|
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Z3CL EQU 0FF00H ; ZCPR3 Command Line Buffer |
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;Z3CLS EQU 208-5 ; Size of Command Line Buffer-5 |
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Z3CLS EQU 176-5 ; Size of Command Line Buffer-5 |
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|
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; The ZCPR3 External Environment Descriptor is mandatory B/P Bios & ZCPR 3.3. |
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; The Environment Descriptor MUST begin on an even Page Boundary (xx00H). |
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|
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Z3ENV EQU 0FE00H ; Environment Descriptors |
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Z3ENVS EQU 2 ; Size of Env Descriptor in 128-Byte Blks |
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; Z3BASE - Dynamic Configuration |
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; |
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; ZCPR33 is copyright 1987 by Echelon, Inc. All rights reserved. End-user |
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; distribution and duplication permitted for non-commercial purposes only. |
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; Any commercial use of ZCPR33, defined as any situation where the duplicator |
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; recieves revenue by duplicating or distributing ZCPR33 by itself or in |
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; conjunction with any hardware or software product, is expressly prohibited |
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; unless authorized in writing by Echelon. |
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; |
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; This is a special version of Z3BASE, inspired by Joe Wright's Z3BASE |
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; for Z-Com. All segment addresses are automatically derived when the |
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; CCP equate is set. The benefit of this is that reconfiguration of the |
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; system after initial installation is greatly eased. |
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; |
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; Although this version of Z3BASE is being distributed with ZCPR 3.3, any |
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; previous version of Z3BASE can be used to assemble the Z33 Command |
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; Processor. No new symbols are needed. So, if you have an existing |
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; Z3BASE, go ahead and use it. |
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; |
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; Instructions: |
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; |
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; The user should first design the ZCPR3 memory usage using the chart |
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; below. (Echelon recommends the chart be filled out, even though it is |
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; not read by the assembler, so that your system will be self-documenting.) |
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; Then set the CCP equate for the beginning address of ZCPR3. Next, examine |
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; and change the SEGn equates which follow in the file to ensure that the |
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; system segments and buffers are placed at the proper addresses. |
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; |
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; This file has been customized for use with AMPRO hard disk systems. The |
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; target configuration has support for hard disks up to 49 Meg, extended |
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; IOP support, and 28-entry NDR. |
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; |
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;**************************************************************** |
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;* * |
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;* Z3BASE.LIB -- Base Addresses for ZCPR 3.3/Z-System * |
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;* * |
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;* Segments: * |
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;* * |
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;* Segment Function * |
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;* ------- -------- * |
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;* ZRDOS Echelon Z80 Replacement Disk Operating * |
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;* System, Version 1.7 (Public ZRDOS Plus) * |
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;* CBIOSZ Ampro-compatible BIOS with additional * |
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;* ZCPR3 initialization routines * |
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;* ZCPR3 Echelon Z80 Command Processor * |
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;* Replacement, Version 3.3 (ZCPR3) * |
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;* *.ENV All Environment Descriptors * |
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;* *.FCP All Flow Command Packages * |
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;* *.NDR All Named Directory Definition Files * |
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;* *.RCP All Resident Command Packages * |
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;* *.IOP All Input/Output Packages * |
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;* * |
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;* * |
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;* Memory Map of System (for CCP EQU 0BC00H): * |
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;* * |
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;* Address Range Size Function * |
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;* ------------- ------- -------- * |
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;* 0 - FF 256 b Standard CP/M Buffers except * |
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;* 100 - C3FF ~49 K Transient Program Area * |
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;* BC00 - C3FF 2K ZCPR 3.3 Command Processor * |
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;* C400 - D1FF 3.5 K ZRDOS * |
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;* D200 - EAFF 6.25K Ampro BIOS w/hard disk buffers * |
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;* EB00 - F2FF 2 K Resident Command Package * |
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;* F300 - F8FF 1.5 K Input/Output Package * |
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;* F900 - FAFF .5 K Flow Command Package * |
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;* FB00 - FB7F 128 b ZCPR3 Shell Stack * |
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;* FB80 - FBCF 80 b ZCPR3 Message Buffers * |
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;* FBD0 - FBF3 36 b ZCPR3 External FCB * |
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;* FBF4 - FBFE 11 b ZCPR3 External Path * |
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;* FBFF 1 b Wheel Byte * |
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;* FC00 - FDFF .5 K Memory-Based Named Directory * |
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;* FE00 - FEFF 256 b Environment Descriptor * |
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;* Bytes 00H-7FH: Z3 Parameters * |
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;* Bytes 80H-FFH: Z3 TCAP * |
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;* FF00 - FFCF 208 B Multiple Command Line Buffer * |
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;* FD00 - FFFF 48 b ZCPR3 External Stack * |
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;**************************************************************** |
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|
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FALSE equ 0 |
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TRUE equ NOT FALSE |
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|
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Z3REV EQU 33 ; ZCPR3 REV NUMBER |
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MSIZE EQU 54 ; SIZE OF CPM SYSTEM |
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|
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BASE EQU 0 |
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|
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CCP EQU 0BC00H ; ZCPR3 COMMAND PROCESSOR |
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|
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seg1 equ CCP+2F00h ; 11.75k from CCP to here (adding 2k ZCPR, |
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; 3.5k DOS, and 6.25k BIOS). |
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|
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; |
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; RCP definition. Set RCPS to 0 to eliminate RCP |
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; |
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|
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RCPS EQU 16 ; 16 128-byte Blocks (2K bytes) |
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|
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IF RCPS NE 0 |
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RCP EQU seg1 ; RESIDENT COMMAND PACKAGE |
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ELSE |
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RCP EQU 0 |
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ENDIF |
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|
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seg2 equ seg1+[rcps*128] |
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|
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; |
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; IOP definition. Set IOPS to 0 to eliminate IOP |
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; |
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IOPS EQU 12 ; 12 128-byte Blocks (1.5K bytes) |
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|
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IF IOPS NE 0 |
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IOP EQU seg2 ; REDIRECTABLE I/O PACKAGE |
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ELSE |
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IOP EQU 0 |
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ENDIF |
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|
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seg3 equ seg2+[iops*128] |
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|
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; |
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; FCP definition. Set FCPS to 0 to eliminate FCP |
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; |
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|
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FCPS EQU 4 ; 4 128-byte Blocks (0.5K bytes) |
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|
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IF FCPS NE 0 |
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fcp equ seg3 |
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ELSE |
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fcp equ 0 |
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ENDIF |
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|
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seg4 equ seg3+[fcps*128] |
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|
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; |
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; Shell Stack definition. Set SHSTKS to 0 to eliminate Shell Stack |
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; |
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|
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; The ZCPR3 Wheel Byte is mandatory for ZCPR 3.3. |
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SHSTKS EQU 4 ; NUMBER OF SHSIZE-BYTE SHELL STACK ENTRIES |
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SHSIZE EQU 32 ; SIZE OF A SHELL STACK ENTRY |
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; (STACK SIZE = SHSTKS * SHSIZE) |
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IF SHSTKS NE 0 |
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SHSTK EQU seg4 |
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ELSE |
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SHSTK EQU 0 |
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ENDIF |
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|
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Z3WHL EQU 0FDFFH ; Wheel Byte Address |
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Z3WHLS EQU YES |
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seg5 equ seg4+[shstks*shsize] |
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|
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; The Path is mandatory for ZCPR 3.3. |
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; |
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; The ZCPR3 Message Buffers are mandatory for ZCPR 3.3. |
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; |
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Z3MSG EQU seg5 ; ZCPR3 MESSAGE BUFFER |
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|
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EXPATH EQU 0FDF4H ; External Path starting Address |
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EXPATHS EQU 5 ; (Path Size = EXPATHS*2 + 1 = 11 bytes) |
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; This defines 5 2-byte Path Elements |
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seg6 equ seg5+80 |
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|
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; |
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; The ZCPR3 External FCB is mandatory for ZCPR 3.3. |
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; |
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|
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EXTFCB EQU 0FDD0H ; 36-Byte ZCPR3 External FCB |
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EXTFCBS EQU YES |
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EXTFCB EQU seg6 ; ZCPR3 EXTERNAL FCB |
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|
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; The ZCPR3 Message Buffers are mandatory for ZCPR 3.3. |
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seg7 equ seg6+36 |
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|
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Z3MSG EQU 0FD80H ; 80-Byte ZCPR3 Message Buffer |
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Z3MSGS EQU YES |
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; |
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; The Path is mandatory for ZCPR 3.3. No more than 5 path elements can be |
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; used with this Z3BASE.LIB file. |
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; |
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|
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; Shell Stack definition. Set SHSTKS to 0 to eliminate Shell Stack |
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EXPATH EQU seg7 ; EXTERNAL PATH |
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EXPATHS EQU 5 ; 5 2-byte Path Elements |
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; (PATH SIZE = EXPATHS*2 + 1) |
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|
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seg8 equ seg7+[expaths*2]+1 |
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|
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; |
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; The ZCPR3 Wheel Byte is mandatory for ZCPR 3.3. |
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; |
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|
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Z3WHL EQU seg8 ; WHEEL BYTE ADDRESS |
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|
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SHSTK EQU 0FD00H ; Shell Stack Starting Address |
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SHSTKS EQU 4 ; Number of SHSIZE-Byte Shell Stack entries |
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SHSIZE EQU 32 ; (Stack Size = SHSTKS * SHSIZE = 128 Bytes) |
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seg9 equ seg8+1 |
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|
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; |
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; ZCPR3 Named Directory Buffer definition. Set Z3NDIRS to 0 to eliminate |
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; the named directory buffer. |
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; the named directory buffer. If Z3NDIRS is changed, also change the seg10 |
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; equate below. |
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; |
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Z3NDIRS EQU 28 ; 28 18-byte Named Directory Elements permitted |
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; (NDIR SIZE = Z3NDIRS*18 + 1 for trailing 0) |
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IF Z3NDIRS NE 0 |
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Z3NDIR EQU seg9 ; ZCPR3 NAMED DIRECTORY AREA |
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ELSE |
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Z3NDIR EQU 0 |
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ENDIF |
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|
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Z3NDIR EQU 0FC00H ; Start of Named Directory Buffer |
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Z3NDIRS EQU 14 ; Number of Named Directory Elements |
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; (NDIR Size = Z3NDIRS * 18 + 1 = 253 Bytes) |
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seg10 equ seg9+512 ; add 512 for 28-entry NDR |
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; add 256 for 14-entry NDR ("standard") |
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; add 0 if Z3NDIRS is set to 0 |
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|
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; Flow Command Package definition. Set FCPS to 0 to eliminate FCP |
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; |
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; The ZCPR3 External Environment Descriptor is mandatory for ZCPR 3.3. |
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; Echelon recommends you work this out so that your ENV begins at address |
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; FE00h, but this is only a recommendation and not mandatory. |
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; |
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|
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FCP EQU 0FA00H ; Start of Flow Command Package |
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FCPS EQU 4 ; (FCP Size = 128 * FCPS = 512 Bytes) |
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Z3ENV EQU seg10 ; ENVIRONMENT DESCRIPTORS |
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Z3ENVS EQU 2 ; SIZE OF ENVIRONMENT DESCRIPTOR IN 128-BYTE BLOCKS |
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|
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; Resident Command Processor Definition. Set RCPS to 0 to eliminate RCP |
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seg11 equ seg10+[z3envs*128] |
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|
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RCP EQU 0F200H ; Start of Resident Command Processor |
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RCPS EQU 16 ; (RCP Size = 128 * RCPS = 2 kBytes) |
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; |
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; The ZCPR3 External Command Line Buffer is mandatory for ZCPR 3.3. |
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; |
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|
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; IO Package definition. Set IOPS to 0 to eliminate IOP |
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Z3CL EQU seg11 ; ZCPR3 COMMAND LINE BUFFER |
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Z3CLS EQU 208 ; SIZE OF COMMAND LINE BUFFER |
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|
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IOP EQU 0EC00H ; Start of IO Package |
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IOPS DEFL 12 ; (IOP Size = 128 * IOPS = 1.5 kBytes) |
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seg12 equ seg11+z3cls |
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|
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;========================================================================= |
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; Resident User Space Definition. Set USPCS to 0 to eliminate USPC. |
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; The USPC Value marks the Lower Limit of Reserved Common High Memory and |
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; MUST BE PRESENT! |
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; |
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; The ZCPR3 External Stack is mandatory for ZCPR 3.3. |
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; |
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|
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USPC EQU 0E900H ; Start of Resident User Space (MANDATORY) |
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USPCS EQU 6 ; (USPC Size = 128 * USPCS = 0.75 kBytes) |
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EXTSTK EQU seg12 ; ZCPR3 EXTERNAL STACK |
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|
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;--- End of Z3BASE.LIB --- |
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|
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; end of Z3BASE.LIB |
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|
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@ -1,226 +0,0 @@ |
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; Z3BASE - Dynamic Configuration |
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; |
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; ZCPR33 is copyright 1987 by Echelon, Inc. All rights reserved. End-user |
|||
; distribution and duplication permitted for non-commercial purposes only. |
|||
; Any commercial use of ZCPR33, defined as any situation where the duplicator |
|||
; recieves revenue by duplicating or distributing ZCPR33 by itself or in |
|||
; conjunction with any hardware or software product, is expressly prohibited |
|||
; unless authorized in writing by Echelon. |
|||
; |
|||
; This is a special version of Z3BASE, inspired by Joe Wright's Z3BASE |
|||
; for Z-Com. All segment addresses are automatically derived when the |
|||
; CCP equate is set. The benefit of this is that reconfiguration of the |
|||
; system after initial installation is greatly eased. |
|||
; |
|||
; Although this version of Z3BASE is being distributed with ZCPR 3.3, any |
|||
; previous version of Z3BASE can be used to assemble the Z33 Command |
|||
; Processor. No new symbols are needed. So, if you have an existing |
|||
; Z3BASE, go ahead and use it. |
|||
; |
|||
; Instructions: |
|||
; |
|||
; The user should first design the ZCPR3 memory usage using the chart |
|||
; below. (Echelon recommends the chart be filled out, even though it is |
|||
; not read by the assembler, so that your system will be self-documenting.) |
|||
; Then set the CCP equate for the beginning address of ZCPR3. Next, examine |
|||
; and change the SEGn equates which follow in the file to ensure that the |
|||
; system segments and buffers are placed at the proper addresses. |
|||
; |
|||
; This file has been customized for use with AMPRO hard disk systems. The |
|||
; target configuration has support for hard disks up to 49 Meg, extended |
|||
; IOP support, and 28-entry NDR. |
|||
; |
|||
;**************************************************************** |
|||
;* * |
|||
;* Z3BASE.LIB -- Base Addresses for ZCPR 3.3/Z-System * |
|||
;* * |
|||
;* Segments: * |
|||
;* * |
|||
;* Segment Function * |
|||
;* ------- -------- * |
|||
;* ZRDOS Echelon Z80 Replacement Disk Operating * |
|||
;* System, Version 1.7 (Public ZRDOS Plus) * |
|||
;* CBIOSZ Ampro-compatible BIOS with additional * |
|||
;* ZCPR3 initialization routines * |
|||
;* ZCPR3 Echelon Z80 Command Processor * |
|||
;* Replacement, Version 3.3 (ZCPR3) * |
|||
;* *.ENV All Environment Descriptors * |
|||
;* *.FCP All Flow Command Packages * |
|||
;* *.NDR All Named Directory Definition Files * |
|||
;* *.RCP All Resident Command Packages * |
|||
;* *.IOP All Input/Output Packages * |
|||
;* * |
|||
;* * |
|||
;* Memory Map of System (for CCP EQU 0BC00H): * |
|||
;* * |
|||
;* Address Range Size Function * |
|||
;* ------------- ------- -------- * |
|||
;* 0 - FF 256 b Standard CP/M Buffers except * |
|||
;* 100 - C3FF ~49 K Transient Program Area * |
|||
;* BC00 - C3FF 2K ZCPR 3.3 Command Processor * |
|||
;* C400 - D1FF 3.5 K ZRDOS * |
|||
;* D200 - EAFF 6.25K Ampro BIOS w/hard disk buffers * |
|||
;* EB00 - F2FF 2 K Resident Command Package * |
|||
;* F300 - F8FF 1.5 K Input/Output Package * |
|||
;* F900 - FAFF .5 K Flow Command Package * |
|||
;* FB00 - FB7F 128 b ZCPR3 Shell Stack * |
|||
;* FB80 - FBCF 80 b ZCPR3 Message Buffers * |
|||
;* FBD0 - FBF3 36 b ZCPR3 External FCB * |
|||
;* FBF4 - FBFE 11 b ZCPR3 External Path * |
|||
;* FBFF 1 b Wheel Byte * |
|||
;* FC00 - FDFF .5 K Memory-Based Named Directory * |
|||
;* FE00 - FEFF 256 b Environment Descriptor * |
|||
;* Bytes 00H-7FH: Z3 Parameters * |
|||
;* Bytes 80H-FFH: Z3 TCAP * |
|||
;* FF00 - FFCF 208 B Multiple Command Line Buffer * |
|||
;* FD00 - FFFF 48 b ZCPR3 External Stack * |
|||
;**************************************************************** |
|||
|
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FALSE equ 0 |
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TRUE equ NOT FALSE |
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|
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Z3REV EQU 33 ; ZCPR3 REV NUMBER |
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MSIZE EQU 54 ; SIZE OF CPM SYSTEM |
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|
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BASE EQU 0 |
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|
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CCP EQU 0BC00H ; ZCPR3 COMMAND PROCESSOR |
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|
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seg1 equ CCP+2F00h ; 11.75k from CCP to here (adding 2k ZCPR, |
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; 3.5k DOS, and 6.25k BIOS). |
|||
|
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; |
|||
; RCP definition. Set RCPS to 0 to eliminate RCP |
|||
; |
|||
|
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RCPS EQU 16 ; 16 128-byte Blocks (2K bytes) |
|||
|
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IF RCPS NE 0 |
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RCP EQU seg1 ; RESIDENT COMMAND PACKAGE |
|||
ELSE |
|||
RCP EQU 0 |
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ENDIF |
|||
|
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seg2 equ seg1+[rcps*128] |
|||
|
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; |
|||
; IOP definition. Set IOPS to 0 to eliminate IOP |
|||
; |
|||
IOPS EQU 12 ; 12 128-byte Blocks (1.5K bytes) |
|||
|
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IF IOPS NE 0 |
|||
IOP EQU seg2 ; REDIRECTABLE I/O PACKAGE |
|||
ELSE |
|||
IOP EQU 0 |
|||
ENDIF |
|||
|
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seg3 equ seg2+[iops*128] |
|||
|
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; |
|||
; FCP definition. Set FCPS to 0 to eliminate FCP |
|||
; |
|||
|
|||
FCPS EQU 4 ; 4 128-byte Blocks (0.5K bytes) |
|||
|
|||
IF FCPS NE 0 |
|||
fcp equ seg3 |
|||
ELSE |
|||
fcp equ 0 |
|||
ENDIF |
|||
|
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seg4 equ seg3+[fcps*128] |
|||
|
|||
; |
|||
; Shell Stack definition. Set SHSTKS to 0 to eliminate Shell Stack |
|||
; |
|||
|
|||
SHSTKS EQU 4 ; NUMBER OF SHSIZE-BYTE SHELL STACK ENTRIES |
|||
SHSIZE EQU 32 ; SIZE OF A SHELL STACK ENTRY |
|||
; (STACK SIZE = SHSTKS * SHSIZE) |
|||
IF SHSTKS NE 0 |
|||
SHSTK EQU seg4 |
|||
ELSE |
|||
SHSTK EQU 0 |
|||
ENDIF |
|||
|
|||
seg5 equ seg4+[shstks*shsize] |
|||
|
|||
; |
|||
; The ZCPR3 Message Buffers are mandatory for ZCPR 3.3. |
|||
; |
|||
Z3MSG EQU seg5 ; ZCPR3 MESSAGE BUFFER |
|||
|
|||
seg6 equ seg5+80 |
|||
|
|||
; |
|||
; The ZCPR3 External FCB is mandatory for ZCPR 3.3. |
|||
; |
|||
|
|||
EXTFCB EQU seg6 ; ZCPR3 EXTERNAL FCB |
|||
|
|||
seg7 equ seg6+36 |
|||
|
|||
; |
|||
; The Path is mandatory for ZCPR 3.3. No more than 5 path elements can be |
|||
; used with this Z3BASE.LIB file. |
|||
; |
|||
|
|||
EXPATH EQU seg7 ; EXTERNAL PATH |
|||
EXPATHS EQU 5 ; 5 2-byte Path Elements |
|||
; (PATH SIZE = EXPATHS*2 + 1) |
|||
|
|||
seg8 equ seg7+[expaths*2]+1 |
|||
|
|||
; |
|||
; The ZCPR3 Wheel Byte is mandatory for ZCPR 3.3. |
|||
; |
|||
|
|||
Z3WHL EQU seg8 ; WHEEL BYTE ADDRESS |
|||
|
|||
seg9 equ seg8+1 |
|||
|
|||
; |
|||
; ZCPR3 Named Directory Buffer definition. Set Z3NDIRS to 0 to eliminate |
|||
; the named directory buffer. If Z3NDIRS is changed, also change the seg10 |
|||
; equate below. |
|||
; |
|||
Z3NDIRS EQU 28 ; 28 18-byte Named Directory Elements permitted |
|||
; (NDIR SIZE = Z3NDIRS*18 + 1 for trailing 0) |
|||
IF Z3NDIRS NE 0 |
|||
Z3NDIR EQU seg9 ; ZCPR3 NAMED DIRECTORY AREA |
|||
ELSE |
|||
Z3NDIR EQU 0 |
|||
ENDIF |
|||
|
|||
seg10 equ seg9+512 ; add 512 for 28-entry NDR |
|||
; add 256 for 14-entry NDR ("standard") |
|||
; add 0 if Z3NDIRS is set to 0 |
|||
|
|||
; |
|||
; The ZCPR3 External Environment Descriptor is mandatory for ZCPR 3.3. |
|||
; Echelon recommends you work this out so that your ENV begins at address |
|||
; FE00h, but this is only a recommendation and not mandatory. |
|||
; |
|||
|
|||
Z3ENV EQU seg10 ; ENVIRONMENT DESCRIPTORS |
|||
Z3ENVS EQU 2 ; SIZE OF ENVIRONMENT DESCRIPTOR IN 128-BYTE BLOCKS |
|||
|
|||
seg11 equ seg10+[z3envs*128] |
|||
|
|||
; |
|||
; The ZCPR3 External Command Line Buffer is mandatory for ZCPR 3.3. |
|||
; |
|||
|
|||
Z3CL EQU seg11 ; ZCPR3 COMMAND LINE BUFFER |
|||
Z3CLS EQU 208 ; SIZE OF COMMAND LINE BUFFER |
|||
|
|||
seg12 equ seg11+z3cls |
|||
|
|||
; |
|||
; The ZCPR3 External Stack is mandatory for ZCPR 3.3. |
|||
; |
|||
|
|||
EXTSTK EQU seg12 ; ZCPR3 EXTERNAL STACK |
|||
|
|||
; end of Z3BASE.LIB |
|||
|
|||
@ -0,0 +1,126 @@ |
|||
; B/P Bios System Z3 Definition File. |
|||
|
|||
; This file is adapted from the basic Z3BASE.LIB configuration file used for |
|||
; most ZCPR33 systems. It has added the new definitions for the Resident |
|||
; User Space defined in B/P Bios descriptions. |
|||
;========================================================================= |
|||
;== NOTE: The Starting Address of the User Space marks the lower == |
|||
;== base of memory and MUST be entered. B/P Bios Utilities use == |
|||
;== this address to locate many portions of the operating system. == |
|||
;========================================================================= |
|||
; To change your systems definition, first sketch out the memory map in the |
|||
; comment table, then set the equates to reflect the memory map, doing any |
|||
; required calculations for element sizes and required spaces. As an |
|||
; alternative, just leave this file alone and configure everything with |
|||
; the utilities provided. |
|||
|
|||
; FE00 - FFFF 512 Bytes HBIOS Reserved |
|||
; FDFF 1 Byte Wheel byte |
|||
; FDF4 - FDFE 11 Bytes Path (5 elements) |
|||
; FDD0 - FDF3 36 Bytes ZCPR3 External FCB |
|||
; FD80 - FDCF 80 Bytes ZCPR3 Message Buffers |
|||
; FD00 - FD7F 128 Bytes ZCPR3 Shell Stack |
|||
; FC00 - FCFF 256 Bytes Named Directory Buffer |
|||
; FA00 - FBFF 512 Bytes Flow Command Package |
|||
; F200 - F9FF 2.0 KBytes Resident Command Package |
|||
; EC00 - F1FF 1.5 KBytes IO Package |
|||
; EBD0 - EBFF 48 Bytes ZCPR3 External Stack |
|||
; EB00 - EBAF 176 Bytes Multiple Command Line Buffer |
|||
; EA00 - EAFF 256 Bytes Environment Descriptor |
|||
; Bytes 00H-7FH: Z3 Parameters |
|||
; Bytes 80H-FFH: Z3 TCAP |
|||
; E700 - E9FF .75 KBytes Resident User Space |
|||
|
|||
; The remainder is for the Operating System. Exact sizes vary depending |
|||
; primarily on the Number and sizes of Hard Drive Partitions, but may be: |
|||
|
|||
; D300 - E6FF 5.0 KBytes B/P BIOS (unbanked version) |
|||
; C500 - D2FF 3.5 KBytes ZSDOS 1.0 BDOS |
|||
; BD00 - C4FF 2 KBytes ZCPR 3.3 Command Processor |
|||
; 0100 - BCFF ~47 KBytes Transient Program Area |
|||
; 0000 - 00FF 256 Bytes Standard CP/M Buffers |
|||
;======================================================================== |
|||
|
|||
FALSE EQU 0 |
|||
TRUE EQU NOT FALSE |
|||
|
|||
YES EQU TRUE |
|||
NO EQU FALSE |
|||
|
|||
; The External Stack is placed in the very top position in memory. It is |
|||
; mandatory for B/P Bios and ZCPR 3.3. |
|||
|
|||
EXTSTK EQU 0EBD0H ; ZCPR3 External Stack |
|||
EXTSTKS EQU YES |
|||
|
|||
; The Multiple Command Line Buffer is placed in the Top Page of Memory to |
|||
; place it above the Environment. It is mandatory for ZCPR 3.3. |
|||
|
|||
Z3CL EQU 0EB00H ; ZCPR3 Command Line Buffer |
|||
Z3CLS EQU 208-5 ; Size of Command Line Buffer-5 |
|||
|
|||
; The ZCPR3 External Environment Descriptor is mandatory B/P Bios & ZCPR 3.3. |
|||
; The Environment Descriptor MUST begin on an even Page Boundary (xx00H). |
|||
|
|||
Z3ENV EQU 0EA00H ; Environment Descriptors |
|||
Z3ENVS EQU 2 ; Size of Env Descriptor in 128-Byte Blks |
|||
|
|||
; The ZCPR3 Wheel Byte is mandatory for ZCPR 3.3. |
|||
|
|||
Z3WHL EQU 0FDFFH ; Wheel Byte Address |
|||
Z3WHLS EQU YES |
|||
|
|||
; The Path is mandatory for ZCPR 3.3. |
|||
|
|||
EXPATH EQU 0FDF4H ; External Path starting Address |
|||
EXPATHS EQU 5 ; (Path Size = EXPATHS*2 + 1 = 11 bytes) |
|||
; This defines 5 2-byte Path Elements |
|||
|
|||
; The ZCPR3 External FCB is mandatory for ZCPR 3.3. |
|||
|
|||
EXTFCB EQU 0FDD0H ; 36-Byte ZCPR3 External FCB |
|||
EXTFCBS EQU YES |
|||
|
|||
; The ZCPR3 Message Buffers are mandatory for ZCPR 3.3. |
|||
|
|||
Z3MSG EQU 0FD80H ; 80-Byte ZCPR3 Message Buffer |
|||
Z3MSGS EQU YES |
|||
|
|||
; Shell Stack definition. Set SHSTKS to 0 to eliminate Shell Stack |
|||
|
|||
SHSTK EQU 0FD00H ; Shell Stack Starting Address |
|||
SHSTKS EQU 4 ; Number of SHSIZE-Byte Shell Stack entries |
|||
SHSIZE EQU 32 ; (Stack Size = SHSTKS * SHSIZE = 128 Bytes) |
|||
|
|||
; ZCPR3 Named Directory Buffer definition. Set Z3NDIRS to 0 to eliminate |
|||
; the named directory buffer. |
|||
|
|||
Z3NDIR EQU 0FC00H ; Start of Named Directory Buffer |
|||
Z3NDIRS EQU 14 ; Number of Named Directory Elements |
|||
; (NDIR Size = Z3NDIRS * 18 + 1 = 253 Bytes) |
|||
|
|||
; Flow Command Package definition. Set FCPS to 0 to eliminate FCP |
|||
|
|||
FCP EQU 0FA00H ; Start of Flow Command Package |
|||
FCPS EQU 4 ; (FCP Size = 128 * FCPS = 512 Bytes) |
|||
|
|||
; Resident Command Processor Definition. Set RCPS to 0 to eliminate RCP |
|||
|
|||
RCP EQU 0F200H ; Start of Resident Command Processor |
|||
RCPS EQU 16 ; (RCP Size = 128 * RCPS = 2 kBytes) |
|||
|
|||
; IO Package definition. Set IOPS to 0 to eliminate IOP |
|||
|
|||
IOP EQU 0EC00H ; Start of IO Package |
|||
IOPS DEFL 12 ; (IOP Size = 128 * IOPS = 1.5 kBytes) |
|||
|
|||
;========================================================================= |
|||
; Resident User Space Definition. Set USPCS to 0 to eliminate USPC. |
|||
; The USPC Value marks the Lower Limit of Reserved Common High Memory and |
|||
; MUST BE PRESENT! |
|||
|
|||
USPC EQU 0E700H ; Start of Resident User Space (MANDATORY) |
|||
USPCS EQU 6 ; (USPC Size = 128 * USPCS = 0.75 kBytes) |
|||
|
|||
;--- End of Z3BASE.LIB --- |
|||
|
|||
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@ -0,0 +1,373 @@ |
|||
;:::::::::::::::::::::::::::::::::::::::::::::::********************** |
|||
; B/P BIOS Configuration and Equate File. ** System Dependant ** |
|||
; - D-X Designs Pty Ltd P112 CPU Board - ********************** |
|||
; Tailor your system here. |
|||
; |
|||
; 30 Aug 01 - Cleaned up for GPL release. HFB |
|||
; 11 May 97 - Added GIDE and adjusted HD equates. HFB |
|||
; 5 Jan 97 - Reformatted to Standard. HFB |
|||
; 10 Jun 96 - Initial Test Release. HFB |
|||
;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::: |
|||
; BIOS Configuration Equates and Macros |
|||
|
|||
DATE MACRO |
|||
DEFB '17 Jan 14' ; Date of this version |
|||
ENDM |
|||
|
|||
AUTOCL MACRO |
|||
DEFB 8,'ZEX Z33 ',0 ; Autostart command line |
|||
ENDM |
|||
|
|||
;--- Basic System and Z-System Section --- |
|||
|
|||
MOVCPM EQU no ; Integrate into MOVCPM "type" loader? |
|||
IF MOVCPM |
|||
VERS EQU 13H ; Version number in BCD (Hex) (Major/Minor) |
|||
ELSE |
|||
VERS EQU 21H ; Version number w/Device Swapping permitted |
|||
ENDIF |
|||
BANKED EQU NO ; Is this a banked BIOS? |
|||
ZSDOS2 EQU NO ; Yes = Banked Dos, No = CP/M 2.2 Compatible |
|||
INROM EQU NO ; Alternate bank in ROM? |
|||
MHZ EQU 18 ; Set to Speed in MHZ (6/9/12/16/18/24) |
|||
FASTWB EQU YES ; Yes if restoring CPR from banked RAM |
|||
; ..No if restoring from Drive A |
|||
Z3 EQU YES ; Include ZCPR init code? |
|||
HAVIOP EQU NO ; Include IOP code into Jump table? |
|||
INTPXY EQU YES ; Internal HBIOS Mini Proxy |
|||
CONF_T EQU NO ; Set for Segment Configuration T |
|||
CONF_N EQU YES ; Set for Segment Configuration N |
|||
|
|||
;--- Memory configuration Section --- (Expansion Memory configured here) |
|||
|
|||
IBMOVS EQU NO ; Yes = Inter-bank Moves allowed (Z180/64180) |
|||
; No = Include Common RAM transfer buffer |
|||
|
|||
;--- Character Device Section --- |
|||
|
|||
MORDEV EQU NO ; YES = Include any extra Char Device Drivers |
|||
; NO = Only use the 4 defined Char Devices |
|||
ESCC_B EQU NO ; Include ESCC Channel B Driver? |
|||
; The following two devices result in non-standard data rates |
|||
; with the standard 16.00 MHz crystal in the P112. If a more |
|||
; "standard" crystal is used (12.288, 18.432, 24.576 MHz etc) |
|||
; is used, the ports become usable. |
|||
; Driver code for ASCI0 and ASCI1 includes an option for |
|||
; assembling Polled or Interrupt-driven buffered input. |
|||
; Select the desired option for ASCI0 with the BUFFA0 flag, |
|||
; and BUFFA1 for ASCI1. |
|||
ASCI_0 EQU false ; Include ASCI0 Driver? |
|||
BUFFA0 EQU false ; Use buffered ASCI0 Input Driver? |
|||
ASCI_1 EQU false ; Include ASCI1 Driver? |
|||
BUFFA1 EQU false ; Use buffered ASCI1 Input Driver? |
|||
|
|||
QSIZE EQU 32 ; size of interrupt typeahead buffers (if used) |
|||
; ..must be 2^n with n<8 |
|||
RTSCTS EQU no ; Include RTS/CTS code on Serial Outputs? |
|||
XONOFF EQU no ; Include Xon/Xoff handshaking in Serial lines? |
|||
|
|||
;--- Clock and Time Section --- |
|||
|
|||
CLOCK EQU YES ; Include ZSDOS Clock Driver Code? |
|||
DS1202 EQU YES ; Use Dallas DS-1202 instead of Interrupt RTC? |
|||
CLKSET EQU YES ; Allow DS-1202 Clock Sets? (Error if No) |
|||
TICTOC EQU NO ;== NOT USED IN P112 ("heartbeat" count) |
|||
|
|||
;--- Floppy Diskette Section --- |
|||
|
|||
BIOERM EQU yes ; Print BIOS error messages? |
|||
CALCSK EQU YES ; Calculate skew table? |
|||
AUTOSL EQU YES ; Auto select floppy formats? |
|||
; If AUTOSL=True, the next two are active... |
|||
FDDMA EQU no ; Use DMA Control for Floppy Drive Transfers? |
|||
FLOPYH EQU no ; Include "Hi-Density" Floppy Formats? |
|||
FLOPY8 EQU no ; Include 8" Floppy Formats? |
|||
MORDPB EQU NO ; Include additional Floppy DPB Formats? |
|||
|
|||
;--- RAM Disk Section --- |
|||
|
|||
RAMDSK EQU YES ; YES = Make RAM-Disk Code, NO = No code made |
|||
|
|||
;--- Hard Disk Section --- |
|||
|
|||
HARDDSK EQU YES ; YES = Add Hard-disk Code, NO = Floppy Only |
|||
; (Pick 1 of 3 options below) |
|||
SCSI EQU NO ; YES = Use SCSI Driver |
|||
IDE EQU NO ; YES = Use IDE Driver |
|||
HDSK EQU YES ; YES = Use SIMH HDSK Driver |
|||
HDDMA EQU NO ; Use DMA-Controlled Hard Disk Data Transfers? |
|||
; (DMA not implemented for GIDE) |
|||
UNIT_0 EQU YES ; Hard Disk Physical Unit 1 |
|||
UNIT_1 EQU YES ; Hard Disk Physical Unit 2 |
|||
UNIT_2 EQU YES ; Hard Disk Physical Unit 3 |
|||
|
|||
;--- Logical Drive Section --- |
|||
|
|||
DRV_A EQU no ; Set each of these equates for the drive and |
|||
DRV_B EQU no ; partition complement of your system. Assume |
|||
DRV_C EQU no ; that A-D are Floppies. |
|||
DRV_D EQU no |
|||
DRV_E EQU yes ; Assume that E-L and N-P are Hard Disk |
|||
DRV_F EQU yes ; Partitions |
|||
DRV_G EQU yes |
|||
DRV_H EQU yes |
|||
DRV_I EQU yes |
|||
DRV_J EQU yes |
|||
DRV_K EQU yes |
|||
DRV_L EQU yes |
|||
DRV_M EQU RAMDSK ; This is Yes for RAM drive |
|||
DRV_N EQU yes |
|||
DRV_O EQU ~RAMDSK ; Use HBIOS RAM disk if BPBIOS RAM disk is not enabled |
|||
DRV_P EQU no |
|||
|
|||
;========== Configuration Unique Equates (P112) =========== |
|||
;>>>>>>>>>>>>>>>>>>>>>>>>>>> W A R N I N G <<<<<<<<<<<<<<<<<<<<<<<<<<<<< |
|||
;>>> Do NOT Alter these unless you KNOW what you're doing <<< |
|||
;>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>><<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< |
|||
|
|||
REFRSH EQU NO ; Set to NO for only Static RAM, needed for |
|||
; systems with dynamic RAMs. |
|||
NOWAIT EQU NO ; Set to NO to use configured Wait States in |
|||
; Hard Disk Driver. Yes to eliminate Waits. |
|||
|
|||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
|||
; For Z-180/HD64180 systems, The Bank numbers should reflect Physical |
|||
; memory in 32k increments. In P112, the ROM occupies the first 32k |
|||
; increment and is ambiguously addressed occupying 0-1FFFFH. The upper |
|||
; memory bounds (BNKU, BNK3 and BNKM) should be set for your configuration. |
|||
|
|||
BNK0 EQU BID_USR ; First TPA Bank (switched in/out) 40000H |
|||
BNK1 EQU BID_HB ; Second TPA Bank (Common Bank) 48000H |
|||
BNK2 EQU BID_SYS ; System Bank (BIOS, DOS, CPR) 50000H |
|||
BNKU EQU 00H ; User Area Bank 58000H |
|||
; (set to 0 to disable) |
|||
BNK3 EQU BID_RAMD ; First Bank for RAM disk 60000H |
|||
BNKM EQU BID_RAMM ; Maximum Bank # F8000H |
|||
; With both on-board RAMs only (MEM1 or MEM2), |
|||
; the maximum Bank number is 11 (0BH). |
|||
|
|||
;=========== CPU-dependent Equates, Zilog Z-180/Hitachi HD64180 ========== |
|||
|
|||
CNTLA0 EQU 00H ; Control Port ASCI 0 |
|||
CNTLA1 EQU 01H ; Control Port ASCI 1 |
|||
STAT0 EQU 04H ; Serial port 0 Status |
|||
STAT1 EQU 05H ; Serial port 1 Status |
|||
TDR0 EQU 06H ; Serial port 0 Output Data |
|||
TDR1 EQU 07H ; Serial port 1 Output Data |
|||
RDR0 EQU 08H ; Serial port 0 Input Data |
|||
RDR1 EQU 09H ; Serial Port 1 Input Data |
|||
CNTR EQU 0AH ; HD64180 Counter port |
|||
TMDR0L EQU 0CH ; HD64180 DMA channel reg (low) |
|||
TMDR0H EQU 0DH ; HD64180 DMA channel reg (hi) |
|||
RLDR0L EQU 0EH ; CTC0 Reload Count, Low |
|||
RLDR0H EQU 0FH ; CTC0 Reload Count, High |
|||
TCR EQU 10H ; Interrupt Control Register |
|||
TMDR1L EQU 14H ; Timer Data Reg Ch1 (Low) |
|||
TMDR1H EQU 15H ; Timer Data Reg Ch1 (High) |
|||
RLDR1L EQU 16H ; Timer Reload Reg Ch1 (Low) |
|||
RLDR1H EQU 17H ; Timer Reload Reg Ch1 (High) |
|||
FRC EQU 18H ; Free-Running Counter |
|||
CCR EQU 1FH ; CPU Control Register (ZS8180/Z80182) |
|||
SAR0L EQU 20H ; DMA Channel 0 Register start (8 ports) |
|||
MAR1L EQU 28H ; DMA Channel 1 Register start (8 ports) |
|||
DSTAT EQU 30H ; DMA Status/Control port |
|||
DMODE EQU 31H ; DMA Mode Control port |
|||
DCNTL EQU 32H ; DMA/WAIT Control Register |
|||
IL EQU 33H ; Interrupt Segment Register |
|||
ITC EQU 34H ; Interrupt/Trap Control Register |
|||
RCR EQU 36H ; HD64180 Refresh Control register |
|||
CBR EQU 38H ; MMU Common Base Register |
|||
BBR EQU 39H ; MMU Bank Base Register |
|||
CBAR EQU 3AH ; MMU Common/Bank Area Register |
|||
OMCR EQU 3EH ; Operation Mode Control Reg |
|||
ICR EQU 3FH ; I/O Control Register |
|||
|
|||
; Some bit definitions used with the Z-180 on-chip peripherals: |
|||
|
|||
TDRE EQU 02H ; ACSI Transmitter Buffer Empty |
|||
RDRF EQU 80H ; ACSI Received Character available |
|||
|
|||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
|||
; Extended Features of Z80182 for P112 |
|||
|
|||
WSGCS EQU 0D8H ; Wait-State Generator CS |
|||
ENH182 EQU 0D9H ; Z80182 Enhancements Register |
|||
PINMUX EQU 0DFH ; Interrupt Edge/Pin Mux Register |
|||
RAMUBR EQU 0E6H ; RAM End Boundary |
|||
RAMLBR EQU 0E7H ; RAM Start Boundary |
|||
ROMBR EQU 0E8H ; ROM Boundary |
|||
FIFOCTL EQU 0E9H ; FIFO Control Register |
|||
RTOTC EQU 0EAH ; RX Time-Out Time Constant |
|||
TTOTC EQU 0EBH ; TX Time-Out Time Constant |
|||
FCR EQU 0ECH ; FIFO Register |
|||
SCR EQU 0EFH ; System Pin Control |
|||
RBR EQU 0F0H ; MIMIC RX Buffer Register (R) |
|||
THR EQU 0F0H ; MIMIN TX Holding Register (W) |
|||
IER EQU 0F1H ; Interrupt Enable Register |
|||
LCR EQU 0F3H ; Line Control Register |
|||
MCR EQU 0F4H ; Modem Control Register |
|||
LSR EQU 0F5H ; Line Status Register |
|||
MDMSR EQU 0F6H ; Modem Status Register |
|||
MSCR EQU 0F7H ; MIMIC Scratch Register |
|||
DLATL EQU 0F8H ; Divisor Latch (Low) |
|||
DLATM EQU 0F9H ; Divisor Latch (High) |
|||
TTCR EQU 0FAH ; TX Time Constant |
|||
RTCR EQU 0FBH ; RX Time Constant |
|||
IVEC EQU 0FCH ; MIMIC Interrupt Vector |
|||
MIMIE EQU 0FDH ; MIMIC Interrupt Enable Register |
|||
IUSIP EQU 0FEH ; MIMIC Interrupt Under-Service Register |
|||
MMCR EQU 0FFH ; MIMIC Master Control Register |
|||
|
|||
; Z80182 PIO Registers |
|||
|
|||
DDRA EQU 0EDH ; Data Direction Register A |
|||
DRA EQU 0EEH ; Port A Data |
|||
DDRB EQU 0E4H ; Data Direction Register B |
|||
DRB EQU 0E5H ; Data B Data |
|||
DDRC EQU 0DDH ; Data Direction Register C |
|||
DRC EQU 0DEH ; Data C Data |
|||
|
|||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
|||
; ESCC Registers on Z80182 |
|||
|
|||
SCCACNT EQU 0E0H ; ESCC Control Channel A |
|||
SCCAD EQU 0E1H ; ESCC Data Channel A |
|||
SCCBCNT EQU 0E2H ; ESCC Control Channel B |
|||
SCCBD EQU 0E3H ; ESCC Data Channel B |
|||
|
|||
; [E]SCC Internal Register Definitions |
|||
|
|||
RR0 EQU 00H |
|||
RR1 EQU 01H |
|||
RR2 EQU 02H |
|||
RR3 EQU 03H |
|||
RR6 EQU 06H |
|||
RR7 EQU 07H |
|||
RR10 EQU 0AH |
|||
RR12 EQU 0CH |
|||
RR13 EQU 0DH |
|||
RR15 EQU 0FH |
|||
|
|||
WR0 EQU 00H |
|||
WR1 EQU 01H |
|||
WR2 EQU 02H |
|||
WR3 EQU 03H |
|||
WR4 EQU 04H |
|||
WR5 EQU 05H |
|||
WR6 EQU 06H |
|||
WR7 EQU 07H |
|||
WR9 EQU 09H |
|||
WR10 EQU 0AH |
|||
WR11 EQU 0BH |
|||
WR12 EQU 0CH |
|||
WR13 EQU 0DH |
|||
WR14 EQU 0EH |
|||
WR15 EQU 0FH |
|||
|
|||
; FDC37C665/6 Parallel Port in Standard AT Mode |
|||
|
|||
DPORT EQU 8CH ; Data Port |
|||
SPORT EQU 8DH ; Status Port |
|||
CPORT EQU 8EH ; Control Port |
|||
|
|||
; FDC37C665/6 Configuration Control (access internal registers) |
|||
|
|||
CFCNTL EQU 90H ; Configuration control port |
|||
CFDATA EQU 91H ; Configuration data port |
|||
|
|||
; FDC37C665/6 Floppy Controller on P112 (Intel 80277 compatible) |
|||
|
|||
DCR EQU 92H ; Drive Control Register (Digital Output) |
|||
MSR EQU 94H ; Main Status Register |
|||
DR EQU 95H ; Data/Command Register |
|||
DRR EQU 97H ; Data Rate Register/Disk Changed Bit in B7 |
|||
|
|||
_DMA EQU 0A0H ; Diskette DMA Address |
|||
|
|||
; FDC37C665/6 Serial Port (National 16550 compatible) |
|||
|
|||
_RBR EQU 68H ;R Receiver Buffer |
|||
_THR EQU 68H ;W Transmit Holding Reg |
|||
_IER EQU 69H ;RW Interrupt-Enable Reg |
|||
_IIR EQU 6AH ;R Interrupt Ident. Reg |
|||
_FCR EQU 6AH ;W FIFO Control Reg |
|||
_LCR EQU 6BH ;RW Line Control Reg |
|||
_MCR EQU 6CH ;RW Modem Control Reg |
|||
_LSR EQU 6DH ;RW Line Status Reg |
|||
_MMSR EQU 6EH ;RW Modem Status Reg |
|||
_SCR EQU 6FH ;N/A Scratch Reg. (not avail in XT) |
|||
_DDL EQU 68H ;RW Divisor LSB | wih DLAB |
|||
_DLM EQU 69H ;RW Divisor MSB | set High |
|||
|
|||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
|||
; Equates for the National DP8490/NCR 5380 Prototype SCSI controller |
|||
|
|||
IF HARDDSK |
|||
NCR EQU 40H ; Base of NCR 5380 |
|||
|
|||
; 5380 Chip Registers |
|||
|
|||
NCRDAT EQU NCR ; Current SCSI Data (Read) |
|||
; Output Data Register (Write) |
|||
NCRCMD EQU NCR+1 ; Initiator Command Register (Read/Write) |
|||
NCRMOD EQU NCR+2 ; Mode Register (Read/Write) |
|||
NCRTGT EQU NCR+3 ; Target Command Register (Read/Write) |
|||
NCRBUS EQU NCR+4 ; Current SCSI Bus Status (Read) |
|||
NCRST EQU NCR+5 ; Bus & Status Register (Read) |
|||
; Start DMA Send (Write) |
|||
NCRINT EQU NCR+7 ; Reset Parity/Interrupt (Read) |
|||
; Start DMA Initiator Receive (Write) |
|||
DMAACK EQU NCR+8 ; SCSI Dack IO Port (Read/Write) |
|||
|
|||
; Bit Assignments for NCR 5380 Ports as indicated |
|||
|
|||
B_ARST EQU 10000000B ; Assert *RST (NCRCMD) |
|||
B_AACK EQU 00010000B ; Assert *ACK (NCRCMD) |
|||
B_ASEL EQU 00000100B ; Assert *SEL (NCRCMD) |
|||
B_ABUS EQU 00000001B ; Assert *Data Bus (NCRCMD) |
|||
|
|||
B_BSY EQU 01000000B ; *Busy (NCRBUS) |
|||
B_REQ EQU 00100000B ; *Request (NCRBUS) |
|||
B_MSG EQU 00010000B ; *Message (NCRBUS) |
|||
B_CD EQU 00001000B ; *Command/Data (NCRBUS) |
|||
B_IO EQU 00000100B ; *I/O (NCRBUS) |
|||
B_SEL EQU 00000010B ; *Select (NCRBUS) |
|||
|
|||
B_PHAS EQU 00001000B ; Phase Match (NCRST) |
|||
B_BBSY EQU 00000100B ; Bus Busy (NCRST) |
|||
|
|||
B_MBSY EQU 00000100B ; Monitor Busy Flag (NCRMOD) |
|||
B_DMA EQU 00000010B ; DMA Mode of transfer (NCRMOD) |
|||
ENDIF ;harddsk |
|||
|
|||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
|||
; Equates reflecting GIDE Base address from Address Jumpers (if GIDE added) |
|||
; Set the base GIDE equate to the jumper setting on the GIDE board. |
|||
|
|||
IF IDE |
|||
GIDE EQU 50H ; Set base of 16 byte address range |
|||
|
|||
IDEDOR EQU GIDE+6 ; Digital Output Register |
|||
IDEDat EQU GIDE+8 ; IDE Data Register (16-bit wide) |
|||
IDEErr EQU GIDE+9 ; IDE Error Register |
|||
IDESCnt EQU GIDE+0AH ; IDE Sector Count Register |
|||
IDESNum EQU GIDE+0BH ; IDE Sector Number Register |
|||
IDECLo EQU GIDE+0CH ; IDE Cylinder Number (Low) |
|||
IDECHi EQU GIDE+0DH ; IDE Cylinter Number (High) |
|||
IDESDH EQU GIDE+0EH ; IDE S-Drive-Head Register |
|||
IDECmd EQU GIDE+0FH ; IDE Command/Status Register |
|||
|
|||
CMDHOM EQU 10H ; Home Drive Heads |
|||
CMDRD EQU 20H ; Read Sector Command (w/retry) |
|||
CMDWR EQU 30H ; Write Sector Command (w/retry) |
|||
CMDVER EQU 40H ; Verify Sector(s) Command (w/retry) |
|||
CMDFMT EQU 50H ; Format Track Command |
|||
CMDDIAG EQU 90H ; Execute Diagnostics Command |
|||
CMDINIT EQU 91H ; Initialize Drive Params Command |
|||
CMDPW0 EQU 0E0H ; Low Range of Power Control Commands |
|||
CMDPW3 EQU 0E3H ; High Range of Power Control Commands |
|||
CMDPWQ EQU 0E5H ; Power Status Query Command |
|||
CMDID EQU 0ECH ; Read Drive Ident Data Command |
|||
ENDIF ;ide |
|||
;=================== End Unique Equates ======================= |
|||
|
|||
@ -0,0 +1,373 @@ |
|||
;:::::::::::::::::::::::::::::::::::::::::::::::********************** |
|||
; B/P BIOS Configuration and Equate File. ** System Dependant ** |
|||
; - D-X Designs Pty Ltd P112 CPU Board - ********************** |
|||
; Tailor your system here. |
|||
; |
|||
; 30 Aug 01 - Cleaned up for GPL release. HFB |
|||
; 11 May 97 - Added GIDE and adjusted HD equates. HFB |
|||
; 5 Jan 97 - Reformatted to Standard. HFB |
|||
; 10 Jun 96 - Initial Test Release. HFB |
|||
;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::: |
|||
; BIOS Configuration Equates and Macros |
|||
|
|||
DATE MACRO |
|||
DEFB '17 Jan 14' ; Date of this version |
|||
ENDM |
|||
|
|||
AUTOCL MACRO |
|||
DEFB 8,'ZEX Z33 ',0 ; Autostart command line |
|||
ENDM |
|||
|
|||
;--- Basic System and Z-System Section --- |
|||
|
|||
MOVCPM EQU no ; Integrate into MOVCPM "type" loader? |
|||
IF MOVCPM |
|||
VERS EQU 13H ; Version number in BCD (Hex) (Major/Minor) |
|||
ELSE |
|||
VERS EQU 21H ; Version number w/Device Swapping permitted |
|||
ENDIF |
|||
BANKED EQU YES ; Is this a banked BIOS? |
|||
ZSDOS2 EQU NO ; Yes = Banked Dos, No = CP/M 2.2 Compatible |
|||
INROM EQU NO ; Alternate bank in ROM? |
|||
MHZ EQU 18 ; Set to Speed in MHZ (6/9/12/16/18/24) |
|||
FASTWB EQU YES ; Yes if restoring CPR from banked RAM |
|||
; ..No if restoring from Drive A |
|||
Z3 EQU YES ; Include ZCPR init code? |
|||
HAVIOP EQU NO ; Include IOP code into Jump table? |
|||
INTPXY EQU YES ; Internal HBIOS Mini Proxy |
|||
CONF_T EQU NO ; Set for Segment Configuration T |
|||
CONF_N EQU YES ; Set for Segment Configuration N |
|||
|
|||
;--- Memory configuration Section --- (Expansion Memory configured here) |
|||
|
|||
IBMOVS EQU NO ; Yes = Inter-bank Moves allowed (Z180/64180) |
|||
; No = Include Common RAM transfer buffer |
|||
|
|||
;--- Character Device Section --- |
|||
|
|||
MORDEV EQU NO ; YES = Include any extra Char Device Drivers |
|||
; NO = Only use the 4 defined Char Devices |
|||
ESCC_B EQU no ; Include ESCC Channel B Driver? |
|||
; The following two devices result in non-standard data rates |
|||
; with the standard 16.00 MHz crystal in the P112. If a more |
|||
; "standard" crystal is used (12.288, 18.432, 24.576 MHz etc) |
|||
; is used, the ports become usable. |
|||
; Driver code for ASCI0 and ASCI1 includes an option for |
|||
; assembling Polled or Interrupt-driven buffered input. |
|||
; Select the desired option for ASCI0 with the BUFFA0 flag, |
|||
; and BUFFA1 for ASCI1. |
|||
ASCI_0 EQU false ; Include ASCI0 Driver? |
|||
BUFFA0 EQU false ; Use buffered ASCI0 Input Driver? |
|||
ASCI_1 EQU false ; Include ASCI1 Driver? |
|||
BUFFA1 EQU false ; Use buffered ASCI1 Input Driver? |
|||
|
|||
QSIZE EQU 32 ; size of interrupt typeahead buffers (if used) |
|||
; ..must be 2^n with n<8 |
|||
RTSCTS EQU no ; Include RTS/CTS code on Serial Outputs? |
|||
XONOFF EQU no ; Include Xon/Xoff handshaking in Serial lines? |
|||
|
|||
;--- Clock and Time Section --- |
|||
|
|||
CLOCK EQU YES ; Include ZSDOS Clock Driver Code? |
|||
DS1202 EQU YES ; Use Dallas DS-1202 instead of Interrupt RTC? |
|||
CLKSET EQU YES ; Allow DS-1202 Clock Sets? (Error if No) |
|||
TICTOC EQU NO ;== NOT USED IN P112 ("heartbeat" count) |
|||
|
|||
;--- Floppy Diskette Section --- |
|||
|
|||
BIOERM EQU yes ; Print BIOS error messages? |
|||
CALCSK EQU YES ; Calculate skew table? |
|||
AUTOSL EQU YES ; Auto select floppy formats? |
|||
; If AUTOSL=True, the next two are active... |
|||
FDDMA EQU no ; Use DMA Control for Floppy Drive Transfers? |
|||
FLOPYH EQU no ; Include "Hi-Density" Floppy Formats? |
|||
FLOPY8 EQU no ; Include 8" Floppy Formats? |
|||
MORDPB EQU NO ; Include additional Floppy DPB Formats? |
|||
|
|||
;--- RAM Disk Section --- |
|||
|
|||
RAMDSK EQU YES ; YES = Make RAM-Disk Code, NO = No code made |
|||
|
|||
;--- Hard Disk Section --- |
|||
|
|||
HARDDSK EQU YES ; YES = Add Hard-disk Code, NO = Floppy Only |
|||
; (Pick 1 of 3 options below) |
|||
SCSI EQU NO ; YES = Use SCSI Driver |
|||
IDE EQU NO ; YES = Use IDE Driver |
|||
HDSK EQU YES ; YES = Use SIMH HDSK Driver |
|||
HDDMA EQU NO ; Use DMA-Controlled Hard Disk Data Transfers? |
|||
; (DMA not implemented for GIDE) |
|||
UNIT_0 EQU YES ; Hard Disk Physical Unit 1 |
|||
UNIT_1 EQU YES ; Hard Disk Physical Unit 2 |
|||
UNIT_2 EQU YES ; Hard Disk Physical Unit 3 |
|||
|
|||
;--- Logical Drive Section --- |
|||
|
|||
DRV_A EQU no ; Set each of these equates for the drive and |
|||
DRV_B EQU no ; partition complement of your system. Assume |
|||
DRV_C EQU no ; that A-D are Floppies. |
|||
DRV_D EQU no |
|||
DRV_E EQU yes ; Assume that E-L and N-P are Hard Disk |
|||
DRV_F EQU yes ; Partitions |
|||
DRV_G EQU yes |
|||
DRV_H EQU yes |
|||
DRV_I EQU yes |
|||
DRV_J EQU yes |
|||
DRV_K EQU yes |
|||
DRV_L EQU yes |
|||
DRV_M EQU RAMDSK ; This is Yes for RAM drive |
|||
DRV_N EQU yes |
|||
DRV_O EQU ~RAMDSK ; Use HBIOS RAM disk if BPBIOS RAM disk is not enabled |
|||
DRV_P EQU no |
|||
|
|||
;========== Configuration Unique Equates (P112) =========== |
|||
;>>>>>>>>>>>>>>>>>>>>>>>>>>> W A R N I N G <<<<<<<<<<<<<<<<<<<<<<<<<<<<< |
|||
;>>> Do NOT Alter these unless you KNOW what you're doing <<< |
|||
;>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>><<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< |
|||
|
|||
REFRSH EQU NO ; Set to NO for only Static RAM, needed for |
|||
; systems with dynamic RAMs. |
|||
NOWAIT EQU NO ; Set to NO to use configured Wait States in |
|||
; Hard Disk Driver. Yes to eliminate Waits. |
|||
|
|||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
|||
; For Z-180/HD64180 systems, The Bank numbers should reflect Physical |
|||
; memory in 32k increments. In P112, the ROM occupies the first 32k |
|||
; increment and is ambiguously addressed occupying 0-1FFFFH. The upper |
|||
; memory bounds (BNKU, BNK3 and BNKM) should be set for your configuration. |
|||
|
|||
BNK0 EQU BID_USR ; First TPA Bank (switched in/out) 40000H |
|||
BNK1 EQU BID_HB ; Second TPA Bank (Common Bank) 48000H |
|||
BNK2 EQU BID_SYS ; System Bank (BIOS, DOS, CPR) 50000H |
|||
BNKU EQU 00H ; User Area Bank 58000H |
|||
; (set to 0 to disable) |
|||
BNK3 EQU BID_RAMD ; First Bank for RAM disk 60000H |
|||
BNKM EQU BID_RAMM ; Maximum Bank # F8000H |
|||
; With both on-board RAMs only (MEM1 or MEM2), |
|||
; the maximum Bank number is 11 (0BH). |
|||
|
|||
;=========== CPU-dependent Equates, Zilog Z-180/Hitachi HD64180 ========== |
|||
|
|||
CNTLA0 EQU 00H ; Control Port ASCI 0 |
|||
CNTLA1 EQU 01H ; Control Port ASCI 1 |
|||
STAT0 EQU 04H ; Serial port 0 Status |
|||
STAT1 EQU 05H ; Serial port 1 Status |
|||
TDR0 EQU 06H ; Serial port 0 Output Data |
|||
TDR1 EQU 07H ; Serial port 1 Output Data |
|||
RDR0 EQU 08H ; Serial port 0 Input Data |
|||
RDR1 EQU 09H ; Serial Port 1 Input Data |
|||
CNTR EQU 0AH ; HD64180 Counter port |
|||
TMDR0L EQU 0CH ; HD64180 DMA channel reg (low) |
|||
TMDR0H EQU 0DH ; HD64180 DMA channel reg (hi) |
|||
RLDR0L EQU 0EH ; CTC0 Reload Count, Low |
|||
RLDR0H EQU 0FH ; CTC0 Reload Count, High |
|||
TCR EQU 10H ; Interrupt Control Register |
|||
TMDR1L EQU 14H ; Timer Data Reg Ch1 (Low) |
|||
TMDR1H EQU 15H ; Timer Data Reg Ch1 (High) |
|||
RLDR1L EQU 16H ; Timer Reload Reg Ch1 (Low) |
|||
RLDR1H EQU 17H ; Timer Reload Reg Ch1 (High) |
|||
FRC EQU 18H ; Free-Running Counter |
|||
CCR EQU 1FH ; CPU Control Register (ZS8180/Z80182) |
|||
SAR0L EQU 20H ; DMA Channel 0 Register start (8 ports) |
|||
MAR1L EQU 28H ; DMA Channel 1 Register start (8 ports) |
|||
DSTAT EQU 30H ; DMA Status/Control port |
|||
DMODE EQU 31H ; DMA Mode Control port |
|||
DCNTL EQU 32H ; DMA/WAIT Control Register |
|||
IL EQU 33H ; Interrupt Segment Register |
|||
ITC EQU 34H ; Interrupt/Trap Control Register |
|||
RCR EQU 36H ; HD64180 Refresh Control register |
|||
CBR EQU 38H ; MMU Common Base Register |
|||
BBR EQU 39H ; MMU Bank Base Register |
|||
CBAR EQU 3AH ; MMU Common/Bank Area Register |
|||
OMCR EQU 3EH ; Operation Mode Control Reg |
|||
ICR EQU 3FH ; I/O Control Register |
|||
|
|||
; Some bit definitions used with the Z-180 on-chip peripherals: |
|||
|
|||
TDRE EQU 02H ; ACSI Transmitter Buffer Empty |
|||
RDRF EQU 80H ; ACSI Received Character available |
|||
|
|||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
|||
; Extended Features of Z80182 for P112 |
|||
|
|||
WSGCS EQU 0D8H ; Wait-State Generator CS |
|||
ENH182 EQU 0D9H ; Z80182 Enhancements Register |
|||
PINMUX EQU 0DFH ; Interrupt Edge/Pin Mux Register |
|||
RAMUBR EQU 0E6H ; RAM End Boundary |
|||
RAMLBR EQU 0E7H ; RAM Start Boundary |
|||
ROMBR EQU 0E8H ; ROM Boundary |
|||
FIFOCTL EQU 0E9H ; FIFO Control Register |
|||
RTOTC EQU 0EAH ; RX Time-Out Time Constant |
|||
TTOTC EQU 0EBH ; TX Time-Out Time Constant |
|||
FCR EQU 0ECH ; FIFO Register |
|||
SCR EQU 0EFH ; System Pin Control |
|||
RBR EQU 0F0H ; MIMIC RX Buffer Register (R) |
|||
THR EQU 0F0H ; MIMIN TX Holding Register (W) |
|||
IER EQU 0F1H ; Interrupt Enable Register |
|||
LCR EQU 0F3H ; Line Control Register |
|||
MCR EQU 0F4H ; Modem Control Register |
|||
LSR EQU 0F5H ; Line Status Register |
|||
MDMSR EQU 0F6H ; Modem Status Register |
|||
MSCR EQU 0F7H ; MIMIC Scratch Register |
|||
DLATL EQU 0F8H ; Divisor Latch (Low) |
|||
DLATM EQU 0F9H ; Divisor Latch (High) |
|||
TTCR EQU 0FAH ; TX Time Constant |
|||
RTCR EQU 0FBH ; RX Time Constant |
|||
IVEC EQU 0FCH ; MIMIC Interrupt Vector |
|||
MIMIE EQU 0FDH ; MIMIC Interrupt Enable Register |
|||
IUSIP EQU 0FEH ; MIMIC Interrupt Under-Service Register |
|||
MMCR EQU 0FFH ; MIMIC Master Control Register |
|||
|
|||
; Z80182 PIO Registers |
|||
|
|||
DDRA EQU 0EDH ; Data Direction Register A |
|||
DRA EQU 0EEH ; Port A Data |
|||
DDRB EQU 0E4H ; Data Direction Register B |
|||
DRB EQU 0E5H ; Data B Data |
|||
DDRC EQU 0DDH ; Data Direction Register C |
|||
DRC EQU 0DEH ; Data C Data |
|||
|
|||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
|||
; ESCC Registers on Z80182 |
|||
|
|||
SCCACNT EQU 0E0H ; ESCC Control Channel A |
|||
SCCAD EQU 0E1H ; ESCC Data Channel A |
|||
SCCBCNT EQU 0E2H ; ESCC Control Channel B |
|||
SCCBD EQU 0E3H ; ESCC Data Channel B |
|||
|
|||
; [E]SCC Internal Register Definitions |
|||
|
|||
RR0 EQU 00H |
|||
RR1 EQU 01H |
|||
RR2 EQU 02H |
|||
RR3 EQU 03H |
|||
RR6 EQU 06H |
|||
RR7 EQU 07H |
|||
RR10 EQU 0AH |
|||
RR12 EQU 0CH |
|||
RR13 EQU 0DH |
|||
RR15 EQU 0FH |
|||
|
|||
WR0 EQU 00H |
|||
WR1 EQU 01H |
|||
WR2 EQU 02H |
|||
WR3 EQU 03H |
|||
WR4 EQU 04H |
|||
WR5 EQU 05H |
|||
WR6 EQU 06H |
|||
WR7 EQU 07H |
|||
WR9 EQU 09H |
|||
WR10 EQU 0AH |
|||
WR11 EQU 0BH |
|||
WR12 EQU 0CH |
|||
WR13 EQU 0DH |
|||
WR14 EQU 0EH |
|||
WR15 EQU 0FH |
|||
|
|||
; FDC37C665/6 Parallel Port in Standard AT Mode |
|||
|
|||
DPORT EQU 8CH ; Data Port |
|||
SPORT EQU 8DH ; Status Port |
|||
CPORT EQU 8EH ; Control Port |
|||
|
|||
; FDC37C665/6 Configuration Control (access internal registers) |
|||
|
|||
CFCNTL EQU 90H ; Configuration control port |
|||
CFDATA EQU 91H ; Configuration data port |
|||
|
|||
; FDC37C665/6 Floppy Controller on P112 (Intel 80277 compatible) |
|||
|
|||
DCR EQU 92H ; Drive Control Register (Digital Output) |
|||
MSR EQU 94H ; Main Status Register |
|||
DR EQU 95H ; Data/Command Register |
|||
DRR EQU 97H ; Data Rate Register/Disk Changed Bit in B7 |
|||
|
|||
_DMA EQU 0A0H ; Diskette DMA Address |
|||
|
|||
; FDC37C665/6 Serial Port (National 16550 compatible) |
|||
|
|||
_RBR EQU 68H ;R Receiver Buffer |
|||
_THR EQU 68H ;W Transmit Holding Reg |
|||
_IER EQU 69H ;RW Interrupt-Enable Reg |
|||
_IIR EQU 6AH ;R Interrupt Ident. Reg |
|||
_FCR EQU 6AH ;W FIFO Control Reg |
|||
_LCR EQU 6BH ;RW Line Control Reg |
|||
_MCR EQU 6CH ;RW Modem Control Reg |
|||
_LSR EQU 6DH ;RW Line Status Reg |
|||
_MMSR EQU 6EH ;RW Modem Status Reg |
|||
_SCR EQU 6FH ;N/A Scratch Reg. (not avail in XT) |
|||
_DDL EQU 68H ;RW Divisor LSB | wih DLAB |
|||
_DLM EQU 69H ;RW Divisor MSB | set High |
|||
|
|||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
|||
; Equates for the National DP8490/NCR 5380 Prototype SCSI controller |
|||
|
|||
IF HARDDSK |
|||
NCR EQU 40H ; Base of NCR 5380 |
|||
|
|||
; 5380 Chip Registers |
|||
|
|||
NCRDAT EQU NCR ; Current SCSI Data (Read) |
|||
; Output Data Register (Write) |
|||
NCRCMD EQU NCR+1 ; Initiator Command Register (Read/Write) |
|||
NCRMOD EQU NCR+2 ; Mode Register (Read/Write) |
|||
NCRTGT EQU NCR+3 ; Target Command Register (Read/Write) |
|||
NCRBUS EQU NCR+4 ; Current SCSI Bus Status (Read) |
|||
NCRST EQU NCR+5 ; Bus & Status Register (Read) |
|||
; Start DMA Send (Write) |
|||
NCRINT EQU NCR+7 ; Reset Parity/Interrupt (Read) |
|||
; Start DMA Initiator Receive (Write) |
|||
DMAACK EQU NCR+8 ; SCSI Dack IO Port (Read/Write) |
|||
|
|||
; Bit Assignments for NCR 5380 Ports as indicated |
|||
|
|||
B_ARST EQU 10000000B ; Assert *RST (NCRCMD) |
|||
B_AACK EQU 00010000B ; Assert *ACK (NCRCMD) |
|||
B_ASEL EQU 00000100B ; Assert *SEL (NCRCMD) |
|||
B_ABUS EQU 00000001B ; Assert *Data Bus (NCRCMD) |
|||
|
|||
B_BSY EQU 01000000B ; *Busy (NCRBUS) |
|||
B_REQ EQU 00100000B ; *Request (NCRBUS) |
|||
B_MSG EQU 00010000B ; *Message (NCRBUS) |
|||
B_CD EQU 00001000B ; *Command/Data (NCRBUS) |
|||
B_IO EQU 00000100B ; *I/O (NCRBUS) |
|||
B_SEL EQU 00000010B ; *Select (NCRBUS) |
|||
|
|||
B_PHAS EQU 00001000B ; Phase Match (NCRST) |
|||
B_BBSY EQU 00000100B ; Bus Busy (NCRST) |
|||
|
|||
B_MBSY EQU 00000100B ; Monitor Busy Flag (NCRMOD) |
|||
B_DMA EQU 00000010B ; DMA Mode of transfer (NCRMOD) |
|||
ENDIF ;harddsk |
|||
|
|||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
|||
; Equates reflecting GIDE Base address from Address Jumpers (if GIDE added) |
|||
; Set the base GIDE equate to the jumper setting on the GIDE board. |
|||
|
|||
IF IDE |
|||
GIDE EQU 50H ; Set base of 16 byte address range |
|||
|
|||
IDEDOR EQU GIDE+6 ; Digital Output Register |
|||
IDEDat EQU GIDE+8 ; IDE Data Register (16-bit wide) |
|||
IDEErr EQU GIDE+9 ; IDE Error Register |
|||
IDESCnt EQU GIDE+0AH ; IDE Sector Count Register |
|||
IDESNum EQU GIDE+0BH ; IDE Sector Number Register |
|||
IDECLo EQU GIDE+0CH ; IDE Cylinder Number (Low) |
|||
IDECHi EQU GIDE+0DH ; IDE Cylinter Number (High) |
|||
IDESDH EQU GIDE+0EH ; IDE S-Drive-Head Register |
|||
IDECmd EQU GIDE+0FH ; IDE Command/Status Register |
|||
|
|||
CMDHOM EQU 10H ; Home Drive Heads |
|||
CMDRD EQU 20H ; Read Sector Command (w/retry) |
|||
CMDWR EQU 30H ; Write Sector Command (w/retry) |
|||
CMDVER EQU 40H ; Verify Sector(s) Command (w/retry) |
|||
CMDFMT EQU 50H ; Format Track Command |
|||
CMDDIAG EQU 90H ; Execute Diagnostics Command |
|||
CMDINIT EQU 91H ; Initialize Drive Params Command |
|||
CMDPW0 EQU 0E0H ; Low Range of Power Control Commands |
|||
CMDPW3 EQU 0E3H ; High Range of Power Control Commands |
|||
CMDPWQ EQU 0E5H ; Power Status Query Command |
|||
CMDID EQU 0ECH ; Read Drive Ident Data Command |
|||
ENDIF ;ide |
|||
;=================== End Unique Equates ======================= |
|||
|
|||
@ -0,0 +1,373 @@ |
|||
;:::::::::::::::::::::::::::::::::::::::::::::::********************** |
|||
; B/P BIOS Configuration and Equate File. ** System Dependant ** |
|||
; - D-X Designs Pty Ltd P112 CPU Board - ********************** |
|||
; Tailor your system here. |
|||
; |
|||
; 30 Aug 01 - Cleaned up for GPL release. HFB |
|||
; 11 May 97 - Added GIDE and adjusted HD equates. HFB |
|||
; 5 Jan 97 - Reformatted to Standard. HFB |
|||
; 10 Jun 96 - Initial Test Release. HFB |
|||
;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::: |
|||
; BIOS Configuration Equates and Macros |
|||
|
|||
DATE MACRO |
|||
DEFB '17 Jan 14' ; Date of this version |
|||
ENDM |
|||
|
|||
AUTOCL MACRO |
|||
DEFB 8,'ZEX Z34 ',0 ; Autostart command line |
|||
ENDM |
|||
|
|||
;--- Basic System and Z-System Section --- |
|||
|
|||
MOVCPM EQU no ; Integrate into MOVCPM "type" loader? |
|||
IF MOVCPM |
|||
VERS EQU 13H ; Version number in BCD (Hex) (Major/Minor) |
|||
ELSE |
|||
VERS EQU 21H ; Version number w/Device Swapping permitted |
|||
ENDIF |
|||
BANKED EQU NO ; Is this a banked BIOS? |
|||
ZSDOS2 EQU NO ; Yes = Banked Dos, No = CP/M 2.2 Compatible |
|||
INROM EQU NO ; Alternate bank in ROM? |
|||
MHZ EQU 18 ; Set to Speed in MHZ (6/9/12/16/18/24) |
|||
FASTWB EQU YES ; Yes if restoring CPR from banked RAM |
|||
; ..No if restoring from Drive A |
|||
Z3 EQU YES ; Include ZCPR init code? |
|||
HAVIOP EQU NO ; Include IOP code into Jump table? |
|||
INTPXY EQU YES ; Internal HBIOS Mini Proxy |
|||
CONF_T EQU NO ; Set for Segment Configuration T |
|||
CONF_N EQU YES ; Set for Segment Configuration N |
|||
|
|||
;--- Memory configuration Section --- (Expansion Memory configured here) |
|||
|
|||
IBMOVS EQU NO ; Yes = Inter-bank Moves allowed (Z180/64180) |
|||
; No = Include Common RAM transfer buffer |
|||
|
|||
;--- Character Device Section --- |
|||
|
|||
MORDEV EQU NO ; YES = Include any extra Char Device Drivers |
|||
; NO = Only use the 4 defined Char Devices |
|||
ESCC_B EQU no ; Include ESCC Channel B Driver? |
|||
; The following two devices result in non-standard data rates |
|||
; with the standard 16.00 MHz crystal in the P112. If a more |
|||
; "standard" crystal is used (12.288, 18.432, 24.576 MHz etc) |
|||
; is used, the ports become usable. |
|||
; Driver code for ASCI0 and ASCI1 includes an option for |
|||
; assembling Polled or Interrupt-driven buffered input. |
|||
; Select the desired option for ASCI0 with the BUFFA0 flag, |
|||
; and BUFFA1 for ASCI1. |
|||
ASCI_0 EQU false ; Include ASCI0 Driver? |
|||
BUFFA0 EQU false ; Use buffered ASCI0 Input Driver? |
|||
ASCI_1 EQU false ; Include ASCI1 Driver? |
|||
BUFFA1 EQU false ; Use buffered ASCI1 Input Driver? |
|||
|
|||
QSIZE EQU 32 ; size of interrupt typeahead buffers (if used) |
|||
; ..must be 2^n with n<8 |
|||
RTSCTS EQU no ; Include RTS/CTS code on Serial Outputs? |
|||
XONOFF EQU no ; Include Xon/Xoff handshaking in Serial lines? |
|||
|
|||
;--- Clock and Time Section --- |
|||
|
|||
CLOCK EQU YES ; Include ZSDOS Clock Driver Code? |
|||
DS1202 EQU YES ; Use Dallas DS-1202 instead of Interrupt RTC? |
|||
CLKSET EQU YES ; Allow DS-1202 Clock Sets? (Error if No) |
|||
TICTOC EQU NO ;== NOT USED IN P112 ("heartbeat" count) |
|||
|
|||
;--- Floppy Diskette Section --- |
|||
|
|||
BIOERM EQU yes ; Print BIOS error messages? |
|||
CALCSK EQU YES ; Calculate skew table? |
|||
AUTOSL EQU YES ; Auto select floppy formats? |
|||
; If AUTOSL=True, the next two are active... |
|||
FDDMA EQU no ; Use DMA Control for Floppy Drive Transfers? |
|||
FLOPYH EQU no ; Include "Hi-Density" Floppy Formats? |
|||
FLOPY8 EQU no ; Include 8" Floppy Formats? |
|||
MORDPB EQU NO ; Include additional Floppy DPB Formats? |
|||
|
|||
;--- RAM Disk Section --- |
|||
|
|||
RAMDSK EQU YES ; YES = Make RAM-Disk Code, NO = No code made |
|||
|
|||
;--- Hard Disk Section --- |
|||
|
|||
HARDDSK EQU YES ; YES = Add Hard-disk Code, NO = Floppy Only |
|||
; (Pick 1 of 3 options below) |
|||
SCSI EQU NO ; YES = Use SCSI Driver |
|||
IDE EQU NO ; YES = Use IDE Driver |
|||
HDSK EQU YES ; YES = Use SIMH HDSK Driver |
|||
HDDMA EQU NO ; Use DMA-Controlled Hard Disk Data Transfers? |
|||
; (DMA not implemented for GIDE) |
|||
UNIT_0 EQU YES ; Hard Disk Physical Unit 1 |
|||
UNIT_1 EQU YES ; Hard Disk Physical Unit 2 |
|||
UNIT_2 EQU YES ; Hard Disk Physical Unit 3 |
|||
|
|||
;--- Logical Drive Section --- |
|||
|
|||
DRV_A EQU no ; Set each of these equates for the drive and |
|||
DRV_B EQU no ; partition complement of your system. Assume |
|||
DRV_C EQU no ; that A-D are Floppies. |
|||
DRV_D EQU no |
|||
DRV_E EQU yes ; Assume that E-L and N-P are Hard Disk |
|||
DRV_F EQU yes ; Partitions |
|||
DRV_G EQU yes |
|||
DRV_H EQU yes |
|||
DRV_I EQU yes |
|||
DRV_J EQU yes |
|||
DRV_K EQU yes |
|||
DRV_L EQU yes |
|||
DRV_M EQU RAMDSK ; This is Yes for RAM drive |
|||
DRV_N EQU yes |
|||
DRV_O EQU ~RAMDSK ; Use HBIOS RAM disk if BPBIOS RAM disk is not enabled |
|||
DRV_P EQU no |
|||
|
|||
;========== Configuration Unique Equates (P112) =========== |
|||
;>>>>>>>>>>>>>>>>>>>>>>>>>>> W A R N I N G <<<<<<<<<<<<<<<<<<<<<<<<<<<<< |
|||
;>>> Do NOT Alter these unless you KNOW what you're doing <<< |
|||
;>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>><<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< |
|||
|
|||
REFRSH EQU NO ; Set to NO for only Static RAM, needed for |
|||
; systems with dynamic RAMs. |
|||
NOWAIT EQU NO ; Set to NO to use configured Wait States in |
|||
; Hard Disk Driver. Yes to eliminate Waits. |
|||
|
|||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
|||
; For Z-180/HD64180 systems, The Bank numbers should reflect Physical |
|||
; memory in 32k increments. In P112, the ROM occupies the first 32k |
|||
; increment and is ambiguously addressed occupying 0-1FFFFH. The upper |
|||
; memory bounds (BNKU, BNK3 and BNKM) should be set for your configuration. |
|||
|
|||
BNK0 EQU BID_USR ; First TPA Bank (switched in/out) 40000H |
|||
BNK1 EQU BID_HB ; Second TPA Bank (Common Bank) 48000H |
|||
BNK2 EQU BID_SYS ; System Bank (BIOS, DOS, CPR) 50000H |
|||
BNKU EQU 00H ; User Area Bank 58000H |
|||
; (set to 0 to disable) |
|||
BNK3 EQU BID_RAMD ; First Bank for RAM disk 60000H |
|||
BNKM EQU BID_RAMM ; Maximum Bank # F8000H |
|||
; With both on-board RAMs only (MEM1 or MEM2), |
|||
; the maximum Bank number is 11 (0BH). |
|||
|
|||
;=========== CPU-dependent Equates, Zilog Z-180/Hitachi HD64180 ========== |
|||
|
|||
CNTLA0 EQU 00H ; Control Port ASCI 0 |
|||
CNTLA1 EQU 01H ; Control Port ASCI 1 |
|||
STAT0 EQU 04H ; Serial port 0 Status |
|||
STAT1 EQU 05H ; Serial port 1 Status |
|||
TDR0 EQU 06H ; Serial port 0 Output Data |
|||
TDR1 EQU 07H ; Serial port 1 Output Data |
|||
RDR0 EQU 08H ; Serial port 0 Input Data |
|||
RDR1 EQU 09H ; Serial Port 1 Input Data |
|||
CNTR EQU 0AH ; HD64180 Counter port |
|||
TMDR0L EQU 0CH ; HD64180 DMA channel reg (low) |
|||
TMDR0H EQU 0DH ; HD64180 DMA channel reg (hi) |
|||
RLDR0L EQU 0EH ; CTC0 Reload Count, Low |
|||
RLDR0H EQU 0FH ; CTC0 Reload Count, High |
|||
TCR EQU 10H ; Interrupt Control Register |
|||
TMDR1L EQU 14H ; Timer Data Reg Ch1 (Low) |
|||
TMDR1H EQU 15H ; Timer Data Reg Ch1 (High) |
|||
RLDR1L EQU 16H ; Timer Reload Reg Ch1 (Low) |
|||
RLDR1H EQU 17H ; Timer Reload Reg Ch1 (High) |
|||
FRC EQU 18H ; Free-Running Counter |
|||
CCR EQU 1FH ; CPU Control Register (ZS8180/Z80182) |
|||
SAR0L EQU 20H ; DMA Channel 0 Register start (8 ports) |
|||
MAR1L EQU 28H ; DMA Channel 1 Register start (8 ports) |
|||
DSTAT EQU 30H ; DMA Status/Control port |
|||
DMODE EQU 31H ; DMA Mode Control port |
|||
DCNTL EQU 32H ; DMA/WAIT Control Register |
|||
IL EQU 33H ; Interrupt Segment Register |
|||
ITC EQU 34H ; Interrupt/Trap Control Register |
|||
RCR EQU 36H ; HD64180 Refresh Control register |
|||
CBR EQU 38H ; MMU Common Base Register |
|||
BBR EQU 39H ; MMU Bank Base Register |
|||
CBAR EQU 3AH ; MMU Common/Bank Area Register |
|||
OMCR EQU 3EH ; Operation Mode Control Reg |
|||
ICR EQU 3FH ; I/O Control Register |
|||
|
|||
; Some bit definitions used with the Z-180 on-chip peripherals: |
|||
|
|||
TDRE EQU 02H ; ACSI Transmitter Buffer Empty |
|||
RDRF EQU 80H ; ACSI Received Character available |
|||
|
|||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
|||
; Extended Features of Z80182 for P112 |
|||
|
|||
WSGCS EQU 0D8H ; Wait-State Generator CS |
|||
ENH182 EQU 0D9H ; Z80182 Enhancements Register |
|||
PINMUX EQU 0DFH ; Interrupt Edge/Pin Mux Register |
|||
RAMUBR EQU 0E6H ; RAM End Boundary |
|||
RAMLBR EQU 0E7H ; RAM Start Boundary |
|||
ROMBR EQU 0E8H ; ROM Boundary |
|||
FIFOCTL EQU 0E9H ; FIFO Control Register |
|||
RTOTC EQU 0EAH ; RX Time-Out Time Constant |
|||
TTOTC EQU 0EBH ; TX Time-Out Time Constant |
|||
FCR EQU 0ECH ; FIFO Register |
|||
SCR EQU 0EFH ; System Pin Control |
|||
RBR EQU 0F0H ; MIMIC RX Buffer Register (R) |
|||
THR EQU 0F0H ; MIMIN TX Holding Register (W) |
|||
IER EQU 0F1H ; Interrupt Enable Register |
|||
LCR EQU 0F3H ; Line Control Register |
|||
MCR EQU 0F4H ; Modem Control Register |
|||
LSR EQU 0F5H ; Line Status Register |
|||
MDMSR EQU 0F6H ; Modem Status Register |
|||
MSCR EQU 0F7H ; MIMIC Scratch Register |
|||
DLATL EQU 0F8H ; Divisor Latch (Low) |
|||
DLATM EQU 0F9H ; Divisor Latch (High) |
|||
TTCR EQU 0FAH ; TX Time Constant |
|||
RTCR EQU 0FBH ; RX Time Constant |
|||
IVEC EQU 0FCH ; MIMIC Interrupt Vector |
|||
MIMIE EQU 0FDH ; MIMIC Interrupt Enable Register |
|||
IUSIP EQU 0FEH ; MIMIC Interrupt Under-Service Register |
|||
MMCR EQU 0FFH ; MIMIC Master Control Register |
|||
|
|||
; Z80182 PIO Registers |
|||
|
|||
DDRA EQU 0EDH ; Data Direction Register A |
|||
DRA EQU 0EEH ; Port A Data |
|||
DDRB EQU 0E4H ; Data Direction Register B |
|||
DRB EQU 0E5H ; Data B Data |
|||
DDRC EQU 0DDH ; Data Direction Register C |
|||
DRC EQU 0DEH ; Data C Data |
|||
|
|||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
|||
; ESCC Registers on Z80182 |
|||
|
|||
SCCACNT EQU 0E0H ; ESCC Control Channel A |
|||
SCCAD EQU 0E1H ; ESCC Data Channel A |
|||
SCCBCNT EQU 0E2H ; ESCC Control Channel B |
|||
SCCBD EQU 0E3H ; ESCC Data Channel B |
|||
|
|||
; [E]SCC Internal Register Definitions |
|||
|
|||
RR0 EQU 00H |
|||
RR1 EQU 01H |
|||
RR2 EQU 02H |
|||
RR3 EQU 03H |
|||
RR6 EQU 06H |
|||
RR7 EQU 07H |
|||
RR10 EQU 0AH |
|||
RR12 EQU 0CH |
|||
RR13 EQU 0DH |
|||
RR15 EQU 0FH |
|||
|
|||
WR0 EQU 00H |
|||
WR1 EQU 01H |
|||
WR2 EQU 02H |
|||
WR3 EQU 03H |
|||
WR4 EQU 04H |
|||
WR5 EQU 05H |
|||
WR6 EQU 06H |
|||
WR7 EQU 07H |
|||
WR9 EQU 09H |
|||
WR10 EQU 0AH |
|||
WR11 EQU 0BH |
|||
WR12 EQU 0CH |
|||
WR13 EQU 0DH |
|||
WR14 EQU 0EH |
|||
WR15 EQU 0FH |
|||
|
|||
; FDC37C665/6 Parallel Port in Standard AT Mode |
|||
|
|||
DPORT EQU 8CH ; Data Port |
|||
SPORT EQU 8DH ; Status Port |
|||
CPORT EQU 8EH ; Control Port |
|||
|
|||
; FDC37C665/6 Configuration Control (access internal registers) |
|||
|
|||
CFCNTL EQU 90H ; Configuration control port |
|||
CFDATA EQU 91H ; Configuration data port |
|||
|
|||
; FDC37C665/6 Floppy Controller on P112 (Intel 80277 compatible) |
|||
|
|||
DCR EQU 92H ; Drive Control Register (Digital Output) |
|||
MSR EQU 94H ; Main Status Register |
|||
DR EQU 95H ; Data/Command Register |
|||
DRR EQU 97H ; Data Rate Register/Disk Changed Bit in B7 |
|||
|
|||
_DMA EQU 0A0H ; Diskette DMA Address |
|||
|
|||
; FDC37C665/6 Serial Port (National 16550 compatible) |
|||
|
|||
_RBR EQU 68H ;R Receiver Buffer |
|||
_THR EQU 68H ;W Transmit Holding Reg |
|||
_IER EQU 69H ;RW Interrupt-Enable Reg |
|||
_IIR EQU 6AH ;R Interrupt Ident. Reg |
|||
_FCR EQU 6AH ;W FIFO Control Reg |
|||
_LCR EQU 6BH ;RW Line Control Reg |
|||
_MCR EQU 6CH ;RW Modem Control Reg |
|||
_LSR EQU 6DH ;RW Line Status Reg |
|||
_MMSR EQU 6EH ;RW Modem Status Reg |
|||
_SCR EQU 6FH ;N/A Scratch Reg. (not avail in XT) |
|||
_DDL EQU 68H ;RW Divisor LSB | wih DLAB |
|||
_DLM EQU 69H ;RW Divisor MSB | set High |
|||
|
|||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
|||
; Equates for the National DP8490/NCR 5380 Prototype SCSI controller |
|||
|
|||
IF HARDDSK |
|||
NCR EQU 40H ; Base of NCR 5380 |
|||
|
|||
; 5380 Chip Registers |
|||
|
|||
NCRDAT EQU NCR ; Current SCSI Data (Read) |
|||
; Output Data Register (Write) |
|||
NCRCMD EQU NCR+1 ; Initiator Command Register (Read/Write) |
|||
NCRMOD EQU NCR+2 ; Mode Register (Read/Write) |
|||
NCRTGT EQU NCR+3 ; Target Command Register (Read/Write) |
|||
NCRBUS EQU NCR+4 ; Current SCSI Bus Status (Read) |
|||
NCRST EQU NCR+5 ; Bus & Status Register (Read) |
|||
; Start DMA Send (Write) |
|||
NCRINT EQU NCR+7 ; Reset Parity/Interrupt (Read) |
|||
; Start DMA Initiator Receive (Write) |
|||
DMAACK EQU NCR+8 ; SCSI Dack IO Port (Read/Write) |
|||
|
|||
; Bit Assignments for NCR 5380 Ports as indicated |
|||
|
|||
B_ARST EQU 10000000B ; Assert *RST (NCRCMD) |
|||
B_AACK EQU 00010000B ; Assert *ACK (NCRCMD) |
|||
B_ASEL EQU 00000100B ; Assert *SEL (NCRCMD) |
|||
B_ABUS EQU 00000001B ; Assert *Data Bus (NCRCMD) |
|||
|
|||
B_BSY EQU 01000000B ; *Busy (NCRBUS) |
|||
B_REQ EQU 00100000B ; *Request (NCRBUS) |
|||
B_MSG EQU 00010000B ; *Message (NCRBUS) |
|||
B_CD EQU 00001000B ; *Command/Data (NCRBUS) |
|||
B_IO EQU 00000100B ; *I/O (NCRBUS) |
|||
B_SEL EQU 00000010B ; *Select (NCRBUS) |
|||
|
|||
B_PHAS EQU 00001000B ; Phase Match (NCRST) |
|||
B_BBSY EQU 00000100B ; Bus Busy (NCRST) |
|||
|
|||
B_MBSY EQU 00000100B ; Monitor Busy Flag (NCRMOD) |
|||
B_DMA EQU 00000010B ; DMA Mode of transfer (NCRMOD) |
|||
ENDIF ;harddsk |
|||
|
|||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
|||
; Equates reflecting GIDE Base address from Address Jumpers (if GIDE added) |
|||
; Set the base GIDE equate to the jumper setting on the GIDE board. |
|||
|
|||
IF IDE |
|||
GIDE EQU 50H ; Set base of 16 byte address range |
|||
|
|||
IDEDOR EQU GIDE+6 ; Digital Output Register |
|||
IDEDat EQU GIDE+8 ; IDE Data Register (16-bit wide) |
|||
IDEErr EQU GIDE+9 ; IDE Error Register |
|||
IDESCnt EQU GIDE+0AH ; IDE Sector Count Register |
|||
IDESNum EQU GIDE+0BH ; IDE Sector Number Register |
|||
IDECLo EQU GIDE+0CH ; IDE Cylinder Number (Low) |
|||
IDECHi EQU GIDE+0DH ; IDE Cylinter Number (High) |
|||
IDESDH EQU GIDE+0EH ; IDE S-Drive-Head Register |
|||
IDECmd EQU GIDE+0FH ; IDE Command/Status Register |
|||
|
|||
CMDHOM EQU 10H ; Home Drive Heads |
|||
CMDRD EQU 20H ; Read Sector Command (w/retry) |
|||
CMDWR EQU 30H ; Write Sector Command (w/retry) |
|||
CMDVER EQU 40H ; Verify Sector(s) Command (w/retry) |
|||
CMDFMT EQU 50H ; Format Track Command |
|||
CMDDIAG EQU 90H ; Execute Diagnostics Command |
|||
CMDINIT EQU 91H ; Initialize Drive Params Command |
|||
CMDPW0 EQU 0E0H ; Low Range of Power Control Commands |
|||
CMDPW3 EQU 0E3H ; High Range of Power Control Commands |
|||
CMDPWQ EQU 0E5H ; Power Status Query Command |
|||
CMDID EQU 0ECH ; Read Drive Ident Data Command |
|||
ENDIF ;ide |
|||
;=================== End Unique Equates ======================= |
|||
|
|||
@ -0,0 +1,373 @@ |
|||
;:::::::::::::::::::::::::::::::::::::::::::::::********************** |
|||
; B/P BIOS Configuration and Equate File. ** System Dependant ** |
|||
; - D-X Designs Pty Ltd P112 CPU Board - ********************** |
|||
; Tailor your system here. |
|||
; |
|||
; 30 Aug 01 - Cleaned up for GPL release. HFB |
|||
; 11 May 97 - Added GIDE and adjusted HD equates. HFB |
|||
; 5 Jan 97 - Reformatted to Standard. HFB |
|||
; 10 Jun 96 - Initial Test Release. HFB |
|||
;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::: |
|||
; BIOS Configuration Equates and Macros |
|||
|
|||
DATE MACRO |
|||
DEFB '17 Jan 14' ; Date of this version |
|||
ENDM |
|||
|
|||
AUTOCL MACRO |
|||
DEFB 8,'ZEX Z34 ',0 ; Autostart command line |
|||
ENDM |
|||
|
|||
;--- Basic System and Z-System Section --- |
|||
|
|||
MOVCPM EQU no ; Integrate into MOVCPM "type" loader? |
|||
IF MOVCPM |
|||
VERS EQU 13H ; Version number in BCD (Hex) (Major/Minor) |
|||
ELSE |
|||
VERS EQU 21H ; Version number w/Device Swapping permitted |
|||
ENDIF |
|||
BANKED EQU YES ; Is this a banked BIOS? |
|||
ZSDOS2 EQU NO ; Yes = Banked Dos, No = CP/M 2.2 Compatible |
|||
INROM EQU NO ; Alternate bank in ROM? |
|||
MHZ EQU 18 ; Set to Speed in MHZ (6/9/12/16/18/24) |
|||
FASTWB EQU YES ; Yes if restoring CPR from banked RAM |
|||
; ..No if restoring from Drive A |
|||
Z3 EQU YES ; Include ZCPR init code? |
|||
HAVIOP EQU NO ; Include IOP code into Jump table? |
|||
INTPXY EQU YES ; Internal HBIOS Mini Proxy |
|||
CONF_T EQU NO ; Set for Segment Configuration T |
|||
CONF_N EQU YES ; Set for Segment Configuration N |
|||
|
|||
;--- Memory configuration Section --- (Expansion Memory configured here) |
|||
|
|||
IBMOVS EQU NO ; Yes = Inter-bank Moves allowed (Z180/64180) |
|||
; No = Include Common RAM transfer buffer |
|||
|
|||
;--- Character Device Section --- |
|||
|
|||
MORDEV EQU NO ; YES = Include any extra Char Device Drivers |
|||
; NO = Only use the 4 defined Char Devices |
|||
ESCC_B EQU no ; Include ESCC Channel B Driver? |
|||
; The following two devices result in non-standard data rates |
|||
; with the standard 16.00 MHz crystal in the P112. If a more |
|||
; "standard" crystal is used (12.288, 18.432, 24.576 MHz etc) |
|||
; is used, the ports become usable. |
|||
; Driver code for ASCI0 and ASCI1 includes an option for |
|||
; assembling Polled or Interrupt-driven buffered input. |
|||
; Select the desired option for ASCI0 with the BUFFA0 flag, |
|||
; and BUFFA1 for ASCI1. |
|||
ASCI_0 EQU false ; Include ASCI0 Driver? |
|||
BUFFA0 EQU false ; Use buffered ASCI0 Input Driver? |
|||
ASCI_1 EQU false ; Include ASCI1 Driver? |
|||
BUFFA1 EQU false ; Use buffered ASCI1 Input Driver? |
|||
|
|||
QSIZE EQU 32 ; size of interrupt typeahead buffers (if used) |
|||
; ..must be 2^n with n<8 |
|||
RTSCTS EQU no ; Include RTS/CTS code on Serial Outputs? |
|||
XONOFF EQU no ; Include Xon/Xoff handshaking in Serial lines? |
|||
|
|||
;--- Clock and Time Section --- |
|||
|
|||
CLOCK EQU YES ; Include ZSDOS Clock Driver Code? |
|||
DS1202 EQU YES ; Use Dallas DS-1202 instead of Interrupt RTC? |
|||
CLKSET EQU YES ; Allow DS-1202 Clock Sets? (Error if No) |
|||
TICTOC EQU NO ;== NOT USED IN P112 ("heartbeat" count) |
|||
|
|||
;--- Floppy Diskette Section --- |
|||
|
|||
BIOERM EQU yes ; Print BIOS error messages? |
|||
CALCSK EQU YES ; Calculate skew table? |
|||
AUTOSL EQU YES ; Auto select floppy formats? |
|||
; If AUTOSL=True, the next two are active... |
|||
FDDMA EQU no ; Use DMA Control for Floppy Drive Transfers? |
|||
FLOPYH EQU no ; Include "Hi-Density" Floppy Formats? |
|||
FLOPY8 EQU no ; Include 8" Floppy Formats? |
|||
MORDPB EQU NO ; Include additional Floppy DPB Formats? |
|||
|
|||
;--- RAM Disk Section --- |
|||
|
|||
RAMDSK EQU YES ; YES = Make RAM-Disk Code, NO = No code made |
|||
|
|||
;--- Hard Disk Section --- |
|||
|
|||
HARDDSK EQU YES ; YES = Add Hard-disk Code, NO = Floppy Only |
|||
; (Pick 1 of 3 options below) |
|||
SCSI EQU NO ; YES = Use SCSI Driver |
|||
IDE EQU NO ; YES = Use IDE Driver |
|||
HDSK EQU YES ; YES = Use SIMH HDSK Driver |
|||
HDDMA EQU NO ; Use DMA-Controlled Hard Disk Data Transfers? |
|||
; (DMA not implemented for GIDE) |
|||
UNIT_0 EQU YES ; Hard Disk Physical Unit 1 |
|||
UNIT_1 EQU YES ; Hard Disk Physical Unit 2 |
|||
UNIT_2 EQU YES ; Hard Disk Physical Unit 3 |
|||
|
|||
;--- Logical Drive Section --- |
|||
|
|||
DRV_A EQU no ; Set each of these equates for the drive and |
|||
DRV_B EQU no ; partition complement of your system. Assume |
|||
DRV_C EQU no ; that A-D are Floppies. |
|||
DRV_D EQU no |
|||
DRV_E EQU yes ; Assume that E-L and N-P are Hard Disk |
|||
DRV_F EQU yes ; Partitions |
|||
DRV_G EQU yes |
|||
DRV_H EQU yes |
|||
DRV_I EQU yes |
|||
DRV_J EQU yes |
|||
DRV_K EQU yes |
|||
DRV_L EQU yes |
|||
DRV_M EQU RAMDSK ; This is Yes for RAM drive |
|||
DRV_N EQU yes |
|||
DRV_O EQU ~RAMDSK ; Use HBIOS RAM disk if BPBIOS RAM disk is not enabled |
|||
DRV_P EQU no |
|||
|
|||
;========== Configuration Unique Equates (P112) =========== |
|||
;>>>>>>>>>>>>>>>>>>>>>>>>>>> W A R N I N G <<<<<<<<<<<<<<<<<<<<<<<<<<<<< |
|||
;>>> Do NOT Alter these unless you KNOW what you're doing <<< |
|||
;>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>><<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< |
|||
|
|||
REFRSH EQU NO ; Set to NO for only Static RAM, needed for |
|||
; systems with dynamic RAMs. |
|||
NOWAIT EQU NO ; Set to NO to use configured Wait States in |
|||
; Hard Disk Driver. Yes to eliminate Waits. |
|||
|
|||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
|||
; For Z-180/HD64180 systems, The Bank numbers should reflect Physical |
|||
; memory in 32k increments. In P112, the ROM occupies the first 32k |
|||
; increment and is ambiguously addressed occupying 0-1FFFFH. The upper |
|||
; memory bounds (BNKU, BNK3 and BNKM) should be set for your configuration. |
|||
|
|||
BNK0 EQU BID_USR ; First TPA Bank (switched in/out) 40000H |
|||
BNK1 EQU BID_HB ; Second TPA Bank (Common Bank) 48000H |
|||
BNK2 EQU BID_SYS ; System Bank (BIOS, DOS, CPR) 50000H |
|||
BNKU EQU 00H ; User Area Bank 58000H |
|||
; (set to 0 to disable) |
|||
BNK3 EQU BID_RAMD ; First Bank for RAM disk 60000H |
|||
BNKM EQU BID_RAMM ; Maximum Bank # F8000H |
|||
; With both on-board RAMs only (MEM1 or MEM2), |
|||
; the maximum Bank number is 11 (0BH). |
|||
|
|||
;=========== CPU-dependent Equates, Zilog Z-180/Hitachi HD64180 ========== |
|||
|
|||
CNTLA0 EQU 00H ; Control Port ASCI 0 |
|||
CNTLA1 EQU 01H ; Control Port ASCI 1 |
|||
STAT0 EQU 04H ; Serial port 0 Status |
|||
STAT1 EQU 05H ; Serial port 1 Status |
|||
TDR0 EQU 06H ; Serial port 0 Output Data |
|||
TDR1 EQU 07H ; Serial port 1 Output Data |
|||
RDR0 EQU 08H ; Serial port 0 Input Data |
|||
RDR1 EQU 09H ; Serial Port 1 Input Data |
|||
CNTR EQU 0AH ; HD64180 Counter port |
|||
TMDR0L EQU 0CH ; HD64180 DMA channel reg (low) |
|||
TMDR0H EQU 0DH ; HD64180 DMA channel reg (hi) |
|||
RLDR0L EQU 0EH ; CTC0 Reload Count, Low |
|||
RLDR0H EQU 0FH ; CTC0 Reload Count, High |
|||
TCR EQU 10H ; Interrupt Control Register |
|||
TMDR1L EQU 14H ; Timer Data Reg Ch1 (Low) |
|||
TMDR1H EQU 15H ; Timer Data Reg Ch1 (High) |
|||
RLDR1L EQU 16H ; Timer Reload Reg Ch1 (Low) |
|||
RLDR1H EQU 17H ; Timer Reload Reg Ch1 (High) |
|||
FRC EQU 18H ; Free-Running Counter |
|||
CCR EQU 1FH ; CPU Control Register (ZS8180/Z80182) |
|||
SAR0L EQU 20H ; DMA Channel 0 Register start (8 ports) |
|||
MAR1L EQU 28H ; DMA Channel 1 Register start (8 ports) |
|||
DSTAT EQU 30H ; DMA Status/Control port |
|||
DMODE EQU 31H ; DMA Mode Control port |
|||
DCNTL EQU 32H ; DMA/WAIT Control Register |
|||
IL EQU 33H ; Interrupt Segment Register |
|||
ITC EQU 34H ; Interrupt/Trap Control Register |
|||
RCR EQU 36H ; HD64180 Refresh Control register |
|||
CBR EQU 38H ; MMU Common Base Register |
|||
BBR EQU 39H ; MMU Bank Base Register |
|||
CBAR EQU 3AH ; MMU Common/Bank Area Register |
|||
OMCR EQU 3EH ; Operation Mode Control Reg |
|||
ICR EQU 3FH ; I/O Control Register |
|||
|
|||
; Some bit definitions used with the Z-180 on-chip peripherals: |
|||
|
|||
TDRE EQU 02H ; ACSI Transmitter Buffer Empty |
|||
RDRF EQU 80H ; ACSI Received Character available |
|||
|
|||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
|||
; Extended Features of Z80182 for P112 |
|||
|
|||
WSGCS EQU 0D8H ; Wait-State Generator CS |
|||
ENH182 EQU 0D9H ; Z80182 Enhancements Register |
|||
PINMUX EQU 0DFH ; Interrupt Edge/Pin Mux Register |
|||
RAMUBR EQU 0E6H ; RAM End Boundary |
|||
RAMLBR EQU 0E7H ; RAM Start Boundary |
|||
ROMBR EQU 0E8H ; ROM Boundary |
|||
FIFOCTL EQU 0E9H ; FIFO Control Register |
|||
RTOTC EQU 0EAH ; RX Time-Out Time Constant |
|||
TTOTC EQU 0EBH ; TX Time-Out Time Constant |
|||
FCR EQU 0ECH ; FIFO Register |
|||
SCR EQU 0EFH ; System Pin Control |
|||
RBR EQU 0F0H ; MIMIC RX Buffer Register (R) |
|||
THR EQU 0F0H ; MIMIN TX Holding Register (W) |
|||
IER EQU 0F1H ; Interrupt Enable Register |
|||
LCR EQU 0F3H ; Line Control Register |
|||
MCR EQU 0F4H ; Modem Control Register |
|||
LSR EQU 0F5H ; Line Status Register |
|||
MDMSR EQU 0F6H ; Modem Status Register |
|||
MSCR EQU 0F7H ; MIMIC Scratch Register |
|||
DLATL EQU 0F8H ; Divisor Latch (Low) |
|||
DLATM EQU 0F9H ; Divisor Latch (High) |
|||
TTCR EQU 0FAH ; TX Time Constant |
|||
RTCR EQU 0FBH ; RX Time Constant |
|||
IVEC EQU 0FCH ; MIMIC Interrupt Vector |
|||
MIMIE EQU 0FDH ; MIMIC Interrupt Enable Register |
|||
IUSIP EQU 0FEH ; MIMIC Interrupt Under-Service Register |
|||
MMCR EQU 0FFH ; MIMIC Master Control Register |
|||
|
|||
; Z80182 PIO Registers |
|||
|
|||
DDRA EQU 0EDH ; Data Direction Register A |
|||
DRA EQU 0EEH ; Port A Data |
|||
DDRB EQU 0E4H ; Data Direction Register B |
|||
DRB EQU 0E5H ; Data B Data |
|||
DDRC EQU 0DDH ; Data Direction Register C |
|||
DRC EQU 0DEH ; Data C Data |
|||
|
|||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
|||
; ESCC Registers on Z80182 |
|||
|
|||
SCCACNT EQU 0E0H ; ESCC Control Channel A |
|||
SCCAD EQU 0E1H ; ESCC Data Channel A |
|||
SCCBCNT EQU 0E2H ; ESCC Control Channel B |
|||
SCCBD EQU 0E3H ; ESCC Data Channel B |
|||
|
|||
; [E]SCC Internal Register Definitions |
|||
|
|||
RR0 EQU 00H |
|||
RR1 EQU 01H |
|||
RR2 EQU 02H |
|||
RR3 EQU 03H |
|||
RR6 EQU 06H |
|||
RR7 EQU 07H |
|||
RR10 EQU 0AH |
|||
RR12 EQU 0CH |
|||
RR13 EQU 0DH |
|||
RR15 EQU 0FH |
|||
|
|||
WR0 EQU 00H |
|||
WR1 EQU 01H |
|||
WR2 EQU 02H |
|||
WR3 EQU 03H |
|||
WR4 EQU 04H |
|||
WR5 EQU 05H |
|||
WR6 EQU 06H |
|||
WR7 EQU 07H |
|||
WR9 EQU 09H |
|||
WR10 EQU 0AH |
|||
WR11 EQU 0BH |
|||
WR12 EQU 0CH |
|||
WR13 EQU 0DH |
|||
WR14 EQU 0EH |
|||
WR15 EQU 0FH |
|||
|
|||
; FDC37C665/6 Parallel Port in Standard AT Mode |
|||
|
|||
DPORT EQU 8CH ; Data Port |
|||
SPORT EQU 8DH ; Status Port |
|||
CPORT EQU 8EH ; Control Port |
|||
|
|||
; FDC37C665/6 Configuration Control (access internal registers) |
|||
|
|||
CFCNTL EQU 90H ; Configuration control port |
|||
CFDATA EQU 91H ; Configuration data port |
|||
|
|||
; FDC37C665/6 Floppy Controller on P112 (Intel 80277 compatible) |
|||
|
|||
DCR EQU 92H ; Drive Control Register (Digital Output) |
|||
MSR EQU 94H ; Main Status Register |
|||
DR EQU 95H ; Data/Command Register |
|||
DRR EQU 97H ; Data Rate Register/Disk Changed Bit in B7 |
|||
|
|||
_DMA EQU 0A0H ; Diskette DMA Address |
|||
|
|||
; FDC37C665/6 Serial Port (National 16550 compatible) |
|||
|
|||
_RBR EQU 68H ;R Receiver Buffer |
|||
_THR EQU 68H ;W Transmit Holding Reg |
|||
_IER EQU 69H ;RW Interrupt-Enable Reg |
|||
_IIR EQU 6AH ;R Interrupt Ident. Reg |
|||
_FCR EQU 6AH ;W FIFO Control Reg |
|||
_LCR EQU 6BH ;RW Line Control Reg |
|||
_MCR EQU 6CH ;RW Modem Control Reg |
|||
_LSR EQU 6DH ;RW Line Status Reg |
|||
_MMSR EQU 6EH ;RW Modem Status Reg |
|||
_SCR EQU 6FH ;N/A Scratch Reg. (not avail in XT) |
|||
_DDL EQU 68H ;RW Divisor LSB | wih DLAB |
|||
_DLM EQU 69H ;RW Divisor MSB | set High |
|||
|
|||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
|||
; Equates for the National DP8490/NCR 5380 Prototype SCSI controller |
|||
|
|||
IF HARDDSK |
|||
NCR EQU 40H ; Base of NCR 5380 |
|||
|
|||
; 5380 Chip Registers |
|||
|
|||
NCRDAT EQU NCR ; Current SCSI Data (Read) |
|||
; Output Data Register (Write) |
|||
NCRCMD EQU NCR+1 ; Initiator Command Register (Read/Write) |
|||
NCRMOD EQU NCR+2 ; Mode Register (Read/Write) |
|||
NCRTGT EQU NCR+3 ; Target Command Register (Read/Write) |
|||
NCRBUS EQU NCR+4 ; Current SCSI Bus Status (Read) |
|||
NCRST EQU NCR+5 ; Bus & Status Register (Read) |
|||
; Start DMA Send (Write) |
|||
NCRINT EQU NCR+7 ; Reset Parity/Interrupt (Read) |
|||
; Start DMA Initiator Receive (Write) |
|||
DMAACK EQU NCR+8 ; SCSI Dack IO Port (Read/Write) |
|||
|
|||
; Bit Assignments for NCR 5380 Ports as indicated |
|||
|
|||
B_ARST EQU 10000000B ; Assert *RST (NCRCMD) |
|||
B_AACK EQU 00010000B ; Assert *ACK (NCRCMD) |
|||
B_ASEL EQU 00000100B ; Assert *SEL (NCRCMD) |
|||
B_ABUS EQU 00000001B ; Assert *Data Bus (NCRCMD) |
|||
|
|||
B_BSY EQU 01000000B ; *Busy (NCRBUS) |
|||
B_REQ EQU 00100000B ; *Request (NCRBUS) |
|||
B_MSG EQU 00010000B ; *Message (NCRBUS) |
|||
B_CD EQU 00001000B ; *Command/Data (NCRBUS) |
|||
B_IO EQU 00000100B ; *I/O (NCRBUS) |
|||
B_SEL EQU 00000010B ; *Select (NCRBUS) |
|||
|
|||
B_PHAS EQU 00001000B ; Phase Match (NCRST) |
|||
B_BBSY EQU 00000100B ; Bus Busy (NCRST) |
|||
|
|||
B_MBSY EQU 00000100B ; Monitor Busy Flag (NCRMOD) |
|||
B_DMA EQU 00000010B ; DMA Mode of transfer (NCRMOD) |
|||
ENDIF ;harddsk |
|||
|
|||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
|||
; Equates reflecting GIDE Base address from Address Jumpers (if GIDE added) |
|||
; Set the base GIDE equate to the jumper setting on the GIDE board. |
|||
|
|||
IF IDE |
|||
GIDE EQU 50H ; Set base of 16 byte address range |
|||
|
|||
IDEDOR EQU GIDE+6 ; Digital Output Register |
|||
IDEDat EQU GIDE+8 ; IDE Data Register (16-bit wide) |
|||
IDEErr EQU GIDE+9 ; IDE Error Register |
|||
IDESCnt EQU GIDE+0AH ; IDE Sector Count Register |
|||
IDESNum EQU GIDE+0BH ; IDE Sector Number Register |
|||
IDECLo EQU GIDE+0CH ; IDE Cylinder Number (Low) |
|||
IDECHi EQU GIDE+0DH ; IDE Cylinter Number (High) |
|||
IDESDH EQU GIDE+0EH ; IDE S-Drive-Head Register |
|||
IDECmd EQU GIDE+0FH ; IDE Command/Status Register |
|||
|
|||
CMDHOM EQU 10H ; Home Drive Heads |
|||
CMDRD EQU 20H ; Read Sector Command (w/retry) |
|||
CMDWR EQU 30H ; Write Sector Command (w/retry) |
|||
CMDVER EQU 40H ; Verify Sector(s) Command (w/retry) |
|||
CMDFMT EQU 50H ; Format Track Command |
|||
CMDDIAG EQU 90H ; Execute Diagnostics Command |
|||
CMDINIT EQU 91H ; Initialize Drive Params Command |
|||
CMDPW0 EQU 0E0H ; Low Range of Power Control Commands |
|||
CMDPW3 EQU 0E3H ; High Range of Power Control Commands |
|||
CMDPWQ EQU 0E5H ; Power Status Query Command |
|||
CMDID EQU 0ECH ; Read Drive Ident Data Command |
|||
ENDIF ;ide |
|||
;=================== End Unique Equates ======================= |
|||
|
|||
@ -0,0 +1,372 @@ |
|||
;:::::::::::::::::::::::::::::::::::::::::::::::********************** |
|||
; B/P BIOS Configuration and Equate File. ** System Dependant ** |
|||
; - D-X Designs Pty Ltd P112 CPU Board - ********************** |
|||
; Tailor your system here. |
|||
; |
|||
; 30 Aug 01 - Cleaned up for GPL release. HFB |
|||
; 11 May 97 - Added GIDE and adjusted HD equates. HFB |
|||
; 5 Jan 97 - Reformatted to Standard. HFB |
|||
; 10 Jun 96 - Initial Test Release. HFB |
|||
;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::: |
|||
; BIOS Configuration Equates and Macros |
|||
|
|||
DATE MACRO |
|||
DEFB '17 Jan 14' ; Date of this version |
|||
ENDM |
|||
|
|||
AUTOCL MACRO |
|||
DEFB 8,'ZEX Z41 ',0 ; Autostart command line |
|||
ENDM |
|||
|
|||
;--- Basic System and Z-System Section --- |
|||
|
|||
MOVCPM EQU no ; Integrate into MOVCPM "type" loader? |
|||
IF MOVCPM |
|||
VERS EQU 13H ; Version number in BCD (Hex) (Major/Minor) |
|||
ELSE |
|||
VERS EQU 21H ; Version number w/Device Swapping permitted |
|||
ENDIF |
|||
BANKED EQU YES ; Is this a banked BIOS? |
|||
ZSDOS2 EQU YES ; Yes = Banked Dos, No = CP/M 2.2 Compatible |
|||
INROM EQU NO ; Alternate bank in ROM? |
|||
MHZ EQU 18 ; Set to Speed in MHZ (6/9/12/16/18/24) |
|||
FASTWB EQU YES ; Yes if restoring CPR from banked RAM |
|||
; ..No if restoring from Drive A |
|||
Z3 EQU YES ; Include ZCPR init code? |
|||
HAVIOP EQU NO ; Include IOP code into Jump table? |
|||
INTPXY EQU YES ; Internal HBIOS Mini Proxy |
|||
CONF_T EQU NO ; Set for Segment Configuration T |
|||
CONF_N EQU YES ; Set for Segment Configuration N |
|||
|
|||
;--- Memory configuration Section --- (Expansion Memory configured here) |
|||
|
|||
IBMOVS EQU NO ; Yes = Inter-bank Moves allowed (Z180/64180) |
|||
; No = Include Common RAM transfer buffer |
|||
;--- Character Device Section --- |
|||
|
|||
MORDEV EQU NO ; YES = Include any extra Char Device Drivers |
|||
; NO = Only use the 4 defined Char Devices |
|||
ESCC_B EQU no ; Include ESCC Channel B Driver? |
|||
; The following two devices result in non-standard data rates |
|||
; with the standard 16.00 MHz crystal in the P112. If a more |
|||
; "standard" crystal is used (12.288, 18.432, 24.576 MHz etc) |
|||
; is used, the ports become usable. |
|||
; Driver code for ASCI0 and ASCI1 includes an option for |
|||
; assembling Polled or Interrupt-driven buffered input. |
|||
; Select the desired option for ASCI0 with the BUFFA0 flag, |
|||
; and BUFFA1 for ASCI1. |
|||
ASCI_0 EQU false ; Include ASCI0 Driver? |
|||
BUFFA0 EQU false ; Use buffered ASCI0 Input Driver? |
|||
ASCI_1 EQU false ; Include ASCI1 Driver? |
|||
BUFFA1 EQU false ; Use buffered ASCI1 Input Driver? |
|||
|
|||
QSIZE EQU 32 ; size of interrupt typeahead buffers (if used) |
|||
; ..must be 2^n with n<8 |
|||
RTSCTS EQU no ; Include RTS/CTS code on Serial Outputs? |
|||
XONOFF EQU no ; Include Xon/Xoff handshaking in Serial lines? |
|||
|
|||
;--- Clock and Time Section --- |
|||
|
|||
CLOCK EQU YES ; Include ZSDOS Clock Driver Code? |
|||
DS1202 EQU YES ; Use Dallas DS-1202 instead of Interrupt RTC? |
|||
CLKSET EQU YES ; Allow DS-1202 Clock Sets? (Error if No) |
|||
TICTOC EQU NO ;== NOT USED IN P112 ("heartbeat" count) |
|||
|
|||
;--- Floppy Diskette Section --- |
|||
|
|||
BIOERM EQU yes ; Print BIOS error messages? |
|||
CALCSK EQU YES ; Calculate skew table? |
|||
AUTOSL EQU YES ; Auto select floppy formats? |
|||
; If AUTOSL=True, the next two are active... |
|||
FDDMA EQU no ; Use DMA Control for Floppy Drive Transfers? |
|||
FLOPYH EQU no ; Include "Hi-Density" Floppy Formats? |
|||
FLOPY8 EQU no ; Include 8" Floppy Formats? |
|||
MORDPB EQU NO ; Include additional Floppy DPB Formats? |
|||
|
|||
;--- RAM Disk Section --- |
|||
|
|||
RAMDSK EQU YES ; YES = Make RAM-Disk Code, NO = No code made |
|||
|
|||
;--- Hard Disk Section --- |
|||
|
|||
HARDDSK EQU YES ; YES = Add Hard-disk Code, NO = Floppy Only |
|||
; (Pick 1 of 3 options below) |
|||
SCSI EQU NO ; YES = Use SCSI Driver |
|||
IDE EQU NO ; YES = Use IDE Driver |
|||
HDSK EQU YES ; YES = Use SIMH HDSK Driver |
|||
HDDMA EQU NO ; Use DMA-Controlled Hard Disk Data Transfers? |
|||
; (DMA not implemented for GIDE) |
|||
UNIT_0 EQU YES ; Hard Disk Physical Unit 1 |
|||
UNIT_1 EQU YES ; Hard Disk Physical Unit 2 |
|||
UNIT_2 EQU YES ; Hard Disk Physical Unit 3 |
|||
|
|||
;--- Logical Drive Section --- |
|||
|
|||
DRV_A EQU no ; Set each of these equates for the drive and |
|||
DRV_B EQU no ; partition complement of your system. Assume |
|||
DRV_C EQU no ; that A-D are Floppies. |
|||
DRV_D EQU no |
|||
DRV_E EQU yes ; Assume that E-L and N-P are Hard Disk |
|||
DRV_F EQU yes ; Partitions |
|||
DRV_G EQU yes |
|||
DRV_H EQU yes |
|||
DRV_I EQU yes |
|||
DRV_J EQU yes |
|||
DRV_K EQU yes |
|||
DRV_L EQU yes |
|||
DRV_M EQU RAMDSK ; This is Yes for RAM drive |
|||
DRV_N EQU yes |
|||
DRV_O EQU ~RAMDSK ; Use HBIOS RAM disk if BPBIOS RAM disk is not enabled |
|||
DRV_P EQU no |
|||
|
|||
;========== Configuration Unique Equates (P112) =========== |
|||
;>>>>>>>>>>>>>>>>>>>>>>>>>>> W A R N I N G <<<<<<<<<<<<<<<<<<<<<<<<<<<<< |
|||
;>>> Do NOT Alter these unless you KNOW what you're doing <<< |
|||
;>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>><<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< |
|||
|
|||
REFRSH EQU NO ; Set to NO for only Static RAM, needed for |
|||
; systems with dynamic RAMs. |
|||
NOWAIT EQU NO ; Set to NO to use configured Wait States in |
|||
; Hard Disk Driver. Yes to eliminate Waits. |
|||
|
|||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
|||
; For Z-180/HD64180 systems, The Bank numbers should reflect Physical |
|||
; memory in 32k increments. In P112, the ROM occupies the first 32k |
|||
; increment and is ambiguously addressed occupying 0-1FFFFH. The upper |
|||
; memory bounds (BNKU, BNK3 and BNKM) should be set for your configuration. |
|||
|
|||
BNK0 EQU BID_USR ; First TPA Bank (switched in/out) 40000H |
|||
BNK1 EQU BID_HB ; Second TPA Bank (Common Bank) 48000H |
|||
BNK2 EQU BID_SYS ; System Bank (BIOS, DOS, CPR) 50000H |
|||
BNKU EQU 00H ; User Area Bank 58000H |
|||
; (set to 0 to disable) |
|||
BNK3 EQU BID_RAMD ; First Bank for RAM disk 60000H |
|||
BNKM EQU BID_RAMM ; Maximum Bank # F8000H |
|||
; With both on-board RAMs only (MEM1 or MEM2), |
|||
; the maximum Bank number is 11 (0BH). |
|||
|
|||
;=========== CPU-dependent Equates, Zilog Z-180/Hitachi HD64180 ========== |
|||
|
|||
CNTLA0 EQU 00H ; Control Port ASCI 0 |
|||
CNTLA1 EQU 01H ; Control Port ASCI 1 |
|||
STAT0 EQU 04H ; Serial port 0 Status |
|||
STAT1 EQU 05H ; Serial port 1 Status |
|||
TDR0 EQU 06H ; Serial port 0 Output Data |
|||
TDR1 EQU 07H ; Serial port 1 Output Data |
|||
RDR0 EQU 08H ; Serial port 0 Input Data |
|||
RDR1 EQU 09H ; Serial Port 1 Input Data |
|||
CNTR EQU 0AH ; HD64180 Counter port |
|||
TMDR0L EQU 0CH ; HD64180 DMA channel reg (low) |
|||
TMDR0H EQU 0DH ; HD64180 DMA channel reg (hi) |
|||
RLDR0L EQU 0EH ; CTC0 Reload Count, Low |
|||
RLDR0H EQU 0FH ; CTC0 Reload Count, High |
|||
TCR EQU 10H ; Interrupt Control Register |
|||
TMDR1L EQU 14H ; Timer Data Reg Ch1 (Low) |
|||
TMDR1H EQU 15H ; Timer Data Reg Ch1 (High) |
|||
RLDR1L EQU 16H ; Timer Reload Reg Ch1 (Low) |
|||
RLDR1H EQU 17H ; Timer Reload Reg Ch1 (High) |
|||
FRC EQU 18H ; Free-Running Counter |
|||
CCR EQU 1FH ; CPU Control Register (ZS8180/Z80182) |
|||
SAR0L EQU 20H ; DMA Channel 0 Register start (8 ports) |
|||
MAR1L EQU 28H ; DMA Channel 1 Register start (8 ports) |
|||
DSTAT EQU 30H ; DMA Status/Control port |
|||
DMODE EQU 31H ; DMA Mode Control port |
|||
DCNTL EQU 32H ; DMA/WAIT Control Register |
|||
IL EQU 33H ; Interrupt Segment Register |
|||
ITC EQU 34H ; Interrupt/Trap Control Register |
|||
RCR EQU 36H ; HD64180 Refresh Control register |
|||
CBR EQU 38H ; MMU Common Base Register |
|||
BBR EQU 39H ; MMU Bank Base Register |
|||
CBAR EQU 3AH ; MMU Common/Bank Area Register |
|||
OMCR EQU 3EH ; Operation Mode Control Reg |
|||
ICR EQU 3FH ; I/O Control Register |
|||
|
|||
; Some bit definitions used with the Z-180 on-chip peripherals: |
|||
|
|||
TDRE EQU 02H ; ACSI Transmitter Buffer Empty |
|||
RDRF EQU 80H ; ACSI Received Character available |
|||
|
|||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
|||
; Extended Features of Z80182 for P112 |
|||
|
|||
WSGCS EQU 0D8H ; Wait-State Generator CS |
|||
ENH182 EQU 0D9H ; Z80182 Enhancements Register |
|||
PINMUX EQU 0DFH ; Interrupt Edge/Pin Mux Register |
|||
RAMUBR EQU 0E6H ; RAM End Boundary |
|||
RAMLBR EQU 0E7H ; RAM Start Boundary |
|||
ROMBR EQU 0E8H ; ROM Boundary |
|||
FIFOCTL EQU 0E9H ; FIFO Control Register |
|||
RTOTC EQU 0EAH ; RX Time-Out Time Constant |
|||
TTOTC EQU 0EBH ; TX Time-Out Time Constant |
|||
FCR EQU 0ECH ; FIFO Register |
|||
SCR EQU 0EFH ; System Pin Control |
|||
RBR EQU 0F0H ; MIMIC RX Buffer Register (R) |
|||
THR EQU 0F0H ; MIMIN TX Holding Register (W) |
|||
IER EQU 0F1H ; Interrupt Enable Register |
|||
LCR EQU 0F3H ; Line Control Register |
|||
MCR EQU 0F4H ; Modem Control Register |
|||
LSR EQU 0F5H ; Line Status Register |
|||
MDMSR EQU 0F6H ; Modem Status Register |
|||
MSCR EQU 0F7H ; MIMIC Scratch Register |
|||
DLATL EQU 0F8H ; Divisor Latch (Low) |
|||
DLATM EQU 0F9H ; Divisor Latch (High) |
|||
TTCR EQU 0FAH ; TX Time Constant |
|||
RTCR EQU 0FBH ; RX Time Constant |
|||
IVEC EQU 0FCH ; MIMIC Interrupt Vector |
|||
MIMIE EQU 0FDH ; MIMIC Interrupt Enable Register |
|||
IUSIP EQU 0FEH ; MIMIC Interrupt Under-Service Register |
|||
MMCR EQU 0FFH ; MIMIC Master Control Register |
|||
|
|||
; Z80182 PIO Registers |
|||
|
|||
DDRA EQU 0EDH ; Data Direction Register A |
|||
DRA EQU 0EEH ; Port A Data |
|||
DDRB EQU 0E4H ; Data Direction Register B |
|||
DRB EQU 0E5H ; Data B Data |
|||
DDRC EQU 0DDH ; Data Direction Register C |
|||
DRC EQU 0DEH ; Data C Data |
|||
|
|||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
|||
; ESCC Registers on Z80182 |
|||
|
|||
SCCACNT EQU 0E0H ; ESCC Control Channel A |
|||
SCCAD EQU 0E1H ; ESCC Data Channel A |
|||
SCCBCNT EQU 0E2H ; ESCC Control Channel B |
|||
SCCBD EQU 0E3H ; ESCC Data Channel B |
|||
|
|||
; [E]SCC Internal Register Definitions |
|||
|
|||
RR0 EQU 00H |
|||
RR1 EQU 01H |
|||
RR2 EQU 02H |
|||
RR3 EQU 03H |
|||
RR6 EQU 06H |
|||
RR7 EQU 07H |
|||
RR10 EQU 0AH |
|||
RR12 EQU 0CH |
|||
RR13 EQU 0DH |
|||
RR15 EQU 0FH |
|||
|
|||
WR0 EQU 00H |
|||
WR1 EQU 01H |
|||
WR2 EQU 02H |
|||
WR3 EQU 03H |
|||
WR4 EQU 04H |
|||
WR5 EQU 05H |
|||
WR6 EQU 06H |
|||
WR7 EQU 07H |
|||
WR9 EQU 09H |
|||
WR10 EQU 0AH |
|||
WR11 EQU 0BH |
|||
WR12 EQU 0CH |
|||
WR13 EQU 0DH |
|||
WR14 EQU 0EH |
|||
WR15 EQU 0FH |
|||
|
|||
; FDC37C665/6 Parallel Port in Standard AT Mode |
|||
|
|||
DPORT EQU 8CH ; Data Port |
|||
SPORT EQU 8DH ; Status Port |
|||
CPORT EQU 8EH ; Control Port |
|||
|
|||
; FDC37C665/6 Configuration Control (access internal registers) |
|||
|
|||
CFCNTL EQU 90H ; Configuration control port |
|||
CFDATA EQU 91H ; Configuration data port |
|||
|
|||
; FDC37C665/6 Floppy Controller on P112 (Intel 80277 compatible) |
|||
|
|||
DCR EQU 92H ; Drive Control Register (Digital Output) |
|||
MSR EQU 94H ; Main Status Register |
|||
DR EQU 95H ; Data/Command Register |
|||
DRR EQU 97H ; Data Rate Register/Disk Changed Bit in B7 |
|||
|
|||
_DMA EQU 0A0H ; Diskette DMA Address |
|||
|
|||
; FDC37C665/6 Serial Port (National 16550 compatible) |
|||
|
|||
_RBR EQU 68H ;R Receiver Buffer |
|||
_THR EQU 68H ;W Transmit Holding Reg |
|||
_IER EQU 69H ;RW Interrupt-Enable Reg |
|||
_IIR EQU 6AH ;R Interrupt Ident. Reg |
|||
_FCR EQU 6AH ;W FIFO Control Reg |
|||
_LCR EQU 6BH ;RW Line Control Reg |
|||
_MCR EQU 6CH ;RW Modem Control Reg |
|||
_LSR EQU 6DH ;RW Line Status Reg |
|||
_MMSR EQU 6EH ;RW Modem Status Reg |
|||
_SCR EQU 6FH ;N/A Scratch Reg. (not avail in XT) |
|||
_DDL EQU 68H ;RW Divisor LSB | wih DLAB |
|||
_DLM EQU 69H ;RW Divisor MSB | set High |
|||
|
|||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
|||
; Equates for the National DP8490/NCR 5380 Prototype SCSI controller |
|||
|
|||
IF HARDDSK |
|||
NCR EQU 40H ; Base of NCR 5380 |
|||
|
|||
; 5380 Chip Registers |
|||
|
|||
NCRDAT EQU NCR ; Current SCSI Data (Read) |
|||
; Output Data Register (Write) |
|||
NCRCMD EQU NCR+1 ; Initiator Command Register (Read/Write) |
|||
NCRMOD EQU NCR+2 ; Mode Register (Read/Write) |
|||
NCRTGT EQU NCR+3 ; Target Command Register (Read/Write) |
|||
NCRBUS EQU NCR+4 ; Current SCSI Bus Status (Read) |
|||
NCRST EQU NCR+5 ; Bus & Status Register (Read) |
|||
; Start DMA Send (Write) |
|||
NCRINT EQU NCR+7 ; Reset Parity/Interrupt (Read) |
|||
; Start DMA Initiator Receive (Write) |
|||
DMAACK EQU NCR+8 ; SCSI Dack IO Port (Read/Write) |
|||
|
|||
; Bit Assignments for NCR 5380 Ports as indicated |
|||
|
|||
B_ARST EQU 10000000B ; Assert *RST (NCRCMD) |
|||
B_AACK EQU 00010000B ; Assert *ACK (NCRCMD) |
|||
B_ASEL EQU 00000100B ; Assert *SEL (NCRCMD) |
|||
B_ABUS EQU 00000001B ; Assert *Data Bus (NCRCMD) |
|||
|
|||
B_BSY EQU 01000000B ; *Busy (NCRBUS) |
|||
B_REQ EQU 00100000B ; *Request (NCRBUS) |
|||
B_MSG EQU 00010000B ; *Message (NCRBUS) |
|||
B_CD EQU 00001000B ; *Command/Data (NCRBUS) |
|||
B_IO EQU 00000100B ; *I/O (NCRBUS) |
|||
B_SEL EQU 00000010B ; *Select (NCRBUS) |
|||
|
|||
B_PHAS EQU 00001000B ; Phase Match (NCRST) |
|||
B_BBSY EQU 00000100B ; Bus Busy (NCRST) |
|||
|
|||
B_MBSY EQU 00000100B ; Monitor Busy Flag (NCRMOD) |
|||
B_DMA EQU 00000010B ; DMA Mode of transfer (NCRMOD) |
|||
ENDIF ;harddsk |
|||
|
|||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
|||
; Equates reflecting GIDE Base address from Address Jumpers (if GIDE added) |
|||
; Set the base GIDE equate to the jumper setting on the GIDE board. |
|||
|
|||
IF IDE |
|||
GIDE EQU 50H ; Set base of 16 byte address range |
|||
|
|||
IDEDOR EQU GIDE+6 ; Digital Output Register |
|||
IDEDat EQU GIDE+8 ; IDE Data Register (16-bit wide) |
|||
IDEErr EQU GIDE+9 ; IDE Error Register |
|||
IDESCnt EQU GIDE+0AH ; IDE Sector Count Register |
|||
IDESNum EQU GIDE+0BH ; IDE Sector Number Register |
|||
IDECLo EQU GIDE+0CH ; IDE Cylinder Number (Low) |
|||
IDECHi EQU GIDE+0DH ; IDE Cylinter Number (High) |
|||
IDESDH EQU GIDE+0EH ; IDE S-Drive-Head Register |
|||
IDECmd EQU GIDE+0FH ; IDE Command/Status Register |
|||
|
|||
CMDHOM EQU 10H ; Home Drive Heads |
|||
CMDRD EQU 20H ; Read Sector Command (w/retry) |
|||
CMDWR EQU 30H ; Write Sector Command (w/retry) |
|||
CMDVER EQU 40H ; Verify Sector(s) Command (w/retry) |
|||
CMDFMT EQU 50H ; Format Track Command |
|||
CMDDIAG EQU 90H ; Execute Diagnostics Command |
|||
CMDINIT EQU 91H ; Initialize Drive Params Command |
|||
CMDPW0 EQU 0E0H ; Low Range of Power Control Commands |
|||
CMDPW3 EQU 0E3H ; High Range of Power Control Commands |
|||
CMDPWQ EQU 0E5H ; Power Status Query Command |
|||
CMDID EQU 0ECH ; Read Drive Ident Data Command |
|||
ENDIF ;ide |
|||
;=================== End Unique Equates ======================= |
|||
|
|||
@ -0,0 +1,128 @@ |
|||
; B/P Bios System Z3 Definition File. |
|||
|
|||
; This file is adapted from the basic Z3BASE.LIB configuration file used for |
|||
; most ZCPR33 systems. It has added the new definitions for the Resident |
|||
; User Space defined in B/P Bios descriptions. |
|||
;========================================================================= |
|||
;== NOTE: The Starting Address of the User Space marks the lower == |
|||
;== base of memory and MUST be entered. B/P Bios Utilities use == |
|||
;== this address to locate many portions of the operating system. == |
|||
;========================================================================= |
|||
; To change your systems definition, first sketch out the memory map in the |
|||
; comment table, then set the equates to reflect the memory map, doing any |
|||
; required calculations for element sizes and required spaces. As an |
|||
; alternative, just leave this file alone and configure everything with |
|||
; the utilities provided. |
|||
|
|||
; FFE0 - FFFF 32 Bytes HBIOS Reserved |
|||
; FFB0 - FFDF 48 Bytes ZCPR3 External Stack |
|||
; FF00 - FFAF 176 Bytes Multiple Command Line Buffer |
|||
; FE00 - FEFF 256 Bytes Environment Descriptor |
|||
; Bytes 00H-7FH: Z3 Parameters |
|||
; Bytes 80H-FFH: Z3 TCAP |
|||
; FDFF 1 Byte Wheel byte |
|||
; FDF4 - FDFE 11 Bytes Path (5 elements) |
|||
; FDD0 - FDF3 36 Bytes ZCPR3 External FCB |
|||
; FD80 - FDCF 80 Bytes ZCPR3 Message Buffers |
|||
; FD00 - FD7F 128 Bytes ZCPR3 Shell Stack |
|||
; FC00 - FCFF 256 Bytes Named Directory Buffer |
|||
; FA00 - FBFF 512 Bytes Flow Command Package |
|||
; F200 - F9FF 2.0 KBytes Resident Command Package |
|||
; EC00 - F1FF 1.5 KBytes IO Package |
|||
; E900 - EBFF .75 KBytes Resident User Space |
|||
|
|||
; The remainder is for the Operating System. Exact sizes vary depending |
|||
; primarily on the Number and sizes of Hard Drive Partitions, but may be: |
|||
|
|||
; D100 - EBFF 5.0 KBytes B/P BIOS (unbanked version) |
|||
; C300 - D0FF 3.5 KBytes ZSDOS 1.0 BDOS |
|||
; BB00 - C2FF 2 KBytes ZCPR 3.3 Command Processor |
|||
; 0100 - BAFF ~46 KBytes Transient Program Area |
|||
; 0000 - 00FF 256 Bytes Standard CP/M Buffers |
|||
;======================================================================== |
|||
|
|||
FALSE EQU 0 |
|||
TRUE EQU NOT FALSE |
|||
|
|||
YES EQU TRUE |
|||
NO EQU FALSE |
|||
|
|||
; The External Stack is placed in the very top position in memory. It is |
|||
; mandatory for B/P Bios and ZCPR 3.3. |
|||
|
|||
;EXTSTK EQU 0FFD0H ; ZCPR3 External Stack |
|||
EXTSTK EQU 0FFB0H ; ZCPR3 External Stack |
|||
EXTSTKS EQU YES |
|||
|
|||
; The Multiple Command Line Buffer is placed in the Top Page of Memory to |
|||
; place it above the Environment. It is mandatory for ZCPR 3.3. |
|||
|
|||
Z3CL EQU 0FF00H ; ZCPR3 Command Line Buffer |
|||
;Z3CLS EQU 208-5 ; Size of Command Line Buffer-5 |
|||
Z3CLS EQU 176-5 ; Size of Command Line Buffer-5 |
|||
|
|||
; The ZCPR3 External Environment Descriptor is mandatory B/P Bios & ZCPR 3.3. |
|||
; The Environment Descriptor MUST begin on an even Page Boundary (xx00H). |
|||
|
|||
Z3ENV EQU 0FE00H ; Environment Descriptors |
|||
Z3ENVS EQU 2 ; Size of Env Descriptor in 128-Byte Blks |
|||
|
|||
; The ZCPR3 Wheel Byte is mandatory for ZCPR 3.3. |
|||
|
|||
Z3WHL EQU 0FDFFH ; Wheel Byte Address |
|||
Z3WHLS EQU YES |
|||
|
|||
; The Path is mandatory for ZCPR 3.3. |
|||
|
|||
EXPATH EQU 0FDF4H ; External Path starting Address |
|||
EXPATHS EQU 5 ; (Path Size = EXPATHS*2 + 1 = 11 bytes) |
|||
; This defines 5 2-byte Path Elements |
|||
|
|||
; The ZCPR3 External FCB is mandatory for ZCPR 3.3. |
|||
|
|||
EXTFCB EQU 0FDD0H ; 36-Byte ZCPR3 External FCB |
|||
EXTFCBS EQU YES |
|||
|
|||
; The ZCPR3 Message Buffers are mandatory for ZCPR 3.3. |
|||
|
|||
Z3MSG EQU 0FD80H ; 80-Byte ZCPR3 Message Buffer |
|||
Z3MSGS EQU YES |
|||
|
|||
; Shell Stack definition. Set SHSTKS to 0 to eliminate Shell Stack |
|||
|
|||
SHSTK EQU 0FD00H ; Shell Stack Starting Address |
|||
SHSTKS EQU 4 ; Number of SHSIZE-Byte Shell Stack entries |
|||
SHSIZE EQU 32 ; (Stack Size = SHSTKS * SHSIZE = 128 Bytes) |
|||
|
|||
; ZCPR3 Named Directory Buffer definition. Set Z3NDIRS to 0 to eliminate |
|||
; the named directory buffer. |
|||
|
|||
Z3NDIR EQU 0FC00H ; Start of Named Directory Buffer |
|||
Z3NDIRS EQU 14 ; Number of Named Directory Elements |
|||
; (NDIR Size = Z3NDIRS * 18 + 1 = 253 Bytes) |
|||
|
|||
; Flow Command Package definition. Set FCPS to 0 to eliminate FCP |
|||
|
|||
FCP EQU 0FA00H ; Start of Flow Command Package |
|||
FCPS EQU 4 ; (FCP Size = 128 * FCPS = 512 Bytes) |
|||
|
|||
; Resident Command Processor Definition. Set RCPS to 0 to eliminate RCP |
|||
|
|||
RCP EQU 0F200H ; Start of Resident Command Processor |
|||
RCPS EQU 16 ; (RCP Size = 128 * RCPS = 2 kBytes) |
|||
|
|||
; IO Package definition. Set IOPS to 0 to eliminate IOP |
|||
|
|||
IOP EQU 0EC00H ; Start of IO Package |
|||
IOPS DEFL 12 ; (IOP Size = 128 * IOPS = 1.5 kBytes) |
|||
|
|||
;========================================================================= |
|||
; Resident User Space Definition. Set USPCS to 0 to eliminate USPC. |
|||
; The USPC Value marks the Lower Limit of Reserved Common High Memory and |
|||
; MUST BE PRESENT! |
|||
|
|||
USPC EQU 0E900H ; Start of Resident User Space (MANDATORY) |
|||
USPCS EQU 6 ; (USPC Size = 128 * USPCS = 0.75 kBytes) |
|||
|
|||
;--- End of Z3BASE.LIB --- |
|||
|
|||
@ -0,0 +1,126 @@ |
|||
; B/P Bios System Z3 Definition File. |
|||
|
|||
; This file is adapted from the basic Z3BASE.LIB configuration file used for |
|||
; most ZCPR33 systems. It has added the new definitions for the Resident |
|||
; User Space defined in B/P Bios descriptions. |
|||
;========================================================================= |
|||
;== NOTE: The Starting Address of the User Space marks the lower == |
|||
;== base of memory and MUST be entered. B/P Bios Utilities use == |
|||
;== this address to locate many portions of the operating system. == |
|||
;========================================================================= |
|||
; To change your systems definition, first sketch out the memory map in the |
|||
; comment table, then set the equates to reflect the memory map, doing any |
|||
; required calculations for element sizes and required spaces. As an |
|||
; alternative, just leave this file alone and configure everything with |
|||
; the utilities provided. |
|||
|
|||
; FE00 - FFFF 512 Bytes HBIOS Reserved |
|||
; FDFF 1 Byte Wheel byte |
|||
; FDF4 - FDFE 11 Bytes Path (5 elements) |
|||
; FDD0 - FDF3 36 Bytes ZCPR3 External FCB |
|||
; FD80 - FDCF 80 Bytes ZCPR3 Message Buffers |
|||
; FD00 - FD7F 128 Bytes ZCPR3 Shell Stack |
|||
; FC00 - FCFF 256 Bytes Named Directory Buffer |
|||
; FA00 - FBFF 512 Bytes Flow Command Package |
|||
; F200 - F9FF 2.0 KBytes Resident Command Package |
|||
; EC00 - F1FF 1.5 KBytes IO Package |
|||
; EBD0 - EBFF 48 Bytes ZCPR3 External Stack |
|||
; EB00 - EBAF 176 Bytes Multiple Command Line Buffer |
|||
; EA00 - EAFF 256 Bytes Environment Descriptor |
|||
; Bytes 00H-7FH: Z3 Parameters |
|||
; Bytes 80H-FFH: Z3 TCAP |
|||
; E700 - E9FF .75 KBytes Resident User Space |
|||
|
|||
; The remainder is for the Operating System. Exact sizes vary depending |
|||
; primarily on the Number and sizes of Hard Drive Partitions, but may be: |
|||
|
|||
; D300 - E6FF 5.0 KBytes B/P BIOS (unbanked version) |
|||
; C500 - D2FF 3.5 KBytes ZSDOS 1.0 BDOS |
|||
; BD00 - C4FF 2 KBytes ZCPR 3.3 Command Processor |
|||
; 0100 - BCFF ~47 KBytes Transient Program Area |
|||
; 0000 - 00FF 256 Bytes Standard CP/M Buffers |
|||
;======================================================================== |
|||
|
|||
FALSE EQU 0 |
|||
TRUE EQU NOT FALSE |
|||
|
|||
YES EQU TRUE |
|||
NO EQU FALSE |
|||
|
|||
; The External Stack is placed in the very top position in memory. It is |
|||
; mandatory for B/P Bios and ZCPR 3.3. |
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|
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EXTSTK EQU 0EBD0H ; ZCPR3 External Stack |
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EXTSTKS EQU YES |
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|
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; The Multiple Command Line Buffer is placed in the Top Page of Memory to |
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; place it above the Environment. It is mandatory for ZCPR 3.3. |
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|
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Z3CL EQU 0EB00H ; ZCPR3 Command Line Buffer |
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Z3CLS EQU 208-5 ; Size of Command Line Buffer-5 |
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|
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; The ZCPR3 External Environment Descriptor is mandatory B/P Bios & ZCPR 3.3. |
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; The Environment Descriptor MUST begin on an even Page Boundary (xx00H). |
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|
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Z3ENV EQU 0EA00H ; Environment Descriptors |
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Z3ENVS EQU 2 ; Size of Env Descriptor in 128-Byte Blks |
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|
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; The ZCPR3 Wheel Byte is mandatory for ZCPR 3.3. |
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|
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Z3WHL EQU 0FDFFH ; Wheel Byte Address |
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Z3WHLS EQU YES |
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|
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; The Path is mandatory for ZCPR 3.3. |
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|
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EXPATH EQU 0FDF4H ; External Path starting Address |
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EXPATHS EQU 5 ; (Path Size = EXPATHS*2 + 1 = 11 bytes) |
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; This defines 5 2-byte Path Elements |
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|
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; The ZCPR3 External FCB is mandatory for ZCPR 3.3. |
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|
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EXTFCB EQU 0FDD0H ; 36-Byte ZCPR3 External FCB |
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EXTFCBS EQU YES |
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|
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; The ZCPR3 Message Buffers are mandatory for ZCPR 3.3. |
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|
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Z3MSG EQU 0FD80H ; 80-Byte ZCPR3 Message Buffer |
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Z3MSGS EQU YES |
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|
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; Shell Stack definition. Set SHSTKS to 0 to eliminate Shell Stack |
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|
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SHSTK EQU 0FD00H ; Shell Stack Starting Address |
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SHSTKS EQU 4 ; Number of SHSIZE-Byte Shell Stack entries |
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SHSIZE EQU 32 ; (Stack Size = SHSTKS * SHSIZE = 128 Bytes) |
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|
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; ZCPR3 Named Directory Buffer definition. Set Z3NDIRS to 0 to eliminate |
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; the named directory buffer. |
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|
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Z3NDIR EQU 0FC00H ; Start of Named Directory Buffer |
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Z3NDIRS EQU 14 ; Number of Named Directory Elements |
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; (NDIR Size = Z3NDIRS * 18 + 1 = 253 Bytes) |
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|
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; Flow Command Package definition. Set FCPS to 0 to eliminate FCP |
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|
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FCP EQU 0FA00H ; Start of Flow Command Package |
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FCPS EQU 4 ; (FCP Size = 128 * FCPS = 512 Bytes) |
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|
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; Resident Command Processor Definition. Set RCPS to 0 to eliminate RCP |
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|
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RCP EQU 0F200H ; Start of Resident Command Processor |
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RCPS EQU 16 ; (RCP Size = 128 * RCPS = 2 kBytes) |
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|
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; IO Package definition. Set IOPS to 0 to eliminate IOP |
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|
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IOP EQU 0EC00H ; Start of IO Package |
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IOPS DEFL 12 ; (IOP Size = 128 * IOPS = 1.5 kBytes) |
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|
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;========================================================================= |
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; Resident User Space Definition. Set USPCS to 0 to eliminate USPC. |
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; The USPC Value marks the Lower Limit of Reserved Common High Memory and |
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; MUST BE PRESENT! |
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|
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USPC EQU 0E700H ; Start of Resident User Space (MANDATORY) |
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USPCS EQU 6 ; (USPC Size = 128 * USPCS = 0.75 kBytes) |
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|
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;--- End of Z3BASE.LIB --- |
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Reference in new issue