Merge pull request #181 from wwarthen/dev

Allow swapping MT011 SPI ports

Doc/ChangeLog.txt

@@ -23,6 +23,8 @@ Version 3.1.1
 - WBW: Allow selection of RAM/ROM disk individually in build
 - WBW: Support 256KB ROM size
 - WBW: CP/M 3 RTC support is now complete (reads and writes RTC date/time)
+- WBW: Add config to allow swapping logical order of MT011 SPI ports
+- WBW: COPY.COM updated from v1.72 -> v1.73 throughout distribution
 
 Version 3.1
 -----------

Source/HBIOS/cfg_ezz80.asm

@@ -189,6 +189,7 @@ SDMODE		.EQU	SDMODE_PPI	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT

Source/HBIOS/cfg_master.asm

@@ -249,6 +249,7 @@ SDMODE		.EQU	SDMODE_NONE	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT

Source/HBIOS/cfg_rcz180.asm

@@ -201,6 +201,7 @@ SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT

Source/HBIOS/cfg_rcz280.asm

@@ -218,6 +218,7 @@ SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT

Source/HBIOS/cfg_rcz80.asm

@@ -207,6 +207,7 @@ SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT

Source/HBIOS/cfg_scz180.asm

@@ -196,6 +196,7 @@ SDMODE		.EQU	SDMODE_SC	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT

Source/HBIOS/sd.asm

@@ -239,11 +239,25 @@ SD_RDNTR	.EQU	SD_BASE	+ 0	; Read data and NO transfer
 SD_OPRREG	.EQU	SD_BASE + 2	; SD CHIP SELECTOR
 SD_OPRDEF	.EQU	%00000000	; QUIESCENT STATE
 SD_CDX		.EQU	%00000001	; IN/OUT:SD_OPREG:0 = CD0, PMOD pull CD0 low
+  #IF (!SDMTSWAP)
+    ; USE NATURAL ORDER
 SD_CD0		.EQU	%00000010	; IN:SD_OPREG:1 = CD1, IN=0 Card detect switch
 SD_CD1		.EQU	%00000100	; IN:SD_OPREG:2 = CD2, IN=0 Card detect switch
+  #ELSE
+    ; REVERSE THE PORTS
+SD_CD0		.EQU	%00000100	; IN:SD_OPREG:2 = CD2, IN=0 Card detect switch
+SD_CD1		.EQU	%00000010	; IN:SD_OPREG:1 = CD1, IN=0 Card detect switch
+  #ENDIF
 SD_CSX		.EQU	%00001000	; IN/OUT:SD_OPREG:3 = CS0, PMOD SPI CS
+  #IF (!SDMTSWAP)
+    ; USE NATURAL ORDER
 SD_CS0		.EQU	%00010000	; IN/OUT:SD_OPREG:4 = CS1, SDCARD1 CS, IN=1 Card present
 SD_CS1		.EQU	%00100000	; IN/OUT:SD_OPREG:5 = CS2, SDCARD2 CS, IN=1 Card present
+  #ELSE
+    ; REVERSE THE PORTS
+SD_CS0		.EQU	%00100000	; IN/OUT:SD_OPREG:5 = CS2, SDCARD2 CS, IN=1 Card present
+SD_CS1		.EQU	%00010000	; IN/OUT:SD_OPREG:4 = CS1, SDCARD1 CS, IN=1 Card present
+  #ENDIF
 SD_IOBASE	.EQU	SD_BASE		; IOBASE
 #ENDIF
 ;

Source/ZZR/ZZR Disk Layout.txt

@@ -16,9 +16,9 @@ Notes
 
 - At startup CPLD ROM is mapped to Z80 CPU address space 0x0000-0x003F, CPU begins execution at 0x0000
 - CPLD ROM (CF bootstrap mode) loads CF Boot Loader (256B) at 0xB000 and runs it
-- CF Boot Loader loads ZRC Monitor at 0xB400 and runs it
-- User loads ZZRCC RomWBW Loader hex file at 0x5000, then runs it using G5000
-- User loads RomWBW ROM hex file to contents of RAM, then runs it using G0000
+- CF Boot Loader loads ZZRCC Monitor at 0xB400 and runs it
+- Monitor (Boot RomWBW) loads ZZRCC RomWBW Loader hex file at 0x5000, then runs it
+- RomWBW Loader loads RomWBW ROM image to contents of RAM, then runs it
 
 
 ;;- ZZRCC Monitor reads 512KB (RomWBW) from sectors 0x120-0x51F of CF into first 512KB of RAM

Source/ver.inc

@@ -2,4 +2,4 @@
 #DEFINE	RMN	1
 #DEFINE	RUP	1
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"3.1.1-pre.67"
+#DEFINE BIOSVER	"3.1.1-pre.68"

Source/ver.lib

@@ -3,5 +3,5 @@ rmn	equ	1
 rup	equ	1
 rtp	equ	0
 biosver	macro
-	db	"3.1.1-pre.67"
+	db	"3.1.1-pre.68"
 	endm