mirror of https://github.com/wwarthen/RomWBW.git
Wayne Warthen
6 years ago
26 changed files with 166 additions and 5 deletions
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; |
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;================================================================================================== |
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; EASY Z80 STANDARD CONFIGURATION |
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;================================================================================================== |
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; |
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; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE |
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; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS |
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; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE |
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; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS. |
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; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY |
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; YOUR FILE IN THE BUILD PROCESS. |
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; |
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; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM. |
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; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO |
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; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON |
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; SETTINGS. |
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; |
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; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE, |
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; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING |
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; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS! |
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; |
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; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO |
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; DIRECTORIES ABOVE THIS ONE). |
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; |
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#DEFINE PLATFORM_NAME "TINYZ80" |
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; |
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#include "cfg_ezz80.asm" |
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; |
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CPUOSC .SET 16000000 ; CPU OSC FREQ IN MHZ |
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; |
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IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) |
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; |
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PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) |
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; |
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EIPCENABLE .SET TRUE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION |
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; |
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CTCBASE .SET $10 ; CTC BASE I/O ADDRESS |
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LEDENABLE .SET TRUE ; ENABLES STATUS LED (SINGLE LED) |
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LEDPORT .SET $6E ; STATUS LED PORT ADDRESS |
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SIO0BASE .SET $18 ; SIO 0: REGISTERS BASE ADR |
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IDE0BASE .SET $90 ; IDE 0: IO BASE ADDRESS |
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@ -0,0 +1,75 @@ |
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; |
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; Z80 EIPC (Z84C15) REGISTERS |
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; |
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EIPC_SCRP .EQU $EE ; SYSTEM CONTROL REGISTER POINTER |
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EIPC_SCDP .EQU $EF ; SYSTEM CONTROL DATA PORT |
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EIPC_WDTMR .EQU $F0 ; WATCHDOG TIMER MASTER REGISTER |
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EIPC_WDTCR .EQU $F1 ; WATCHDOG TIMER COMMAND REGISTER |
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EIPC_INTPR .EQU $F4 ; INTERRUPT PRIORITY REGISTER |
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; |
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; SYSTEM CONTROL REGISTERS (REGISTER NUMBER TO BE WRITTEN TO EIPC_SCRP) |
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; |
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EIPC_WCR .EQU $00 ; WAIT STATE CONTROL REGISTER |
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EIPC_MWBR .EQU $01 ; MEMORY WAIT BOUNDARY REGISTER |
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EIPC_CSBR .EQU $02 ; CHIP SELECT BOUNDARY REGISTER |
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EIPC_MCR .EQU $03 ; MISCELLANEOUS CONTROL REGISTER |
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; |
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; WAIT STATE VALUES (FOR EIPC_WCR) |
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; |
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EIPC_IO_0WS .EQU $00 ; NO (ZERO) I/O WAIT STATES |
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EIPC_IO_2WS .EQU $01 ; 2 I/O WAIT STATES |
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EIPC_IO_4WS .EQU $02 ; 4 I/O WAIT STATES |
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EIPC_IO_6WS .EQU $03 ; 6 I/O WAIT STATES |
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EIPC_MEM_OWS .EQU $00 ; NO (ZERO) MEMORY WAIT STATES |
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EIPC_MEM_1WS .EQU $04 ; 1 MEMORY WAIT STATE |
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EIPC_MEM_2WS .EQU $08 ; 2 MEMORY WAIT STATES |
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EIPC_MEM_3WS .EQU $0C ; 3 MEMORY WAIT STATES |
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EIPC_OCF_0WS .EQU $00 ; NO ADDITIONAL WAIT ON OP-CODE FETCH |
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EIPC_OCF_1WS .EQU $10 ; +1 WAIT STATE ON OP-CODE FETCH |
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EIPC_INT_0WS .EQU $00 ; NO WAIT ON INTERRUPT VECTOR READ |
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EIPC_INT_1WS .EQU $20 ; 1 WAIT STATE ON INT. VECTOR READ |
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EIPC_CHAIN_0WS .EQU $00 ; 0 WAIT ON INT ACK. / 0 WAIT ON RETI |
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EIPC_CHAIN_2WS .EQU $40 ; 2 WAIT ON INT ACK. / 0 WAIT ON RETI |
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EIPC_CHAIN_4WS .EQU $80 ; 4 WAIT ON INT ACK. / 2 WAIT ON RETI |
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EIPC_CHAIN_6WS .EQU $C0 ; 6 WAIT ON INT ACK. / 4 WAIT ON RETI |
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; |
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; MISCELLANEOUS CONTROL REGISTER VALUES |
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; |
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EIPC_CS0_DIS .EQU $00 ; DISABLE /CS0 |
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EIPC_CS0_ENA .EQU $01 ; ENABLE /CS0 |
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EIPC_CS1_DIS .EQU $00 ; DISABLE /CS1 |
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EIPC_CS1_ENA .EQU $02 ; ENABLE /CS1 |
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EIPC_32CRC_DIS .EQU $00 ; DISABLE 32-BIT CRC FOR SIO CHANNEL A |
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EIPC_32CRC_ENA .EQU $04 ; ENABLE 32-BIT CRC FOR SIO CHANNEL A |
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EIPC_RSTOUT_DIS .EQU $08 ; DISABLE RESET OUTPUT |
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EIPC_RSTOUT_ENA .EQU $00 ; ENABLE RESET OUTPUT |
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EIPC_CLKDIV1 .EQU $10 ; DIVIDE XTAL/CGC CLOCK BY ONE |
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EIPC_CLKDIV2 .EQU $00 ; DIVIDE XTAL/CGC CLOCK BY TWO |
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; |
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; WATCHDOG TIMER MASTER REGISTER VALUES |
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; |
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EIPC_WDT_CONST .EQU $03 ; MUST SET LOWER THREE BITS TO 011 |
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EIPC_HALT_IDLE1 .EQU $00 ; HALT / POWER DOWN MODE - IDLE 1 MODE |
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EIPC_HALT_IDLE2 .EQU $08 ; HALT / POWER DOWN MODE - IDLE 2 MODE |
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EIPC_HALT_STOP .EQU $10 ; HALT / POWER DOWN MODE - STOP MODE |
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EIPC_HALT_RUN .EQU $18 ; HALT / POWER DOWN MODE - RUN MODE |
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EIPC_WDT_P2_16 .EQU $00 ; SET WATCHDOG PERIOD TO TOC * 2^16 |
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EIPC_WDT_P2_18 .EQU $20 ; SET WATCHDOG PERIOD TO TOC * 2^18 |
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EIPC_WDT_P2_20 .EQU $40 ; SET WATCHDOG PERIOD TO TOC * 2^20 |
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EIPC_WDT_P2_22 .EQU $60 ; SET WATCHDOG PERIOD TO TOC * 2^22 |
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EIPC_WDTE .EQU $80 ; ENABLE WATCHDOG TIMER |
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; |
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; WATCHDOG TIMER COMMAND REGISTER VALUES |
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; |
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EIPC_DIS_WDT .EQU $B1 ; DISABLE WATCHDOG TIMER |
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EIPC_CLR_WDT .EQU $4E ; CLEAR WATCHDOG TIMER |
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EIPC_HLT_MODE .EQU $DB ; CHANGE HALT MODE |
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; |
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; INTERRUPT PRIORITY REGISTER VALUES |
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; |
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EIPC_CTC_SIO_PIO .EQU $00 ; PRIORITY HIGH TO LOW: CTC, SIO, PIO |
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EIPC_SIO_CTC_PIO .EQU $01 ; PRIORITY HIGH TO LOW: SIO, CTC, PIO |
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EIPC_CTC_PIO_SIO .EQU $02 ; PRIORITY HIGH TO LOW: CTC, PIO, SIO |
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EIPC_PIO_SIO_CTC .EQU $03 ; PRIORITY HIGH TO LOW: PIO, SIO, CTC |
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EIPC_PIC_CTC_SIO .EQU $04 ; PRIORITY HIGH TO LOW: PIO, CTC, SIO |
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EIPC_SIO_PIO_CTC .EQU $05 ; PRIORITY HIGH TO LOW: SIO, PIO, CTC |
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