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@ -166,7 +166,7 @@ |
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<ul class="nav flex-column"> |
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</ul> |
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</li> |
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<li class="nav-item" data-bs-level="3"><a href="#s100-computers-fpga-z80-sbc" class="nav-link">S100 Computers FPGA Z80 SBC</a> |
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<li class="nav-item" data-bs-level="3"><a href="#s100-computers-t35-fpga-z80-sbc" class="nav-link">S100 Computers T35 FPGA Z80 SBC</a> |
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<ul class="nav flex-column"> |
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</ul> |
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@ -396,7 +396,7 @@ |
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<p><strong>RomWBW Hardware</strong> \ |
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Version 3.6 \ |
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Wayne Warthen (<a href="mailto:wwarthen@gmail.com">wwarthen@gmail.com</a>) \ |
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01 Nov 2025</p> |
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09 Nov 2025</p> |
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<h1 id="overview">Overview</h1> |
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<h2 id="supported-platforms">Supported Platforms</h2> |
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<p>This section contains a summary of the system configuration target for |
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@ -752,10 +752,10 @@ external bank switching.</p> |
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<td><a href="#s100-computers-z80-cpu">S100 Computers Z80 CPU</a><sup>4</sup></td> |
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<td>S100</td> |
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<td>SZ80_std.rom</td> |
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<td style="text-align: right;">9600</td> |
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<td style="text-align: right;">19200</td> |
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</tr> |
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<tr> |
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<td>[S100 Computers T35 FPGA Z80 SBC]<sup>4</sup></td> |
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<td><a href="#s100-computers-t35-fpga-z80-sbc">S100 Computers T35 FPGA Z80 SBC</a><sup>4</sup></td> |
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<td>S100</td> |
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<td>SZ80_t35.rom</td> |
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<td style="text-align: right;">9600</td> |
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@ -1234,7 +1234,7 @@ of the SIO ports, for ease of use with modern computers.</p> |
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</tr> |
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<tr> |
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<td>Serial Default</td> |
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<td>9600 Baud</td> |
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<td>19200 Baud</td> |
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</tr> |
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<tr> |
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<td>Memory Manager</td> |
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@ -1246,7 +1246,7 @@ of the SIO ports, for ease of use with modern computers.</p> |
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</tr> |
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<tr> |
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<td>RAM Size</td> |
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<td>512 KB</td> |
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<td>1024 KB</td> |
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</tr> |
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</tbody> |
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</table> |
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@ -1267,9 +1267,21 @@ of the SIO ports, for ease of use with modern computers.</p> |
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</ul> |
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<h4 id="notes">Notes:</h4> |
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<ul> |
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<li>Requires Propeller Console Board (or equivalent)</li> |
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<li> |
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<p>Initial console will depend on the IOBYTE dip switch settings. See |
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website for dip switch settings.</p> |
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</li> |
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<li> |
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<p>Version 6.0 or greater of the S100 Z80 Monitor ROM is required to load |
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and run RomWBW.</p> |
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</li> |
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<li> |
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<p>RomWBW is loaded by the S100 monitor from either CF Card or SD Card. |
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The CF/SD Card should be imaged using SZ80_std_hd1k_combo.img which |
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includes RomWBW.</p> |
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</li> |
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</ul> |
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<h3 id="s100-computers-fpga-z80-sbc">S100 Computers FPGA Z80 SBC</h3> |
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<h3 id="s100-computers-t35-fpga-z80-sbc">S100 Computers T35 FPGA Z80 SBC</h3> |
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<p>A T35 FPGA Z80 based S100 SBC</p> |
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<ul> |
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<li>Creator: John Monahan</li> |
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@ -1303,7 +1315,7 @@ of the SIO ports, for ease of use with modern computers.</p> |
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</tr> |
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<tr> |
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<td>Serial Default</td> |
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<td>9600 Baud</td> |
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<td>19200 Baud</td> |
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</tr> |
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<tr> |
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<td>Memory Manager</td> |
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@ -1343,12 +1355,25 @@ of the SIO ports, for ease of use with modern computers.</p> |
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<li>SD: MODE=T35, IO=108, UNITS=2</li> |
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</ul> |
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<h4 id="notes_1">Notes:</h4> |
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<p>This RomWBW build is specifically for the Trion T35 based module on the |
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S100 Z80 FPGA board. The Waveshare FPGA module is not supported at this |
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time.</p> |
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<ul> |
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<li>Requires matching FPGA code, see <a href="https://github.com/s100projects/ROMWBW_T35">S100 Projects RomWBW T35 |
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Project</a>.</li> |
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<li> |
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<p>This RomWBW build is specifically for the Trion T35 based module on |
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the S100 Z80 FPGA board. The Waveshare FPGA module is not supported at |
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this time.</p> |
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</li> |
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<li> |
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<p>Requires matching FPGA code, see <a href="https://github.com/s100projects/ROMWBW_T35">S100 Projects RomWBW T35 |
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Project</a>.</p> |
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</li> |
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<li> |
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<p>Initial console will depend on the IOBYTE dip switch settings. See |
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website for dip switch settings.</p> |
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</li> |
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<li> |
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<p>RomWBW is loaded by the S100 monitor from either CF Card or SD Card. |
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The CF/SD Card should be imaged using SZ80_t35_hd1k_combo.img which |
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includes RomWBW.</p> |
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</li> |
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</ul> |
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<h2 id="genesis-z180-system">Genesis Z180 System</h2> |
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<p>A Z180 based board with 512k ram, 512k rom, dual serial / parallel, RTC |
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@ -3520,19 +3545,21 @@ slave as defined by the IEEE-696 specs.</p> |
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<h4 id="supported-hardware_34">Supported Hardware</h4> |
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<ul> |
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<li>INTRTC: ENABLED</li> |
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<li>PLDSER: IO=172</li> |
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<li>ASCI: IO=192, INTERRUPTS ENABLED</li> |
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<li>ASCI: IO=193, INTERRUPTS ENABLED</li> |
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<li>SCC MODE=SZ80, IO=160, CHANNEL A</li> |
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<li>SCC MODE=SZ80, IO=160, CHANNEL B</li> |
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<li>SCON: IO=0</li> |
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<li>MD: TYPE=RAM</li> |
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<li>MD: TYPE=ROM</li> |
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<li>SD: MODE=SC, IO=12, UNITS=1</li> |
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<li>ESPSD: IO=128, PRIMARY</li> |
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<li>ESPSD: IO=128, SECONDARY</li> |
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<li>ESPSD occupies 995 bytes.</li> |
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<li>MD: TYPE=RAM</li> |
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<li>MD: TYPE=ROM</li> |
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<li>PPIDE: MODE=S100A, IO=48, MASTER</li> |
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<li>PPIDE: MODE=S100A, IO=48, SLAVE</li> |
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<li>PPIDE: MODE=S100B, IO=48, MASTER</li> |
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<li>PPIDE: MODE=S100B, IO=48, SLAVE</li> |
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<li>SD: MODE=SC, IO=12, UNITS=1</li> |
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</ul> |
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<h4 id="notes_6">Notes:</h4> |
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<ul> |
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wwarthen
3 months ago