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Use definitions for Z80 EIPC / Z84C15

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Signed-off-by: Sergey Kiselev <skiselev@gmail.com>
This commit is contained in:
Sergey Kiselev
2020-08-01 13:24:43 -07:00
parent f482801b94
commit 78cd69e34d
2 changed files with 15 additions and 12 deletions
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24
Source/HBIOS/hbios.asm
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@@ -861,19 +861,19 @@ HB_START:
#ENDIF
;
#IF (EIPCENABLE)
LD A,$7B ; CLEAR WDTE BIT (DISABLE WATCHDOG)
OUT ($F0),A
LD A,$B1 ; DISABLE WDT - SECOND KEY
OUT ($F1),A
LD A,$00 ; SET SYSTEM CONTROL REGISTER POINTER
LD A,(EIPC_WDT_CONST | EIPC_HALT_RUN | EIPC_WDT_P2_22)
OUT (EIPC_WDTMR),A ; CLEAR WDTE BIT (DISABLE WATCHDOG)
LD A,EIPC_DIS_WDT ; DISABLE WDT - SECOND KEY
OUT (EIPC_WDTCR),A
LD A,EIPC_WCR ; SET SYSTEM CONTROL REGISTER POINTER
; (SCRP) TO POINT TO WAIT STATE
OUT ($EE),A ; CONTROL REGISTER (WCR)
LD A,$00 ; NO WAIT STATES
OUT ($EF),A ; SET SYSTEM CONTROL DATA PORT (SCDP)
LD A,$03 ; SET SCRP TO POINT TO MISCELLANEOUS
OUT ($EE),A ; CONTROL REGISTER (MCR)
LD A,$10 ; DIVIDE CLOCK BY 1, /CS0 DISABLE
OUT ($EF),A ; SET SYSTEM CONTROL DATA PORT (SCDP)
OUT (EIPC_SCRP),A ; CONTROL REGISTER (WCR)
LD A,(EIPC_IO_0WS | EIPC_MEM_OWS | EIPC_OCF_0WS | EIPC_INT_0WS | EIPC_CHAIN_0WS)
OUT (EIPC_SCDP),A ; NO WAIT STATES
LD A,EIPC_MCR ; SET SCRP TO POINT TO MISCELLANEOUS
OUT (EIPC_SCRP),A ; CONTROL REGISTER (MCR)
LD A,EIPC_CLKDIV1 ; DIVIDE CLOCK BY 1, /CS0 DISABLE
OUT (EIPC_SCDP),A ; SET SYSTEM CONTROL DATA PORT (SCDP)
#ENDIF
;
#IF (MEMMGR == MM_Z2)

3
Source/HBIOS/std.asm
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@@ -327,6 +327,9 @@ FORCECON .EQU 0 ; DEFAULT IS TO FOLLOW NORMAL SEQUENCE
#IF (CPUFAM == CPU_Z180)
#INCLUDE "z180.inc"
#ENDIF
#IF (EIPCENABLE)
#INCLUDE "eipc.inc"
#ENDIF
#ENDIF
;
; SETUP DEFAULT CPU SPEED VALUES