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Merge pull request #30 from wwarthen/master

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update to dev
This commit is contained in:
Phillip Stevens
2021-02-09 16:58:11 +11:00
committed by GitHub
parent bec1c46d21 8a7bc97fea
commit 7ceaa06800
19 changed files with 164 additions and 4 deletions
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41
Source/HBIOS/Config/EZZ80_tz80.asm Normal file
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@@ -0,0 +1,41 @@
;
;==================================================================================================
; EASY Z80 STANDARD CONFIGURATION
;==================================================================================================
;
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
; YOUR FILE IN THE BUILD PROCESS.
;
; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
; SETTINGS.
;
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
;
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
; DIRECTORIES ABOVE THIS ONE).
;
#DEFINE PLATFORM_NAME "TINYZ80"
;
#include "cfg_ezz80.asm"
;
CPUOSC .SET 16000000 ; CPU OSC FREQ IN MHZ
;
IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
;
PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
;
EIPCENABLE .SET TRUE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
;
CTCBASE .SET $10 ; CTC BASE I/O ADDRESS
LEDENABLE .SET TRUE ; ENABLES STATUS LED (SINGLE LED)
LEDPORT .SET $6E ; STATUS LED PORT ADDRESS
SIO0BASE .SET $18 ; SIO 0: REGISTERS BASE ADR
IDE0BASE .SET $90 ; IDE 0: IO BASE ADDRESS

1
Source/HBIOS/Makefile
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@@ -3,6 +3,7 @@ OBJECTS =
ifeq (1,1)
OBJECTS += DYNO_std.rom DYNO_std.com
OBJECTS += EZZ80_std.rom EZZ80_std.com
OBJECTS += EZZ80_tz80.rom EZZ80_tz80.com
OBJECTS += MK4_std.rom MK4_std.com
OBJECTS += N8_std.rom N8_std.com
OBJECTS += RCZ180_ext.rom RCZ180_ext.com

2
Source/HBIOS/cfg_dyno.asm
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@@ -154,3 +154,5 @@ PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS
PPI_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
;
UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
;
EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION

2
Source/HBIOS/cfg_ezz80.asm
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@@ -176,3 +176,5 @@ PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS
PPI_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
;
UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
;
EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION

2
Source/HBIOS/cfg_master.asm
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@@ -231,3 +231,5 @@ PPI_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
;
UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
UFBASE .EQU $0C ; UF: REGISTERS BASE ADR
;
EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION

2
Source/HBIOS/cfg_mk4.asm
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@@ -185,3 +185,5 @@ PPI_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
;
UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
UFBASE .EQU $0C ; UF: REGISTERS BASE ADR
;
EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION

2
Source/HBIOS/cfg_n8.asm
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@@ -185,3 +185,5 @@ PPI_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
;
UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
FIFO_BASE .EQU $0C ; UF: REGISTERS BASE ADR
;
EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION

2
Source/HBIOS/cfg_rcz180.asm
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@@ -186,3 +186,5 @@ PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS
PPI_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
;
UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
;
EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION

2
Source/HBIOS/cfg_rcz80.asm
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@@ -191,3 +191,5 @@ PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS
PPI_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
;
UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
;
EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION

2
Source/HBIOS/cfg_sbc.asm
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@@ -186,3 +186,5 @@ PPI_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
;
UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
UFBASE .EQU $0C ; UF: REGISTERS BASE ADR
;
EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION

2
Source/HBIOS/cfg_scz180.asm
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@@ -182,3 +182,5 @@ PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS
PPI_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
;
UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
;
EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION

2
Source/HBIOS/cfg_zeta.asm
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@@ -134,3 +134,5 @@ PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS
PPI_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
;
UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
;
EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION

2
Source/HBIOS/cfg_zeta2.asm
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@@ -139,3 +139,5 @@ PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS
PPI_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
;
UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
;
EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION

75
Source/HBIOS/eipc.inc Normal file
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@@ -0,0 +1,75 @@
;
; Z80 EIPC (Z84C15) REGISTERS
;
EIPC_SCRP .EQU $EE ; SYSTEM CONTROL REGISTER POINTER
EIPC_SCDP .EQU $EF ; SYSTEM CONTROL DATA PORT
EIPC_WDTMR .EQU $F0 ; WATCHDOG TIMER MASTER REGISTER
EIPC_WDTCR .EQU $F1 ; WATCHDOG TIMER COMMAND REGISTER
EIPC_INTPR .EQU $F4 ; INTERRUPT PRIORITY REGISTER
;
; SYSTEM CONTROL REGISTERS (REGISTER NUMBER TO BE WRITTEN TO EIPC_SCRP)
;
EIPC_WCR .EQU $00 ; WAIT STATE CONTROL REGISTER
EIPC_MWBR .EQU $01 ; MEMORY WAIT BOUNDARY REGISTER
EIPC_CSBR .EQU $02 ; CHIP SELECT BOUNDARY REGISTER
EIPC_MCR .EQU $03 ; MISCELLANEOUS CONTROL REGISTER
;
; WAIT STATE VALUES (FOR EIPC_WCR)
;
EIPC_IO_0WS .EQU $00 ; NO (ZERO) I/O WAIT STATES
EIPC_IO_2WS .EQU $01 ; 2 I/O WAIT STATES
EIPC_IO_4WS .EQU $02 ; 4 I/O WAIT STATES
EIPC_IO_6WS .EQU $03 ; 6 I/O WAIT STATES
EIPC_MEM_OWS .EQU $00 ; NO (ZERO) MEMORY WAIT STATES
EIPC_MEM_1WS .EQU $04 ; 1 MEMORY WAIT STATE
EIPC_MEM_2WS .EQU $08 ; 2 MEMORY WAIT STATES
EIPC_MEM_3WS .EQU $0C ; 3 MEMORY WAIT STATES
EIPC_OCF_0WS .EQU $00 ; NO ADDITIONAL WAIT ON OP-CODE FETCH
EIPC_OCF_1WS .EQU $10 ; +1 WAIT STATE ON OP-CODE FETCH
EIPC_INT_0WS .EQU $00 ; NO WAIT ON INTERRUPT VECTOR READ
EIPC_INT_1WS .EQU $20 ; 1 WAIT STATE ON INT. VECTOR READ
EIPC_CHAIN_0WS .EQU $00 ; 0 WAIT ON INT ACK. / 0 WAIT ON RETI
EIPC_CHAIN_2WS .EQU $40 ; 2 WAIT ON INT ACK. / 0 WAIT ON RETI
EIPC_CHAIN_4WS .EQU $80 ; 4 WAIT ON INT ACK. / 2 WAIT ON RETI
EIPC_CHAIN_6WS .EQU $C0 ; 6 WAIT ON INT ACK. / 4 WAIT ON RETI
;
; MISCELLANEOUS CONTROL REGISTER VALUES
;
EIPC_CS0_DIS .EQU $00 ; DISABLE /CS0
EIPC_CS0_ENA .EQU $01 ; ENABLE /CS0
EIPC_CS1_DIS .EQU $00 ; DISABLE /CS1
EIPC_CS1_ENA .EQU $02 ; ENABLE /CS1
EIPC_32CRC_DIS .EQU $00 ; DISABLE 32-BIT CRC FOR SIO CHANNEL A
EIPC_32CRC_ENA .EQU $04 ; ENABLE 32-BIT CRC FOR SIO CHANNEL A
EIPC_RSTOUT_DIS .EQU $08 ; DISABLE RESET OUTPUT
EIPC_RSTOUT_ENA .EQU $00 ; ENABLE RESET OUTPUT
EIPC_CLKDIV1 .EQU $10 ; DIVIDE XTAL/CGC CLOCK BY ONE
EIPC_CLKDIV2 .EQU $00 ; DIVIDE XTAL/CGC CLOCK BY TWO
;
; WATCHDOG TIMER MASTER REGISTER VALUES
;
EIPC_WDT_CONST .EQU $03 ; MUST SET LOWER THREE BITS TO 011
EIPC_HALT_IDLE1 .EQU $00 ; HALT / POWER DOWN MODE - IDLE 1 MODE
EIPC_HALT_IDLE2 .EQU $08 ; HALT / POWER DOWN MODE - IDLE 2 MODE
EIPC_HALT_STOP .EQU $10 ; HALT / POWER DOWN MODE - STOP MODE
EIPC_HALT_RUN .EQU $18 ; HALT / POWER DOWN MODE - RUN MODE
EIPC_WDT_P2_16 .EQU $00 ; SET WATCHDOG PERIOD TO TOC * 2^16
EIPC_WDT_P2_18 .EQU $20 ; SET WATCHDOG PERIOD TO TOC * 2^18
EIPC_WDT_P2_20 .EQU $40 ; SET WATCHDOG PERIOD TO TOC * 2^20
EIPC_WDT_P2_22 .EQU $60 ; SET WATCHDOG PERIOD TO TOC * 2^22
EIPC_WDTE .EQU $80 ; ENABLE WATCHDOG TIMER
;
; WATCHDOG TIMER COMMAND REGISTER VALUES
;
EIPC_DIS_WDT .EQU $B1 ; DISABLE WATCHDOG TIMER
EIPC_CLR_WDT .EQU $4E ; CLEAR WATCHDOG TIMER
EIPC_HLT_MODE .EQU $DB ; CHANGE HALT MODE
;
; INTERRUPT PRIORITY REGISTER VALUES
;
EIPC_CTC_SIO_PIO .EQU $00 ; PRIORITY HIGH TO LOW: CTC, SIO, PIO
EIPC_SIO_CTC_PIO .EQU $01 ; PRIORITY HIGH TO LOW: SIO, CTC, PIO
EIPC_CTC_PIO_SIO .EQU $02 ; PRIORITY HIGH TO LOW: CTC, PIO, SIO
EIPC_PIO_SIO_CTC .EQU $03 ; PRIORITY HIGH TO LOW: PIO, SIO, CTC
EIPC_PIC_CTC_SIO .EQU $04 ; PRIORITY HIGH TO LOW: PIO, CTC, SIO
EIPC_SIO_PIO_CTC .EQU $05 ; PRIORITY HIGH TO LOW: SIO, PIO, CTC

16
Source/HBIOS/hbios.asm
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@@ -866,6 +866,22 @@ HB_START:
;
#ENDIF
;
#IF (EIPCENABLE)
LD A,(EIPC_WDT_CONST | EIPC_HALT_RUN | EIPC_WDT_P2_22)
OUT (EIPC_WDTMR),A ; CLEAR WDTE BIT (DISABLE WATCHDOG)
LD A,EIPC_DIS_WDT ; DISABLE WDT - SECOND KEY
OUT (EIPC_WDTCR),A
LD A,EIPC_WCR ; SET SYSTEM CONTROL REGISTER POINTER
; (SCRP) TO POINT TO WAIT STATE
OUT (EIPC_SCRP),A ; CONTROL REGISTER (WCR)
LD A,(EIPC_IO_0WS | EIPC_MEM_OWS | EIPC_OCF_0WS | EIPC_INT_0WS | EIPC_CHAIN_0WS)
OUT (EIPC_SCDP),A ; NO WAIT STATES
LD A,EIPC_MCR ; SET SCRP TO POINT TO MISCELLANEOUS
OUT (EIPC_SCRP),A ; CONTROL REGISTER (MCR)
LD A,EIPC_CLKDIV1 ; DIVIDE CLOCK BY 1, /CS0 DISABLE
OUT (EIPC_SCDP),A ; SET SYSTEM CONTROL DATA PORT (SCDP)
#ENDIF
;
#IF (MEMMGR == MM_Z2)
; SET PAGING REGISTERS
#IFDEF ROMBOOT

3
Source/HBIOS/std.asm
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@@ -327,6 +327,9 @@ FORCECON .EQU 0 ; DEFAULT IS TO FOLLOW NORMAL SEQUENCE
#IF (CPUFAM == CPU_Z180)
#INCLUDE "z180.inc"
#ENDIF
#IF (EIPCENABLE)
#INCLUDE "eipc.inc"
#ENDIF
#ENDIF
;
; SETUP DEFAULT CPU SPEED VALUES