Merge pull request #65 from wwarthen/master

Resync
2 years ago · 81da5af7ae
126 changed files with 4512 additions and 2800 deletions
--- a/Doc/ChangeLog.txt
+++ b/Doc/ChangeLog.txt
@ -12,6 +12,8 @@ Version 3.5
 - WBW: Added Cowgol disk image based on the work of Ladislau Szilagyi
 - WBW: Added support for CP/NET on Duodyne Disk I/O
 - DDW: Added support for Duodyne Media board
+- WBW: Auto restore TMS video on user reset (CP/M warm boot)
+- L?B: Added support for NABU w/ RomWBW Option Board

 Version 3.4
 -----------
--- a/Applications.pdf
+++ b/Applications.pdf
--- a/Catalog.pdf
+++ b/Catalog.pdf
--- a/Errata.pdf
+++ b/Errata.pdf
--- a/Applications.pdf
+++ b/Applications.pdf
--- a/Doc/RomWBW
+++ b/Doc/RomWBW
--- a/Doc/RomWBW
+++ b/Doc/RomWBW
--- a/ReadMe.md
+++ b/ReadMe.md
@ -3,7 +3,7 @@
 **RomWBW ReadMe** \
 Version 3.5 \
 Wayne Warthen  ([wwarthen@gmail.com](mailto:wwarthen@gmail.com)) \
-03 Apr 2024
+03 May 2024

 # Overview

@ -229,6 +229,8 @@ let me know if I missed you!
 - Ladislau Szilagyi has contributed an enhanced version of CP/M Cowgol
  that leverages RomWBW memory banking.

+- Les Bird has contributed support for the NABU w/ Option Board
+
 Contributions of all kinds to RomWBW are very welcome.

 # Licensing
--- a/ReadMe.txt
+++ b/ReadMe.txt
@ -1,6 +1,6 @@
 RomWBW ReadMe
 Wayne Warthen (wwarthen@gmail.com)
-03 Apr 2024
+03 May 2024



@ -230,6 +230,8 @@ let me know if I missed you!
 -   Ladislau Szilagyi has contributed an enhanced version of CP/M Cowgol
    that leverages RomWBW memory banking.

+-   Les Bird has contributed support for the NABU w/ Option Board
+
 Contributions of all kinds to RomWBW are very welcome.


--- a/Source/Apps/FAT/ReadMe.md
+++ b/Source/Apps/FAT/ReadMe.md
@ -1,7 +1,7 @@
 # RomWBW HBIOS CP/M FAT Utility ("FAT.COM")

 Author: Wayne Warthen \
-Updated: 6-Jan-2024
+Updated: 6-May-2024

 This application allows copying files between CP/M filesystems and FAT 
 filesystems (DOS, Windows, Mac, Linux, etc.).  The application runs on 
@ -72,6 +72,38 @@ creation.
 - Wildcard matching in FAT filesystems is a bit unusual as
   implemented by FatFs.  See FatFs documentation.

+ - The `FAT FORMAT` command will not perform a physical format on
+   floppy disks.  You must use FDU to do this prior to using
+   `FAT FORMAT`.
+
+ - Formatting (`FAT FORMAT`) of floppies does not work well.  The    
+   underlying FatFs library uses some non-standard fields.  The 
+   resulting floppy may or may not be useable on other systems.  It is 
+   best to format a FAT floppy on a Windows or DOS system.  You should 
+   have no problems copying files to/from such a floppy using `FAT`.
+
+### Known Issues
+
+ - CP/M (and workalike) OSes have significant restrictions on filename
+   characters.  The FAT application will block any attempt to create a
+   file on the CP/M filesystem containing any of these prohibited
+   characters:
+
+|         `< > . , ; : ? * [ ] |/ \`
+
+   The operation will be aborted with "`Error: Invalid Path Name`" if such
+   a filename character is encountered.
+
+   Since MS-DOS does allow some of these characters, you can have
+   issues when copying files from MS-DOS to CP/M if the MS-DOS filenames
+   use these characters.  Unfortunately, FAT is not yet smart enough to
+   substitute illegal characters with legal ones.  So, you will need to
+   clean the filenames before trying to copy them to CP/M.
+
+ - The FAT application does try to detect the scenario where you are
+   copying a file to itself.  However, this detection is not perfect and
+   can corrupt a file if it occurs.  Be careful to avoid this.
+
 ### License:

  GNU GPLv3 (see file LICENSE.txt)
@ -123,3 +155,4 @@ creation.
 | 12-Oct-2023 | v0.9.9  | (beta) handle updated HBIOS Disk Device call                |
 | 6-Jan-2024  | v1.0.0  | updated to latest FsFat (v0.15)                             |
 |             |         | updated to latest SDCC (v4.3)                               |
+| 6-May-2024  | v1.1.0  | improve floppy format boot record                           |
--- a/Source/Apps/FAT/fat.com
+++ b/Source/Apps/FAT/fat.com
--- a/Source/Apps/Tune/tune.asm
+++ b/Source/Apps/Tune/tune.asm
@ -47,6 +47,8 @@
 ;   2022-03-20 [DDW] Add support for MBC PSG module
 ;   2023-03-30 [WBW] Fix for quark delay adjustment being trashed
 ;   2024-02-23 [WBW] Include ACR value in config table
+;   2024-04-16 [WBW] Add support for NABU AY-3-8910
+;   2024-05-10 [WBW] Hack to avoid corrupting bits 6&7 of PSG R7 for NABU!
 ;_______________________________________________________________________________
 ;
 ; ToDo:
@ -632,6 +634,9 @@ CFGSIZ	.EQU	$ - CFGTBL
 ;
 	.DB	17,	$A4,	$A5,	$A4,	$FF,	$A6,	$FE	; DUODYNE
 	.DW	HWSTR_DUO
+;
+	.DB	22,	$41,	$40,	$40,	$FF,	$FF,	$FF	; NABU
+	.DW	HWSTR_NABU
 ;
 	.DB	$FF					; END OF TABLE MARKER
 ;
@ -661,7 +666,7 @@ TMP		.DB	0	; work around use of undocumented Z80
 HBIOSMD		.DB	0	; NON-ZERO IF USING HBIOS SOUND DRIVER, ZERO OTHERWISE
 OCTAVEADJ	.DB	0	; AMOUNT TO ADJUST OCTAVE UP OR DOWN

-MSGBAN		.DB	"Tune Player for RomWBW v3.6, 23-Feb-2024",0
+MSGBAN		.DB	"Tune Player for RomWBW v3.8, 10-May-2024",0
 MSGUSE		.DB	"Copyright (C) 2024, Wayne Warthen, GNU GPL v3",13,10
 		.DB	"PTxPlayer Copyright (C) 2004-2007 S.V.Bulba",13,10
 		.DB	"MYMPlay by Marq/Lieves!Tuore",13,10,13,10
@ -687,6 +692,7 @@ HWSTR_RCMF	.DB	"RCBus Sound Module (MF)",0
 HWSTR_LINC	.DB	"Z50 LiNC Sound Module",0
 HWSTR_MBC	.DB	"NHYODYNE Sound Module",0
 HWSTR_DUO	.DB	"DUODYNE Sound Module",0
+HWSTR_NABU	.DB	"NABU Onboard Sound",0

 MSGUNSUP	.db	"MYM files not supported with HBIOS yet!\r\n", 0

@ -2080,8 +2086,23 @@ LOUT	OUT (C),A
 	LD 	HL, AYREGS	; START OF VALUE LIST
 LOUT	OUT 	(C), A		; SELECT REGISTER
 	LD 	C, D		; POINT TO DATA PORT
-	OUTI			; WRITE (HL) TO DATA PORT, BUMP HL
-	LD 	C, E		; POINT TO ADDRESS PORT
+
+	; UGLINESS FOR NABU!  WE NEED TO KEEP BIT 7 = 0, AND BIT 6 = 1
+	; FOR PSG REG 7
+	CP	7		; PSG REG 7?
+	JR	NZ,LOUT1	; SKIP SPECIAL PROCESSING
+	PUSH	AF		; SAVE AF
+	LD	A,(HL)		; GET VALUE BYTE
+	AND	%00111111	; FIX BITS 6 & 7
+	OR	%01000000	; ... FOR NABU!
+	OUT	(C),A		; SEND THE FIXED VALUE
+	DEC	B		; SIMULATE THE RESET		
+	INC	HL		; ... OF OUTI
+	POP	AF		; RESTORE AF
+	JR	LOUT1A		; RESUME LOOP
+	
+LOUT1	OUTI			; WRITE (HL) TO DATA PORT, BUMP HL
+LOUT1A	LD 	C, E		; POINT TO ADDRESS PORT
 	INC 	A		; NEXT REGISTER
 	CP 	13		; REG 13?
 	JR 	NZ, LOUT	; IF NOT, LOOP
@ -2091,6 +2112,7 @@ LOUT	OUT 	(C), A		; SELECT REGISTER
 	JP 	M, LOUT2	; IF BIT 7 SET, RETURN W/O WRITING VALUE
 	LD 	C, D		; SELECT DATA PORT
 	OUT 	(C), A		; WRITE VALUE TO REGISTER 13
+
 LOUT2	CALL 	NORMIO
 	EI
 	RET			; AND DONE
@ -2537,8 +2559,23 @@ upsg1:	ld	hl,(psource)
 psglp:	ld	c, e		; C := RSEL
 	out	(c), a		; Select register
 	ld	c, d		; C := RDAT
-	outi			; Set register value
-	inc	a		; Next register
+	
+	; ugliness for nabu!  we need to keep bit 7 = 0, and bit 6 = 1
+	; for psg reg 7
+	cp	7		; psg reg 7?
+	jr	nz,psglp1	; if not, skip special processing
+	push	af		; save af
+	ld	a,(hl)		; get value byte
+	and	%00111111	; fix bits 6 & 7
+	or	%01000000	; ... for NABU!
+	out	(c),a		; send the fixed value
+	dec	b		; simulate the rest
+	inc	hl		; ... of outi
+	pop	af		; restore af
+	jr	psglp2		; resume loop
+
+psglp1:	outi			; Set register value
+psglp2:	inc	a		; Next register

        ld      bc, (3 * FRAG) - 1   ; Bytes to skip before next reg-1
        add     hl, bc		; Update HL
--- a/Source/CBIOS/cbios.asm
+++ b/Source/CBIOS/cbios.asm
@ -2266,13 +2266,7 @@ INIT:
 	RST	08			; DO IT, DE=MAJ/MIN/UP/PAT
 	LD	A,D			; A := MAJ/MIN
 	CP	((RMJ << 4) | RMN)	; MATCH?
-	JR	NZ,INIT1		; HANDLE VER MISMATCH
-	LD	A,E			; A := OS UP/PAT
-	AND	$F0			; PAT NOT INCLUDED IN MATCH
-	CP	(RUP << 4)		; MATCH?
-	JR	NZ,INIT1		; HANDLE VER MISMATCH
-	JR	INIT2			; ALL GOOD, CONTINUE
-INIT1:
+	JR	Z,INIT2			; ALL GOOD, CONTINUE
 	; DISPLAY VERSION MISMATCH
 	CALL	NEWLINE2		; FORMATTING
 	LD	DE,STR_VERMIS		; VERSION MISMATCH
--- a/Source/CPM3/boot.z80
+++ b/Source/CPM3/boot.z80
@ -96,13 +96,7 @@ init$2:
 	rst	08			; do it, de=maj/min/up/pat
 	ld	a,d			; a := maj/min
 	cp	((rmj << 4) | rmn)	; match?
-	jr	nz,init$3		; handle ver mismatch
-	ld	a,e			; a := os up/pat
-	and	0F0h			; pat not included in match
-	cp	(rup << 4)		; match?
-	jr	nz,init$3		; handle ver mismatch
-	jr	init$4			; all good, continue
-init$3:
+	jr	z,init$4		; all good, continue
 	; display version mismatch
 	ld	hl,vermis$msg		; version mismatch
 	call	?pmsg			; display it
--- a/Source/Doc/Applications.md
+++ b/Source/Doc/Applications.md
@ -48,8 +48,9 @@ found:
 | RTC         | Yes      | Yes        | Yes      |
 | TIMER       | Yes      | Yes        | Yes      |
 | CPUSPD      | Yes      | Yes        | Yes      |
+| FAT         | Yes      | Yes        | Yes      |
+| CLRDIR      | Yes      | Yes        | Yes      |
 | INTTEST     | No       | Yes        | Yes      |
-| FAT         | No       | Yes        | Yes      |
 | TUNE        | No       | Yes        | Yes      |
 | WDATE       | No       | Yes        | Yes      |
 | HTALK       | No       | Yes        | Yes      |
@ -545,7 +546,7 @@ distribution in the Doc/Contrib directory.
 The application supports a significant number of EEPROM parts. It
 should automatically detect your part. If it does not recognize your
 chip, make sure that you do not have a write protect jumper set --
-this jumper can prevent the ROM chip from being recognized.
+this jumper will prevent the ROM chip from being recognized.

 Reprogramming a ROM chip in-place is inherently dangerous. If anything
 goes wrong, you will be left with a non-functional system and no
@ -921,6 +922,15 @@ Files written are not verified.
 Wildcard matching in FAT filesystems is a bit unusual as implemented by
 FatFs. See FatFs documentation.

+The `FAT FORMAT` command will not perform a physical format on floppy 
+disks.  You must use FDU to do this prior to using `FAT FORMAT`.
+
+Formatting (`FAT FORMAT`) of floppies does not work well.  The    
+underlying FatFs library uses some non-standard fields.  The resulting 
+floppy may or may not be useable on other systems.  It is best to format
+a FAT floppy on a Windows or DOS system.  You should have no problems 
+copying files to/from such a floppy using `FAT`.
+
 ## Etymology

 The `FAT` application is an original RomWBW work, but utilizes the
@ -953,6 +963,60 @@ can corrupt a file if it occurs.  Be careful to avoid this.

 `\clearpage`{=latex}

+# CLRDIR
+
+`CLRDIR` is used to initialize a CP/M filesystem.  This is frequently
+used to prepare RomWBW disk slices for use.  If there is any data
+on the filesystem, it will be destroyed.  `CLRDIR` works on CP/M
+drive letters.  To initialize a RomWBW slice, the slice must first be
+assigned to a CP/M drive letter.
+
+
+This application is provided by Max Scane.
+
+## Syntax
+
+| `CLRDIR `*`<drive>`*` [options]`
+
+*`<drive>`* is the CP/M drive letter to be cleared (e.g., "A:")
+
+
+Options:
+
+| `-D`: Enable debug output
+| `-Y`: Do not ask for confirmation
+
+## Usage
+
+This application has a command line interface only.  Type an 
+appropriately formatted command at the command prompt at any of the 
+RomWBW CP/M operatings systems (CP/M 2.2, ZSDOS, CP/M 3, etc.).
+
+You will be prompted for confirmation to continue.  You must type a
+**capital** 'Y' to proceed.  The application will confirm that the
+drive has been cleared.
+
+If used under ZSDOS, you should issue a `RELOG` command after using
+`CLRDIR` to ensure that CP/M relogs the cleared drive.
+
+## Notes
+
+This command is inherently dangerous.  It will completely destroy the
+directory area of the target drive.  Be very careful to ensure you do
+not target a drive that contains useful data.
+
+`CLRDIR` understands the directory formats of all of the RomWBW
+CPM-like operating systems and devices including floppy disks, CF/SD
+Cards, etc.
+
+## Etymology
+
+This application was written and provided by Max Scane. He
+provides it in binary format and is included in the RomWBW
+distribution as a binary file.
+
+`\clearpage`{=latex}
+
 # TUNE

 If your RomWBW system has a sound card based on either an AY-3-8190 or
--- a/Source/Doc/ROM_Applications.md
+++ b/Source/Doc/ROM_Applications.md
@ -10,7 +10,7 @@ programming languages.

 `\clearpage`{=latex}

-# ROMWBW Monitor
+# RomWBW Monitor

 The Monitor program is a low level utility that can be used 
 for testing and programming. It allows programs to be entered,
@ -339,8 +339,8 @@ A comprehensive instruction manual is available in the Doc\\Contrib directory.

 ## ROMWBW unsupported features

-  Cassette loading
-  Cassette saving
+- This ROM-hosted implementation does not support cassette or disk
+  access for loading and saving programs.

 # TastyBASIC

@ -350,10 +350,12 @@ original source can be found here [https://github.com/dimitrit/tastybasic](https

 ## Features / Limitations

- Integer arithmetic, numbers -32767 to 32767
- Singles letter variables A-Z
- 1-dimensional array support
- Strings are not supported  
+- This ROM-hosted implementation does not support disk access for
+  loading and saving programs.
+- Integer arithmetic, numbers -32767 to 32767
+- Singles letter variables A-Z
+- 1-dimensional array support
+- Strings are not supported

 ## Direct Commands

@ -494,7 +496,8 @@ Due to different platform processor speeds,  serials speeds and flow control cap

 See the ROMWBW Applications guide for additional information on performing upgrades.

- ## Console Options
+## Console Options
+
 Option ( C ) - Set Console Device

 Option ( S ) - Set Serial Device
@ -576,7 +579,7 @@ Can be used to verify if a ROM image has been transferred and flashed correctly.

 In Windows, right clicking on a file should also give you a context menu option CRC SHA which will allow you to select a CRC32 calculation to be done on the selected file.

-## Teraterm macro configuration 
+## Tera Term macro configuration 

 Macros are a useful tool for automatic common tasks. There are a number of instances where using macros to facilitate the update process could be worthwhile if you are:

@ -595,20 +598,21 @@ crc32file crc '\\desktop\users\phillip\documents\github\romwbw\binary\sbc_std_cu
 sprintf '0x%08x' crc
 messagebox inputstr 'crc32'
 ```
+
 ## Serial speed guidelines

 As identified in the introduction, there are limitations on serial speed depending on processor speed and flow control settings. Listed below are some of the results identified during testing.

 Platform / Configuration       | Processor Speed | Maximum Serial Speed
 -------------------------------|-----------------|---------------------
-Sbc-v2  uart no flow control   | 2mhz            | 9600
-sbc-v2  uart no flow control   | 4mhz            | 19200
-sbc-v2  uart no flow control   | 5mhz            | 19200
-sbc-v2  uart no flow control   | 8mhz            | 38400
-sbc-v2  uart no flow control   | 10mhz           | 38400
-sbc-v2  usb-fifo 2mhz+         |                 | n/a
-sbc-mk4 asci no flow control   | 18.432mhz       | 9600
-sbc-mk4 asci with flow control | 18.432mhz       | 38400
+SBC-V2  UART no flow control   | 2mhz            | 9600
+SBC-V2  UART no flow control   | 4mhz            | 19200
+SBC-V2  UART no flow control   | 5mhz            | 19200
+SBC-V2  UART no flow control   | 8mhz            | 38400
+SBC-V2  UART no flow control   | 10mhz           | 38400
+SBC-V2  USB-FIFO 2mhz+         |                 | n/a
+SBC-MK4 ASCI no flow control   | 18.432mhz       | 9600
+SBC-MK4 ASCI with flow control | 18.432mhz       | 38400

 The **Set Recommend Baud Rate** option in the Updater menu follows the following guidelines.

@ -623,9 +627,9 @@ These can be customized in the updater.asm source code in the CLKTBL table  if d
 Feedback to the ROMWBW developers on these guidelines would be appreciated.

 ## Notes:
-All testing was done with Teraterm x-modem, Forcing checksum mode using macros was found to give  the most reliable transfer.
-Partial writes can be completed with 39SF040 chips. Other chips require entire flash to be erased before being written.
-An SBC V2-005 MegaFlash or Z80 MBC required for 1mb flash support. The Updater assumes both chips are same type
-Failure handling has not been tested.
-Timing broadly calibrated on a Z80 SBC-v2
-Unabios not supported
+- All testing was done with Teraterm x-modem, Forcing checksum mode using macros was found to give  the most reliable transfer.
+- Partial writes can be completed with 39SF040 chips. Other chips require entire flash to be erased before being written.
+- An SBC V2-005 MegaFlash or Z80 MBC required for 1mb flash support. The Updater assumes both chips are same type
+- Failure handling has not been tested.
+- Timing broadly calibrated on a Z80 SBC-v2
+- UNA BIOS not supported
--- a/Source/Doc/ReadMe.md
+++ b/Source/Doc/ReadMe.md
@ -220,6 +220,8 @@ please let me know if I missed you!
 * Ladislau Szilagyi has contributed an enhanced version of
  CP/M Cowgol that leverages RomWBW memory banking.

+* Les Bird has contributed support for the NABU w/ Option Board
+
 Contributions of all kinds to RomWBW are very welcome.

 # Licensing
--- a/Source/Doc/UserGuide.md
+++ b/Source/Doc/UserGuide.md
@ -263,6 +263,7 @@ is discussed in [Customizing RomWBW].
 | [Duodyne Z80 System]^1^                                        | Duo     | DUO_std.rom           | 38400         |
 | [Heath H8 Z80 System]^10^                                      | H8      | HEATH_std.rom         | 115200        |
 | [EP Mini-ITX Z180]^11^                                         | RCBus?  | EPITX_std.rom         | 115200        |
+| [NABU w/ RomWBW Option Board]^10^                              | NABU    | NABU_std.rom          | 115200        |

 | ^1^Designed by Andrew Lynch
 | ^2^Designed by Sergey Kiselev
@ -630,6 +631,7 @@ prompt:
 | CP/M 2.2          | Digital Research CP/M 2.2 OS                                   |
 | Z-System          | ZSDOS 1.1 w/ ZCPR 1 (Enhanced CP/M compatible OS)              |
 | Forth             | Brad Rodriguez's ANSI compatible Forth language                |
+| BASIC             | Microsoft ROM BASIC                                            |
 | Tasty&nbsp;BASIC  | Dimitri Theuling's Tiny BASIC implementation                   |
 | Play              | A simple video game (requires ANSI terminal emulation)         |
 | Network&nbsp;Boot | Boot system via Wiznet MT011 device                            |
@ -649,9 +651,17 @@ in the ROM (CP/M 2.2 & Z-System) are described in the Operating Systems
 chapter of this document.

 In general, the command to exit any of these applications and restart
-the system is `BYE`. The exceptions are the Monitor which uses `B` and
+the system is `BYE`. The exceptions are the Monitor which uses `X` and
 Play which uses `Q`.

+**NOTE:** Of the ROM Applications, only the operating systems (CP/M and 
+Z-System) have the ability to interact with disk drives. So, other than 
+these 2 OSes, the ROM Applications do **not** have any way to save or 
+load data from peristent/disk storage.  For example, if you launch BASIC
+from the Boot Loader, you will not be able to save or load your 
+programs.  You will need to start an operating system first and then run
+BASIC in order to save or load programs.
+
 Two of the ROM Applications are, in fact, complete operating systems.
 Specifically, "CP/M 2.2" and "Z-System" are provided so that you can
 actually start either operating system directly from your ROM.  This
@ -1108,11 +1118,11 @@ system.

 The drive letter assignments **do not** change during an OS session 
 unless you use the `ASSIGN` command yourself to do it. Additionally, the
- assignments at boot will stay the same on each boot as long as you do 
+assignments at boot will stay the same on each boot as long as you do 
 not make changes to your hardware configuration. Note that the 
 assignments **are** dependent on the media currently inserted in hard 
 disk drives when the operating system is started. So, notice that if you
- insert or remove an SD Card, CF Card or USB Drive, the drive 
+insert or remove an SD Card, CF Card or USB Drive, the drive 
 assignments will change. Since drive letter assignments can change, you 
 must be careful when doing destructive things like using `CLRDIR` to 
 make sure the drive letter you use is referring to the desired media.
@ -1394,15 +1404,24 @@ filesystem format used is 8MB. This ensures any filesystem will be
 accessible to any of the operating systems.

 Since storage devices today are quite large, RomWBW implements a
-mechanism called slicing to allow up to 256 8MB filesystems on a
-single large storage device. This allows up to 2GB of usable space on
+mechanism called slicing to allow up to 256 8MB CP/M filesystems on a
+single large storage device.  To say it another way, the media is
+"sliced up" into many 8MB CP/M filesystems.  Each slice is a complete
+CP/M filesystem.  This allows up to 2GB of usable space on
 one media. You can think of slices as a way to refer to any of
-the first 256 8MB chunks of space on a single media.
+the first 256 8MB chunks of space on a single media.  Each chunk
+is a CP/M filesystem.
+
+Note that slices are **not** the same thing as a hard disk partition.
+In fact, these slices all live inside of a single hard disk partition.
+Normally, a RomWBW hard disk will have one partition (called the
+RomWBW partition) containing 64 slices.  Optionally, there may be
+a second partition which contains a FAT filesystem.  For now, we
+are just talking about the slices within the single RomWBW partition.

-Note that although you can use up to 256 slices per physical disk, this
-large number of slices is rarely used.  The recommended RomWBW disk
-layout provides for 64 slices which is more than enough for most
-use cases.
+Although you can use up to 256 slices per physical disk, this large 
+number of slices is rarely used.  The recommended RomWBW disk layout 
+provides for 64 slices which is more than enough for most use cases.

 Of course, the problem is that CP/M-like operating systems have only
 16 drive letters (A:-P:) available. Under the covers, RomWBW allows
@ -1438,22 +1457,28 @@ the same device/slice at the same time. Second, there must always be a
 drive assigned to A:. Any attempt to violate these rules will be blocked
 by the `ASSIGN` command.

+As you see, the name of a slice does not reference the hard disk 
+partition containing the slices.  Since there can only be a single 
+RomWBW partition containing slices on any disk, the partition is 
+determined automatically.
+
 In case this wasn't already clear, you **cannot** refer directly
 to slices using CP/M.  CP/M only understands drive letters, so
 to access a given slice, you must assign a drive letter to it first.

-While it may be obvious, you cannot use slices on any media less
-than 8MB in size. Specifically, you cannot slice RAM disks, ROM
-disks, floppy disks, etc.  All of these are considered to have a single
-slice and any attempt to ASSIGN a drive letter to a slice beyond that
-will result in an error message.
+While it may be obvious, you cannot use slices on any media less than 
+8MB in size. Specifically, you cannot slice RAM disks, ROM disks, floppy
+ disks, etc.  All of these are considered to have a single slice (slice 
+0) and any attempt to ASSIGN a drive letter to a slice beyond that will 
+fail and produce an error message.

 It is very important to understand that RomWBW slices are not
 individually created or allocated on your hard disk.  RomWBW uses a
-single, large chunk of space on your hard disk to contain the slices.
-You should think of slices as just an index into a sequential set of 8MB
-areas that exist in this large chunk of space.  The next section will
-go into more detail on how slices are located on your hard disk.
+single, large chunk of space (partition) on your hard disk to contain
+the slices. You should think of slices as just an index into a
+sequential set of 8MB areas that exist in this large chunk of space.
+The next section will go into more detail on how slices are located on
+your hard disk.

 Although you do not need to allocate slices individually, you do need to
 initialize each slice for CP/M to use it.  This is somewhat analogous
@ -1465,10 +1490,10 @@ absolutely sure you know what media and slice are assigned to that
 drive letter before using `CLRDIR` because CLRDIR will wipe out any
 pre-existing contents of the slice.

-**WARNING**: The `CLRDIR` application does not appear to check for
-disk errors when it runs.  If you attempt to run `CLRDIR` on a drive
-that is mapped to a slice that does not actually fit on the physical
-disk, it may behave erratically.
+**WARNING**: Earlier versions of the `CLRDIR` application does not 
+appear to check for disk errors when it runs.  If you attempt to run 
+`CLRDIR` on a drive that is mapped to a slice that does not actually fit
+on the physical disk, it may behave erratically.

 Here is an example of using `CLRDIR`.  In this example, the `ASSIGN`
 command is used to show the current drive letter assignments.  Then
@ -1488,10 +1513,10 @@ B>assign
   H:=IDE0:3

 B>clrdir G:
-CLRDIR Version 1.2 April 2020 by Max Scane
+CLRDIR Version 1.2B May 2024 by Max Scane

 Warning - this utility will overwrite the directory sectors of Drive: G
-Type Y to proceed, any key other key to exit. Y
+Type CAPITAL Y to proceed, any key other key to exit. Y
 Directory cleared.
 B>
 ```
@ -1695,9 +1720,9 @@ transferring your files over individually. You use your modern
 computer (Windows, Linux, MacOS) to write the disk image onto the
 disk media, then just move the media over to your system.

-The disk image files are found in the Binary directory of the
-distribution. Floppy disk images are prefixed with "fd_" and hard
-disk images are prefixed with either "hd512_" or "hd1k_" depending on the
+The disk image files are found in the Binary directory of the 
+distribution. Floppy disk images are prefixed with "fd_" and hard disk 
+images are prefixed with either "hd512_" or "hd1k_" depending on the 
 hard disk layout they are for.

 Each disk image has the complete set of normal applications and tools 
@ -1968,10 +1993,12 @@ custom hard disk image file, it will need to be written to the media
 using your modern computer.  Note that you **do not** run `CLRDIR` or 
 `SYSCOPY` on the slices that contain the data.  When using this method, 
 the disk will be partitioned and setup with 1 or more slices containing 
-ready-to-run bootable operating systems.
+ready-to-run bootable operating systems.  You **do** need to run
+`CLRDIR` and optionally `SYSCOPY` on slices that are not part of the
+image (slices beyond the ones included with the image).

 To write a hard disk image file onto your actual media (actual hard disk
- or CF/SD/USB Media), you need to use an image writing utility on your 
+or CF/SD/USB Media), you need to use an image writing utility on your 
 modern computer. Your modern computer will need to have an appropriate 
 interface or slot that accepts the media. To actually copy the image, 
 you can use the `dd` command on Linux or MacOS. On Windows, in the 
@ -2254,7 +2281,7 @@ significant improvements such as date/time stamping of files.

 Z-System is a somewhat ambiguous term because there are multiple 
 generations of this software.  RomWBW Z-System is a combination of both 
-ZCPR-DJ (the CCP) and ZSDOS 1.1 (the BDOS) when referring to Z-System.  
+ZCPR-DJ (the CCP) and ZSDOS 1.1 (the BDOS) when referring to Z-System. 
 The latest version of Z-System (ZCPR 3.4) is also provided with RomWBW 
 via the NZ-COM adaptation (see below).

@ -2469,7 +2496,7 @@ CP/M 3 and ZCPR 3.
 To create (or update) a ZPM3 boot drive, you must place `ZPMLDR.SYS` on 
 the system track of the disk.  You must also place `CPM3.SYS`, 
 `ZCCP.COM`, `ZINSTAL.ZPM`, and `STARTZPM.COM` on the target drive as 
-regular files.  Do **not** place CPM3.SYS on the boot track.  
+regular files.  Do **not** place CPM3.SYS on the boot track. 
 `ZPMLDR.SYS` chain loads `CPM3.SYS` which must exist as a regular file 
 on the disk.  Subsequently, `CPM3.SYS` loads `CCP.COM`.

@ -2548,9 +2575,9 @@ the QP/M components.  To do this, you can perform the following steps:

 1. Use RomWBW `SYSCOPY` to place the stock RomWBW CP/M OS image
   onto the system tracks of the QP/M boot disk:
-   
+
   `SYSCOPY A:=x:CPM.SYS`
-   
+
   where x is the drive letter of your ROM Disk.

 1. Run `QINSTALL` to overlay the QP/M OS components on your
@ -2708,11 +2735,11 @@ To boot into Fuzix:
  ```
  RCBus [RCZ180_nat_wbw] Boot Loader
  FP Switches = 0x00
-  
+
  Boot [H=Help]: 2
-  
+
  Booting Disk Unit 2, Slice 0, Sector 0x00000000...
-  
+
  Volume "Fuzix 126 Loader" [0xF200-0xF400, entry @ 0xF200]...
  FUZIX version 0.4
  Copyright (c) 1988-2002 by H.F.Bower, D.Braun, S.Nitschke, H.Peraza
@ -2741,13 +2768,13 @@ To boot into Fuzix:
  Enter new date:
  Current time is 13:30:24
  Enter new time:
-  
+
   ^ ^
   n n   Fuzix 0.4
   >@<
         Welcome to Fuzix
   m m
-  
+
  login:
  ```

@ -2756,7 +2783,7 @@ To boot into Fuzix:

  ```
  login: root
-  
+
  Welcome to FUZIX.
  #
  ```
@ -2840,7 +2867,7 @@ This application understands both FAT filesystems as well as CP/M filesystems.
  characters are **not permitted** in a CP/M filename:

  `< > . , ; : = ? * [ ] _ % | ( ) / \`
-  
+
  The FAT application does not auto-rename files when it encounters
  invalid filenames.  It will just issue an error and quit.
  Additionally, the error message is not very clear about the problem.
@ -2915,8 +2942,8 @@ computer and access it using `FAT` based on its RomWBW unit number.
 **WARNING**: Microsoft Windows will sometimes suggest reformatting 
 partitions that it does not recognize.  If you are prompted to format a 
 partition of your SD/CF/USB Media when inserting the card into a Windows
- computer, you probably want to select Cancel.
-  
+computer, you probably want to select Cancel.
+
 ## FAT Application Usage

 Complete instructions for the `FAT` application are found in $doc_apps$.
@ -3392,7 +3419,7 @@ The document is called "dri-cpnet.pdf".
 Under CP/M 2.2, you will start the networking client using the command 
 `CPNETLDR`.  Under CP/M 3, you use the command `NDOS3`. If that works, 
 you can map network drives as local drives using the `NETWORK` command.
-The `CPNETSTS` command is useful for displaying the current status.  
+The `CPNETSTS` command is useful for displaying the current status.
 Here is a sample session from CP/M 2.2:

 ```
@ -4183,6 +4210,8 @@ please let me know if I missed you!
 * Ladislau Szilagyi has contributed an enhanced version of
  CP/M Cowgol that leverages RomWBW memory banking.

+* Les Bird has contributed support for the NABU w/ Option Board
+
 Contributions of all kinds to RomWBW are very welcome.

 # Licensing
@ -5820,6 +5849,36 @@ S- MD: TYPE=RAM

 `\clearpage`{=latex}

+### NABU w/ RomWBW Option Board
+
+#### ROM Image File:  NABU_std.rom
+
+|                   |               |
+|-------------------|---------------|
+| Default CPU Speed | 3.580 MHz     |
+| Interrupts        | Mode 1        |
+| System Timer      | None          |
+| Serial Default    | 115200 Baud   |
+| Memory Manager    | Z2            |
+| ROM Size          | 512 KB        |
+| RAM Size          | 512 KB        |
+
+##### Supported Hardware (see [Appendix B - Device Summary]):
+
+- UART: MODE=NABU, IO=72
+- TMS: MODE=NABU, IO=160
+- MD: TYPE=RAM
+- MD: TYPE=ROM
+- PPIDE: IO=96, MASTER
+- PPIDE: IO=96, SLAVE
+- AY38910: MODE=NABU, IO=65, CLOCK=1789772 HZ
+
+##### Notes:
+
+- TMS video assumes F18A replacement for TMS9918
+
+`\clearpage`{=latex}
+
 ## Appendix B - Device Summary

 The table below briefly describes each of the possible devices that
--- a/Source/HBIOS/Bank
+++ b/Source/HBIOS/Bank
@ -27,7 +27,7 @@ Bank ID		Module		Start	Size
 0x04 - N	ROM Disk Data


-Typical ROM Bank Layout
+Typical ROM Bank Layout (512K)

 Bank ID         Usage
 -------         ------
@ -35,22 +35,43 @@ Bank ID         Usage
 0x01		ROM Loader, Monitor, ROM OSes
 0x02		ROM Applications
 0x03		Reserved
-0x04-0x0F	ROM Disk Banks
+0x04-0x0F	ROM Disk Banks (12)


-Typical RAM Bank Layout
+Standard RAM Bank Layout (512K)

 Bank ID         Usage
 -------         ------
 0x80            RomWBW HBIOS
-0x81-0x8B       RAM Disk Data
+0x81-0x88       RAM Disk Data (3)
+0x89-0x8B	App Banks (8)
 0x8C		CP/M 3 Buffers
 0x8D            CP/M 3 OS
 0x8E            User TPA
 0x8F            Common

+Large RAM Bank Layout (2048K)

-Typical ROMless Bank Layout
+Bank ID         Usage
+-------         ------
+0x80            RomWBW HBIOS
+0x81-0xB0       RAM Disk Data (30)
+0xB1-0xBB	App Banks (11)
+0xBC		CP/M 3 Buffers
+0x8D            CP/M 3 OS
+0x8E            User TPA
+0x8F            Common
+
+Tiny RAM Bank Layout (128K)
+
+Bank ID         Usage
+-------         ------
+0x80            RomWBW HBIOS
+0x81		CP/M 3 OS
+0x82            User TPA
+0x83            Common
+
+ROMless Standard Bank Layout (512K)

 Bank ID         Usage
 -------         ------
@ -58,7 +79,7 @@ Bank ID         Usage
 0x81		Loader, DbgMon, CP/M 2.2, ZSDOS
 0x82		ROM Apps
 0x83		More ROM Apps
-0x84-0x8B       RAM Disk Data
+0x84-0x8B       RAM Disk Data (8)
 0x8C		CP/M 3 Buffers
 0x8D            CP/M 3 OS
 0x8E            User TPA
--- a/Source/HBIOS/Build.cmd
+++ b/Source/HBIOS/Build.cmd
@ -50,6 +50,7 @@ echo.
 ::

 tasm -t80 -g3 -dCMD hbios_env.asm hbios_env.com hbios_env.lst || exit /b
+zxcc hbios_env
 zxcc hbios_env >hbios_env.cmd
 call hbios_env.cmd

@ -241,6 +242,7 @@ call Build S100 std || exit /b
 call Build DUO std || exit /b
 call Build HEATH std || exit /b
 call Build EPITX std || exit /b
+call Build NABU std || exit /b
 :: call Build MON std || exit /b

 goto :eof
--- a/Source/HBIOS/Build.ps1
+++ b/Source/HBIOS/Build.ps1
@ -27,7 +27,7 @@ $ErrorAction = 'Stop'
 # UNA BIOS is simply imbedded, it is not built here.
 #

-$PlatformListZ80 = "SBC", "MBC", "ZETA", "ZETA2", "RCZ80", "Z80RETRO", "DUO", "UNA", "HEATH", "MON"
+$PlatformListZ80 = "SBC", "MBC", "ZETA", "ZETA2", "RCZ80", "Z80RETRO", "DUO", "UNA", "HEATH", "MON", "NABU"
 $PlatformListZ180 = "N8", "MK4", "RCZ180", "SCZ180", "DYNO", "RPH", "S100", "EPITX"
 $PlatformListZ280 = "RCZ280"

--- a/Source/HBIOS/Build.sh
+++ b/Source/HBIOS/Build.sh
@ -50,6 +50,7 @@ if [ "${ROM_PLATFORM}" == "dist" ] ; then
 	ROM_PLATFORM="ZETA2"; ROM_CONFIG="std"; bash Build.sh
 	ROM_PLATFORM="HEATH"; ROM_CONFIG="std"; bash Build.sh
 	ROM_PLATFORM="EPITX"; ROM_CONFIG="std"; bash Build.sh
+	ROM_PLATFORM="NABU"; ROM_CONFIG="std"; bash Build.sh
 #	ROM_PLATFORM="MON"; ROM_CONFIG="std"; bash Build.sh
 	exit
 fi
--- a/Source/HBIOS/Config/DUO_std.asm
+++ b/Source/HBIOS/Config/DUO_std.asm
@ -31,7 +31,7 @@ CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
 INTMODE		.SET	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
 ;
-;;;DMAENABLE	.SET	TRUE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+DMAENABLE	.SET	TRUE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 ;
 BATCOND		.SET	TRUE		; ENABLE LOW BATTERY WARNING MESSAGE
 ;
@ -44,4 +44,8 @@ MDFFENABLE	.SET	FALSE		; MD: ENABLE FLASH FILE SYSTEM
 ;
 UARTINTS	.SET	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 ;
-ESPENABLE	.SET	TRUE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+;
+CHENABLE	.SET	TRUE		; CH: ENABLE CH375/376 USB SUPPORT
+;
+ESPENABLE	.SET	FALSE 		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
--- a/Source/HBIOS/Config/NABU_std.asm
+++ b/Source/HBIOS/Config/NABU_std.asm
@ -0,0 +1,32 @@
+;
+;==================================================================================================
+;   NABU Z80 STANDARD CONFIGURATION
+;==================================================================================================
+;
+; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
+; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
+; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
+; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
+; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
+; YOUR FILE IN THE BUILD PROCESS.
+;
+; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
+; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
+; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
+; SETTINGS.
+;
+; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
+; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
+; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
+; DIRECTORIES ABOVE THIS ONE).
+;
+#DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
+;
+#include "cfg_nabu.asm"
+;
+CRTACT		.SET	TRUE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+;
+TMSMODE		.SET	TMSMODE_NABU80	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO|NABU40|NABU80]
+
--- a/Source/HBIOS/Config/SCZ180_sc700.asm
+++ b/Source/HBIOS/Config/SCZ180_sc700.asm
@ -36,6 +36,7 @@ Z180_MEMWAIT	.SET	0		; Z180: MEMORY WAIT STATES (0-3)
 Z180_IOWAIT	.SET	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
 ;
 LEDENABLE	.SET	TRUE		; ENABLE STATUS LED (SINGLE LED)
+LEDMODE		.SET	LEDMODE_STD	; LEDMODE_[STD|SC|RTC|NABU]
 LEDPORT		.SET	$0E		; STATUS LED PORT ADDRESS
 ;
 FPLED_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL LEDS
--- a/Source/HBIOS/acia.asm
+++ b/Source/HBIOS/acia.asm
@ -705,12 +705,12 @@ ACIA0_CFG:
        .DW     (ACIA0CLK / ACIA0DIV) & $FFFF   ; CLOCK FREQ AS
        .DW     (ACIA0CLK / ACIA0DIV) >> 16     ; ... DWORD VALUE
 ;
-	.ECHO	"ACIA: IO="
-	.ECHO	ACIA0BASE
+	DEVECHO	"ACIA: IO="
+	DEVECHO	ACIA0BASE
 #IF (INTMODE == 1)
-	.ECHO	", INTERRUPTS ENABLED"
+	DEVECHO	", INTERRUPTS ENABLED"
 #ENDIF
-	.ECHO	"\n"
+	DEVECHO	"\n"
 ;
 ACIA_CFGSIZ     .EQU    $ - ACIA_CFG    ; SIZE OF ONE CFG TABLE ENTRY
 ;
@ -728,12 +728,12 @@ ACIA1_CFG:
        .DW     (ACIA1CLK / ACIA1DIV) & $FFFF   ; CLOCK FREQ AS
        .DW     (ACIA1CLK / ACIA1DIV) >> 16     ; ... DWORD VALUE
 ;
-	.ECHO	"ACIA: IO="
-	.ECHO	ACIA1BASE
+	DEVECHO	"ACIA: IO="
+	DEVECHO	ACIA1BASE
 #IF (INTMODE == 1)
-	.ECHO	", INTERRUPTS ENABLED"
+	DEVECHO	", INTERRUPTS ENABLED"
 #ENDIF
-	.ECHO	"\n"
+	DEVECHO	"\n"
 ;
 #ENDIF
 ;
--- a/Source/HBIOS/ansi.asm
+++ b/Source/HBIOS/ansi.asm
@ -149,8 +149,20 @@ ANSI_IN1:	; PERFORM ACTUAL KEYBOARD INPUT
 	LD	B,BF_VDAKRD	; SET FUNCTION TO KEYBOARD READ
 	CALL	ANSI_VDADISP	; CALL VDA DISPATCHER
 	LD	A,E		; CHARACTER READ INTO A
+;
+; THE NABU USES KEYBOARD CODES TO REPORT JOYSTICK ACTIVITY USING
+; VALUES $A0-$BF.  NORMALLY, WE WOULD PROCESS ANYTHING OVER $80 AS
+; A SPECIAL CHAR AND WIND UP IGNORING $80-$DF.  FOR NABU, WE ALLOW
+; ANYTHING LESS THAN $E0 TO BE RETURNED TO THE APPLICATION FOR
+; JOYSTICK PROCESSING.
+;
+#IF (PLATFORM == PLT_NABU)
+	CP	$E0		; >= $E0 IS SPECIAL KEY
+	JR	NC,ANSI_IN2	; HANDLE SPECIAL KEY
+#ELSE
 	BIT	7,A		; TEST HIGH BIT
 	JR	NZ,ANSI_IN2	; HANDLE $80 OR HIGHER AS SPECIAL CHAR
+#ENDIF
 	XOR	A		; OTHERWISE, SIGNAL SUCCESS
 	RET			; AND RETURN THE KEY 
 ;
--- a/Source/HBIOS/asci.asm
+++ b/Source/HBIOS/asci.asm
@ -618,7 +618,7 @@ ASCI_DETECT:
 ; Z180 DIVISOR IS ALWAYS A FACTOR OF 160
 ;
 ; CNTLB=	XXPXDSSS
-; FAILSAVE = 	00100000
+; FAILSAFE = 	00100000
 ;
 ; PS (PRESCALE): 0=/10, 1=/30
 ; DR (DIVIDE RATIO): 0=/16, 1=/64
@ -837,12 +837,12 @@ ASCI1_CFG:
 	.DW	ASCI1CFG		; LINE CONFIGURATION
 	.DW	ASCI1_RCVBUF		; POINTER TO RCV BUFFER STRUCT
 ;
-	.ECHO	"ASCI: IO="
-	.ECHO	ASCI1_BASE
+	DEVECHO	"ASCI: IO="
+	DEVECHO	ASCI1_BASE
 #IF ((ASCIINTS) & (INTMODE >0))
-	.ECHO	", INTERRUPTS ENABLED"
+	DEVECHO	", INTERRUPTS ENABLED"
 #ENDIF
-	.ECHO	"\n"
+	DEVECHO	"\n"
 ;
 ASCI_CFGSIZ	.EQU	$ - ASCI_CFG	; SIZE OF ONE CFG TABLE ENTRY
 ;
@ -855,12 +855,12 @@ ASCI0_CFG:
 	.DW	ASCI0CFG		; LINE CONFIGURATION
 	.DW	ASCI0_RCVBUF		; POINTER TO RCV BUFFER STRUCT
 ;
-	.ECHO	"ASCI: IO="
-	.ECHO	ASCI0_BASE
+	DEVECHO	"ASCI: IO="
+	DEVECHO	ASCI0_BASE
 #IF ((ASCIINTS) & (INTMODE >0))
-	.ECHO	", INTERRUPTS ENABLED"
+	DEVECHO	", INTERRUPTS ENABLED"
 #ENDIF
-	.ECHO	"\n"
+	DEVECHO	"\n"
 ;
 #ELSE
 ;
@ -873,12 +873,12 @@ ASCI0_CFG:
 	.DW	ASCI0CFG		; LINE CONFIGURATION
 	.DW	ASCI0_RCVBUF		; POINTER TO RCV BUFFER STRUCT
 ;
-	.ECHO	"ASCI: IO="
-	.ECHO	ASCI0_BASE
+	DEVECHO	"ASCI: IO="
+	DEVECHO	ASCI0_BASE
 #IF ((ASCIINTS) & (INTMODE >0))
-	.ECHO	", INTERRUPTS ENABLED"
+	DEVECHO	", INTERRUPTS ENABLED"
 #ENDIF
-	.ECHO	"\n"
+	DEVECHO	"\n"
 ;
 ASCI_CFGSIZ	.EQU	$ - ASCI_CFG	; SIZE OF ONE CFG TABLE ENTRY
 ;
@ -891,12 +891,12 @@ ASCI1_CFG:
 	.DW	ASCI1CFG		; LINE CONFIGURATION
 	.DW	ASCI1_RCVBUF		; POINTER TO RCV BUFFER STRUCT
 ;
-	.ECHO	"ASCI: IO="
-	.ECHO	ASCI1_BASE
+	DEVECHO	"ASCI: IO="
+	DEVECHO	ASCI1_BASE
 #IF ((ASCIINTS) & (INTMODE > 0))
-	.ECHO	", INTERRUPTS ENABLED"
+	DEVECHO	", INTERRUPTS ENABLED"
 #ENDIF
-	.ECHO	"\n"
+	DEVECHO	"\n"
 ;
 #ENDIF
 ;
--- a/Source/HBIOS/ay38910.asm
+++ b/Source/HBIOS/ay38910.asm
@ -21,14 +21,14 @@
 ;
 AY_RCSND	.EQU	0		; 0 = EB MODULE, 1=MF MODULE
 ;
-	.ECHO	"AY38910: MODE="
+	DEVECHO	"AY38910: MODE="
 ;
 #IF (AYMODE == AYMODE_SCG)
 AY_RSEL		.EQU	$9A
 AY_RDAT		.EQU	$9B
 AY_RIN		.EQU	AY_RSEL
 AY_ACR		.EQU	$9C
-		.ECHO	"SCG"
+		DEVECHO	"SCG"
 #ENDIF
 ;
 #IF (AYMODE == AYMODE_N8)
@ -36,35 +36,35 @@ AY_RSEL		.EQU	$9C
 AY_RDAT		.EQU	$9D
 AY_RIN		.EQU	AY_RSEL
 AY_ACR		.EQU	N8_ACR
-		.ECHO	"N8"
+		DEVECHO	"N8"
 #ENDIF
 ;
 #IF (AYMODE == AYMODE_RCZ80)
 AY_RSEL		.EQU	$D8
 AY_RDAT		.EQU	$D0
 AY_RIN		.EQU	AY_RSEL+AY_RCSND
-		.ECHO	"RCZ80"
+		DEVECHO	"RCZ80"
 #ENDIF
 ;
 #IF (AYMODE == AYMODE_RCZ180)
 AY_RSEL		.EQU	$68
 AY_RDAT		.EQU	$60
 AY_RIN		.EQU	AY_RSEL+AY_RCSND
-		.ECHO	"RCZ180"
+		DEVECHO	"RCZ180"
 #ENDIF
 ;
 #IF (AYMODE == AYMODE_MSX)
 AY_RSEL		.EQU	$A0
 AY_RDAT		.EQU	$A1
 AY_RIN		.EQU	$A2
-		.ECHO	"MSX"
+		DEVECHO	"MSX"
 #ENDIF
 ;
 #IF (AYMODE == AYMODE_LINC)
 AY_RSEL		.EQU	$33
 AY_RDAT		.EQU	$32
 AY_RIN		.EQU	$32
-		.ECHO	"LINC"
+		DEVECHO	"LINC"
 #ENDIF
 ;
 #IF (AYMODE == AYMODE_MBC)
@ -72,7 +72,7 @@ AY_RSEL		.EQU	$A0
 AY_RDAT		.EQU	$A1
 AY_RIN		.EQU	AY_RSEL
 AY_ACR		.EQU	$A2
-		.ECHO	"MBC"
+		DEVECHO	"MBC"
 #ENDIF
 ;
 #IF (AYMODE == AYMODE_DUO)
@ -80,14 +80,21 @@ AY_RSEL		.EQU	$A4
 AY_RDAT		.EQU	$A5
 AY_RIN		.EQU	AY_RSEL
 AY_ACR		.EQU	$A6
-		.ECHO	"DUO"
+		DEVECHO	"DUO"
 #ENDIF
 ;
-	.ECHO	", IO="
-	.ECHO	AY_RSEL
-	.ECHO	", CLOCK="
-	.ECHO	AY_CLK
-	.ECHO	" HZ\n"
+#IF (AYMODE == AYMODE_NABU)
+AY_RSEL		.EQU	$41
+AY_RDAT		.EQU	$40
+AY_RIN		.EQU	$40
+		DEVECHO	"NABU"
+#ENDIF
+;
+	DEVECHO	", IO="
+	DEVECHO	AY_RSEL
+	DEVECHO	", CLOCK="
+	DEVECHO	AY_CLK
+	DEVECHO	" HZ\n"
 ;
 ;======================================================================
 ;
@ -271,8 +278,14 @@ AY_TIMTIK	.DB	0		; COUNT DOWN TO FINISH BOOT BEEP
 ;======================================================================
 ;
 AY_INIT:
+#IF (AYMODE == AYMODE_NABU)
+	; I/O B=INPUT, I/O A=OUTPUT, NOISE CHANNEL C, B, A DISABLE, TONE CHANNEL C, B, A ENABLE
+	LD	DE,(AY_R7ENAB*256)+$78	; SET MIXER CONTROL / IO ENABLE.  $78 - 01 111 000
+#ELSE
+	; I/O PORTS = OUTPUT, NOISE CHANNEL C, B, A DISABLE, TONE CHANNEL C, B, A ENABLE
 	LD	DE,(AY_R7ENAB*256)+$F8	; SET MIXER CONTROL / IO ENABLE.  $F8 - 11 111 000
-	JP	AY_WRTPSG		; I/O PORTS = OUTPUT, NOISE CHANNEL C, B, A DISABLE, TONE CHANNEL C, B, A ENABLE
+#ENDIF
+	JP	AY_WRTPSG		
 ;
 AY_CHKREDY:
 	LD	A, (AY_READY)
--- a/Source/HBIOS/bqrtc.asm
+++ b/Source/HBIOS/bqrtc.asm
@ -91,9 +91,9 @@ BQRTC_UTI	.EQU	%00001000

 BQRTC_BUFSIZE	.EQU	6		; 6 BYTE BUFFER (YYMMDDHHMMSS)

-		.ECHO	"BQRTC: IO="
-		.ECHO	BQRTC_BASE
-		.ECHO	"\n"
+		DEVECHO	"BQRTC: IO="
+		DEVECHO	BQRTC_BASE
+		DEVECHO	"\n"

 ; RTC Device Initialization Entry

--- a/Source/HBIOS/cfg_duo.asm
+++ b/Source/HBIOS/cfg_duo.asm
@ -78,7 +78,7 @@ FPSW_INV	.EQU	FALSE		; FP: SWITCH BITS ARE INVERTED
 DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
 ;
 LEDENABLE	.EQU	TRUE		; ENABLES STATUS LED
-LEDMODE		.EQU	LEDMODE_RTC	; LEDMODE_[STD|RTC]
+LEDMODE		.EQU	LEDMODE_RTC	; LEDMODE_[STD|SC|RTC|NABU]
 LEDPORT		.EQU	RTCIO		; STATUS LED PORT ADDRESS
 LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
 ;
@ -131,7 +131,7 @@ UARTOSC		.EQU	7372800		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
 UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
-UARTSBC		.EQU	TRUE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
+UARTSBC		.EQU	TRUE		; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
 UARTAUX		.EQU	TRUE		; UART: AUTO-DETECT AUX UART
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
@ -168,7 +168,7 @@ CVDUMODE	.EQU	CVDUMODE_MBC	; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC]
 CVDUMON		.EQU	CVDUMON_CGA	; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
 GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.EQU	TRUE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_DUO	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO]
+TMSMODE		.EQU	TMSMODE_DUO	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO|NABU40|NABU80]
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VGASIZ		.EQU	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
@ -237,7 +237,7 @@ SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 SDMTSWAP	.EQU	TRUE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
-CHENABLE	.EQU	TRUE		; CH: ENABLE CH375/376 USB SUPPORT
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
 CHTRACE		.EQU	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 CHUSBTRACE	.EQU	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 CHSDTRACE	.EQU	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
@ -305,14 +305,14 @@ PIOSBASE	.EQU	$60		; PIO: PIO REGISTERS BASE ADR FOR SBC PPI
 UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
 UFBASE		.EQU	$0C		; UF: REGISTERS BASE ADR
 ;
-SN76489ENABLE	.EQU	TRUE		; SN: ENABLE SN76489 SOUND DRIVER
+SN76489ENABLE	.EQU	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
 AUDIOTRACE	.EQU	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
 SN7CLK		.EQU	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
 SNMODE		.EQU	SNMODE_DUO	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO]
 ;
 AY38910ENABLE	.EQU	TRUE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.EQU	AYMODE_DUO	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO]
+AYMODE		.EQU	AYMODE_DUO	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
 ;
 SPKENABLE	.EQU	TRUE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
--- a/Source/HBIOS/cfg_dyno.asm
+++ b/Source/HBIOS/cfg_dyno.asm
@ -80,7 +80,7 @@ FPSW_INV	.EQU	FALSE		; FP: SWITCH BITS ARE INVERTED
 DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
 ;
 LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED (SINGLE LED)
-LEDMODE		.EQU	LEDMODE_STD	; LEDMODE_[STD|RTC]
+LEDMODE		.EQU	LEDMODE_STD	; LEDMODE_[STD|SC|RTC|NABU]
 LEDPORT		.EQU	$0E		; STATUS LED PORT ADDRESS
 LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
 ;
@ -139,7 +139,7 @@ UARTENABLE	.EQU	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
 UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG | SER_RTS	; UART: LINE CONFIG FOR UART PORTS
-UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
+UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
 UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
@ -186,7 +186,7 @@ VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
 CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
 GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO]
+TMSMODE		.EQU	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO|NABU40|NABU80]
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
@ -291,7 +291,7 @@ SNMODE		.EQU	SNMODE_NONE	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
 ;
 AY38910ENABLE	.EQU	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.EQU	AYMODE_NONE	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO]
+AYMODE		.EQU	AYMODE_NONE	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
 ;
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
--- a/Source/HBIOS/cfg_epitx.asm
+++ b/Source/HBIOS/cfg_epitx.asm
@ -81,7 +81,7 @@ FPSW_INV	.EQU	FALSE		; FP: SWITCH BITS ARE INVERTED
 DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
 ;
 LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED (SINGLE LED)
-LEDMODE		.EQU	LEDMODE_STD	; LEDMODE_[STD|RTC]
+LEDMODE		.EQU	LEDMODE_STD	; LEDMODE_[STD|SC|RTC|NABU]
 LEDPORT		.EQU	$0E		; STATUS LED PORT ADDRESS
 LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
 ;
@ -141,7 +141,7 @@ UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
 UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG | SER_RTS	; UART: LINE CONFIG FOR UART PORTS
-UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
+UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
 UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
@ -188,7 +188,7 @@ VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
 CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
 GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO]
+TMSMODE		.EQU	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO|NABU40|NABU80]
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
@ -323,7 +323,7 @@ SNMODE		.EQU	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
 ;
 AY38910ENABLE	.EQU	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.EQU	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO]
+AYMODE		.EQU	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
 ;
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
--- a/Source/HBIOS/cfg_heath.asm
+++ b/Source/HBIOS/cfg_heath.asm
@ -80,7 +80,7 @@ FPSW_INV	.EQU	FALSE		; FP: SWITCH BITS ARE INVERTED
 DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
 ;
 LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED (SINGLE LED)
-LEDMODE		.EQU	LEDMODE_STD	; LEDMODE_[STD|RTC]
+LEDMODE		.EQU	LEDMODE_SC	; LEDMODE_[STD|SC|RTC|NABU]
 LEDPORT		.EQU	$0E		; STATUS LED PORT ADDRESS
 LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
 ;
@ -139,7 +139,7 @@ UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
 UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG | SER_RTS	; UART: LINE CONFIG FOR UART PORTS
-UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
+UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
 UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
@ -191,7 +191,7 @@ VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
 CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
 GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO]
+TMSMODE		.EQU	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO|NABU40|NABU80]
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
@ -316,7 +316,7 @@ SNMODE		.EQU	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
 ;
 AY38910ENABLE	.EQU	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.EQU	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO]
+AYMODE		.EQU	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
 ;
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
--- a/Source/HBIOS/cfg_master.asm
+++ b/Source/HBIOS/cfg_master.asm
@ -109,7 +109,7 @@ FPSW_INV	.EQU	FALSE		; FP: SWITCH BITS ARE INVERTED
 DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
 ;
 LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED (SINGLE LED)
-LEDMODE		.EQU	LEDMODE_STD	; LEDMODE_[STD|RTC]
+LEDMODE		.EQU	LEDMODE_STD	; LEDMODE_[STD|SC|RTC|NABU]
 LEDPORT		.EQU	$0E		; STATUS LED PORT ADDRESS
 LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
 ;
@ -169,7 +169,7 @@ UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
 UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
-UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
+UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
 UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
@ -236,7 +236,7 @@ GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 GDCMODE		.EQU	GDCMODE_RPH	; GDC: GDC MODE: GDCMODE_[NONE|ECB|RPH]
 GDCMON		.EQU	GDCMON_EGA      ; GDC: GDC MONITOR SETUP: GDCMON_[NONE|CGA|EGA]
 TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_NONE	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO]
+TMSMODE		.EQU	TMSMODE_NONE	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO|NABU40|NABU80]
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VGASIZ		.EQU	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
@ -383,7 +383,7 @@ SNMODE		.EQU	SNMODE_NONE	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
 ;
 AY38910ENABLE	.EQU	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.EQU	AYMODE_NONE	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO]
+AYMODE		.EQU	AYMODE_NONE	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
 ;
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
--- a/Source/HBIOS/cfg_mbc.asm
+++ b/Source/HBIOS/cfg_mbc.asm
@ -75,7 +75,7 @@ FPSW_INV	.EQU	FALSE		; FP: SWITCH BITS ARE INVERTED
 DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
 ;
 LEDENABLE	.EQU	TRUE		; ENABLES STATUS LED
-LEDMODE		.EQU	LEDMODE_RTC	; LEDMODE_[STD|RTC]
+LEDMODE		.EQU	LEDMODE_RTC	; LEDMODE_[STD|SC|RTC|NABU]
 LEDPORT		.EQU	RTCIO		; STATUS LED PORT ADDRESS
 LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
 ;
@ -128,7 +128,7 @@ UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
 UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
-UARTSBC		.EQU	TRUE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
+UARTSBC		.EQU	TRUE		; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
 UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
@ -165,7 +165,7 @@ CVDUMODE	.EQU	CVDUMODE_MBC	; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC]
 CVDUMON		.EQU	CVDUMON_CGA	; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
 GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.EQU	TRUE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_MBC	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO]
+TMSMODE		.EQU	TMSMODE_MBC	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO|NABU40|NABU80]
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VGASIZ		.EQU	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
@ -299,7 +299,7 @@ SNMODE		.EQU	SNMODE_NONE	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
 ;
 AY38910ENABLE	.EQU	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.EQU	AYMODE_MBC	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO]
+AYMODE		.EQU	AYMODE_MBC	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
 ;
 SPKENABLE	.EQU	TRUE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
--- a/Source/HBIOS/cfg_mk4.asm
+++ b/Source/HBIOS/cfg_mk4.asm
@ -80,7 +80,7 @@ FPSW_INV	.EQU	FALSE		; FP: SWITCH BITS ARE INVERTED
 DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
 ;
 LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED (SINGLE LED)
-LEDMODE		.EQU	LEDMODE_STD	; LEDMODE_[STD|RTC]
+LEDMODE		.EQU	LEDMODE_STD	; LEDMODE_[STD|SC|RTC|NABU]
 LEDPORT		.EQU	$0E		; STATUS LED PORT ADDRESS
 LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
 ;
@ -133,7 +133,7 @@ UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
 UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
-UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
+UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
 UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
 UARTCAS		.EQU	TRUE		; UART: AUTO-DETECT ECB CASSETTE UART
@ -175,7 +175,7 @@ CVDUMODE	.EQU	CVDUMODE_ECB	; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC]
 CVDUMON		.EQU	CVDUMON_EGA	; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
 GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_SCG	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO]
+TMSMODE		.EQU	TMSMODE_SCG	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO|NABU40|NABU80]
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VGASIZ		.EQU	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
@ -295,7 +295,7 @@ SNMODE		.EQU	SNMODE_VGM	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
 ;
 AY38910ENABLE	.EQU	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.EQU	AYMODE_SCG	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO]
+AYMODE		.EQU	AYMODE_SCG	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
 ;
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
--- a/Source/HBIOS/cfg_mon.asm
+++ b/Source/HBIOS/cfg_mon.asm
@ -75,7 +75,7 @@ FPSW_INV	.EQU	FALSE		; FP: SWITCH BITS ARE INVERTED
 DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
 ;
 LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED (SINGLE LED)
-LEDMODE		.EQU	LEDMODE_STD	; LEDMODE_[STD|RTC]
+LEDMODE		.EQU	LEDMODE_STD	; LEDMODE_[STD|SC|RTC|NABU]
 LEDPORT		.EQU	$0E		; STATUS LED PORT ADDRESS
 LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
 ;
@ -134,7 +134,7 @@ UARTENABLE	.EQU	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
 UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG | SER_RTS	; UART: LINE CONFIG FOR UART PORTS
-UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
+UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
 UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
@ -186,7 +186,7 @@ VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
 CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
 GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO]
+TMSMODE		.EQU	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO|NABU40|NABU80]
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
@ -321,7 +321,7 @@ SNMODE		.EQU	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
 ;
 AY38910ENABLE	.EQU	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.EQU	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO]
+AYMODE		.EQU	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
 ;
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
--- a/Source/HBIOS/cfg_n8.asm
+++ b/Source/HBIOS/cfg_n8.asm
@ -82,7 +82,7 @@ FPSW_INV	.EQU	FALSE		; FP: SWITCH BITS ARE INVERTED
 DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
 ;
 LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED
-LEDMODE		.EQU	LEDMODE_RTC	; LEDMODE_[STD|RTC]
+LEDMODE		.EQU	LEDMODE_RTC	; LEDMODE_[STD|SC|RTC|NABU]
 LEDPORT		.EQU	RTCIO		; STATUS LED PORT ADDRESS
 LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
 ;
@ -135,7 +135,7 @@ UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
 UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
-UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
+UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
 UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
 UARTCAS		.EQU	TRUE		; UART: AUTO-DETECT ECB CASSETTE UART
@ -177,7 +177,7 @@ CVDUMODE	.EQU	CVDUMODE_ECB	; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC]
 CVDUMON		.EQU	CVDUMON_EGA	; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
 GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.EQU	TRUE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_N8	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO]
+TMSMODE		.EQU	TMSMODE_N8	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO|NABU40|NABU80]
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VGASIZ		.EQU	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
@ -288,7 +288,7 @@ SNMODE		.EQU	SNMODE_VGM	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
 ;
 AY38910ENABLE	.EQU	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.EQU	AYMODE_N8	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO]
+AYMODE		.EQU	AYMODE_N8	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
 ;
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
--- a/Source/HBIOS/cfg_nabu.asm
+++ b/Source/HBIOS/cfg_nabu.asm
@ -0,0 +1,338 @@
+;
+;==================================================================================================
+;   ROMWBW 3.X CONFIGURATION DEFAULTS FOR NABU Z80 W/ OPTION BOARD
+;==================================================================================================
+;
+; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD, YOU SHOULD
+; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
+; UNDER THIS DIRECTORY.
+;
+; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
+; FOR THE PLATFORM.
+;
+#DEFINE PLATFORM_NAME "NABU Personal Computer", " [", CONFIG, "]"
+;
+#INCLUDE "hbios.inc"
+;
+PLATFORM	.EQU	PLT_NABU	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
+CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
+BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
+BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
+HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
+USELZSA2	.EQU	TRUE		; ENABLE FONT COMPRESSION
+TICKFREQ	.EQU	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
+;
+BOOT_TIMEOUT	.EQU	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
+BOOT_DELAY	.EQU	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
+AUTOCON		.EQU	TRUE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
+;
+CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
+CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
+CPUOSC		.EQU	3580000		; CPU OSC FREQ IN MHZ
+INTMODE		.EQU	1		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
+DEFSERCFG	.EQU	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+;
+RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
+APP_BNKS	.EQU	$FF		; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
+MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
+MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_3	.EQU	$7B		; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
+MPGENA		.EQU	$7C		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
+;
+RTCIO		.EQU	$C0		; RTC LATCH REGISTER ADR
+;
+KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT
+KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
+;
+CTCENABLE	.EQU	FALSE		; ENABLE ZILOG CTC SUPPORT
+CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
+CTCBASE		.EQU	$88		; CTC BASE I/O ADDRESS
+CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
+CTCMODE		.EQU	CTCMODE_TIM16	; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
+CTCPRE		.EQU	256		; PRESCALE CONSTANT (1-256)
+CTCPRECH	.EQU	2		; PRESCALE CHANNEL (0-3)
+CTCTIMCH	.EQU	3		; TIMER CHANNEL (0-3)
+CTCOSC		.EQU	CPUOSC		; CTC CLOCK FREQUENCY
+;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
+EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
+;
+SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
+SKZDIV		.EQU	DIV_1		; UART CLK (CLK2) DIVIDER FOR Z80-512K
+;
+WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
+WDOGIO		.EQU	$6E		; WATCHDOG REGISTER ADR
+;
+FPLED_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL LEDS
+FPLED_IO	.EQU	$00		; FP: PORT ADDRESS FOR FP LEDS
+FPLED_INV	.EQU	FALSE		; FP: LED BITS ARE INVERTED
+FPLED_DSKACT	.EQU	FALSE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
+FPSW_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
+FPSW_IO		.EQU	$00		; FP: PORT ADDRESS FOR FP SWITCHES
+FPSW_INV	.EQU	FALSE		; FP: SWITCH BITS ARE INVERTED
+;
+DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
+;
+LEDENABLE	.EQU	TRUE		; ENABLES STATUS LED (SINGLE LED)
+LEDMODE		.EQU	LEDMODE_NABU	; LEDMODE_[STD|SC|RTC|NABU]
+LEDPORT		.EQU	$00		; STATUS LED PORT ADDRESS
+LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
+;
+DSKYENABLE	.EQU	FALSE		; ENABLES DSKY FUNCTIONALITY
+DSKYDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
+ICMENABLE	.EQU	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
+ICMPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF ICM PPI
+PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
+PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
+PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
+;
+BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
+SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
+CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
+VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+ANSITRACE	.EQU	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKTRACE	.EQU	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+KBDTRACE	.EQU	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+KBDKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+PPKKBLOUT	.EQU	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
+MKYENABLE	.EQU	FALSE		; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
+MKYKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+;
+DSRTCENABLE	.EQU	FALSE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
+DSRTCCHG	.EQU	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
+;
+DS1501RTCENABLE	.EQU	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
+DS1501RTC_BASE	.EQU	$50		; DS1501RTC: I/O BASE ADDRESS
+;
+BQRTCENABLE	.EQU	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
+BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
+;
+INTRTCENABLE	.EQU	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
+;
+RP5RTCENABLE	.EQU	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+;
+HTIMENABLE	.EQU	FALSE		; ENABLE SIMH TIMER SUPPORT
+SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
+;
+DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
+DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
+;
+DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
+DUARTCNT	.EQU	1		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
+DUART0BASE	.EQU	$A0		; DUART 0: BASE ADDRESS OF CHIP
+DUART0ACFG	.EQU	DEFSERCFG	; DUART 0A: SERIAL LINE CONFIG
+DUART0BCFG	.EQU	DEFSERCFG	; DUART 0B: SERIAL LINE CONFIG
+DUART1BASE	.EQU	$40		; DUART 1: BASE ADDRESS OF CHIP
+DUART1ACFG	.EQU	DEFSERCFG	; DUART 1A: SERIAL LINE CONFIG
+DUART1BCFG	.EQU	DEFSERCFG	; DUART 1B: SERIAL LINE CONFIG
+;
+UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
+UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
+UARTCFG		.EQU	DEFSERCFG | SER_RTS	; UART: LINE CONFIG FOR UART PORTS
+UARTSBC		.EQU	TRUE		; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
+UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
+UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
+UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
+UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
+UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
+UARTRC		.EQU	FALSE		; UART: AUTO-DETECT RC UART
+UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
+;
+ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+;
+Z2UENABLE	.EQU	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
+;
+ACIAENABLE	.EQU	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+ACIADEBUG	.EQU	FALSE		; ACIA: ENABLE DEBUG OUTPUT
+ACIACNT		.EQU	1		; ACIA: NUMBER OF CHIPS TO DETECT (1-2)
+ACIA0BASE	.EQU	$80		; ACIA 0: REGISTERS BASE ADR
+ACIA0CLK	.EQU	CPUOSC		; ACIA 0: OSC FREQ IN HZ
+ACIA0DIV	.EQU	1		; ACIA 0: SERIAL CLOCK DIVIDER
+ACIA0CFG	.EQU	DEFSERCFG	; ACIA 0: SERIAL LINE CONFIG  (SEE STD.ASM)
+ACIA1BASE	.EQU	$40		; ACIA 1: REGISTERS BASE ADR
+ACIA1CLK	.EQU	CPUOSC		; ACIA 1: OSC FREQ IN HZ
+ACIA1DIV	.EQU	1		; ACIA 1: SERIAL CLOCK DIVIDER
+ACIA1CFG	.EQU	DEFSERCFG	; ACIA 1: SERIAL LINE CONFIG  (SEE STD.ASM)
+;
+SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
+SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
+SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
+SIO0ACLK	.EQU	CPUOSC		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0ACFG	.EQU	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
+SIO0ACTCC	.EQU	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO0BCLK	.EQU	CPUOSC		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0BCFG	.EQU	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
+SIO0BCTCC	.EQU	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO1BASE	.EQU	$84		; SIO 1: REGISTERS BASE ADR
+SIO1ACLK	.EQU	CPUOSC		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO1ACFG	.EQU	DEFSERCFG	; SIO 1A: SERIAL LINE CONFIG
+SIO1ACTCC	.EQU	-1		; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO1BCLK	.EQU	CPUOSC		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO1BCFG	.EQU	DEFSERCFG	; SIO 1B: SERIAL LINE CONFIG
+SIO1BCTCC	.EQU	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+;
+XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
+;
+VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
+CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
+GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
+TMSENABLE	.EQU	TRUE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSMODE		.EQU	TMSMODE_NABU80	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO|NABU40|NABU80]
+TMSTIMENABLE	.EQU	TRUE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
+VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
+VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
+EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+;
+MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
+MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
+MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
+MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
+;
+FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE		.EQU	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
+FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
+FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
+FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+;
+RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
+;
+IDEENABLE	.EQU	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+IDETRACE	.EQU	1		; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IDECNT		.EQU	1		; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
+IDE0MODE	.EQU	IDEMODE_RC	; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE0BASE	.EQU	$10		; IDE 0: IO BASE ADDRESS
+IDE0DATLO	.EQU	$00		; IDE 0: DATA LO PORT FOR 16-BIT I/O
+IDE0DATHI	.EQU	$00		; IDE 0: DATA HI PORT FOR 16-BIT I/O
+IDE0A8BIT	.EQU	TRUE		; IDE 0A (MASTER): 8 BIT XFER
+IDE0B8BIT	.EQU	TRUE		; IDE 0B (MASTER): 8 BIT XFER
+IDE1MODE	.EQU	IDEMODE_NONE	; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE1BASE	.EQU	$00		; IDE 1: IO BASE ADDRESS
+IDE1DATLO	.EQU	$00		; IDE 1: DATA LO PORT FOR 16-BIT I/O
+IDE1DATHI	.EQU	$00		; IDE 1: DATA HI PORT FOR 16-BIT I/O
+IDE1A8BIT	.EQU	TRUE		; IDE 1A (MASTER): 8 BIT XFER
+IDE1B8BIT	.EQU	TRUE		; IDE 1B (MASTER): 8 BIT XFER
+IDE2MODE	.EQU	IDEMODE_NONE	; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE2BASE	.EQU	$00		; IDE 2: IO BASE ADDRESS
+IDE2DATLO	.EQU	$00		; IDE 2: DATA LO PORT FOR 16-BIT I/O
+IDE2DATHI	.EQU	$00		; IDE 2: DATA HI PORT FOR 16-BIT I/O
+IDE2A8BIT	.EQU	TRUE		; IDE 2A (MASTER): 8 BIT XFER
+IDE2B8BIT	.EQU	TRUE		; IDE 2B (MASTER): 8 BIT XFER
+;
+PPIDEENABLE	.EQU	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+PPIDETRACE	.EQU	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPIDECNT	.EQU	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
+PPIDE0BASE	.EQU	$60		; PPIDE 0: PPI REGISTERS BASE ADR
+PPIDE0A8BIT	.EQU	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
+PPIDE0B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE1BASE	.EQU	$00		; PPIDE 1: PPI REGISTERS BASE ADR
+PPIDE1A8BIT	.EQU	FALSE		; PPIDE 1A (MASTER): 8 BIT XFER
+PPIDE1B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE2BASE	.EQU	$00		; PPIDE 2: PPI REGISTERS BASE ADR
+PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
+PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+;
+SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
+SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
+SDCNT		.EQU	2		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
+SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
+;
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+CHTRACE		.EQU	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHUSBTRACE	.EQU	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHSDTRACE	.EQU	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHCNT		.EQU	2		; CH: NUMBER OF BOARDS TO DETECT (1-2)
+CH0BASE		.EQU	$3E		; CH 0: BASE I/O ADDRESS
+CH0USBENABLE	.EQU	TRUE		; CH 0: ENABLE USB DISK
+CH0SDENABLE	.EQU	FALSE		; CH 0: ENABLE SD DISK
+CH1BASE		.EQU	$3C		; CH 1: BASE I/O ADDRESS
+CH1USBENABLE	.EQU	TRUE		; CH 1: ENABLE USB DISK
+CH1SDENABLE	.EQU	FALSE		; CH 1: ENABLE SD DISK
+;
+PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
+PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
+PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
+;
+PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
+;
+ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+;
+HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
+;
+PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
+PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
+;
+LPTENABLE	.EQU	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
+LPTMODE		.EQU	LPTMODE_MG014	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
+LPTCNT		.EQU	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
+LPTTRACE	.EQU	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+LPT0BASE	.EQU	$0C		; LPT 0: REGISTERS BASE ADR
+LPT1BASE	.EQU	$00		; LPT 1: REGISTERS BASE ADR
+;
+PPAENABLE	.EQU	FALSE		; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
+PPACNT		.EQU	1		; PPA: NUMBER OF PPA DEVICES (1-2)
+PPATRACE	.EQU	1		; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPAMODE		.EQU	PPAMODE_MG014	; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
+PPA0BASE	.EQU	LPT0BASE	; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
+PPA1BASE	.EQU	LPT1BASE	; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
+;
+IMMENABLE	.EQU	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
+IMMCNT		.EQU	1		; IMM: NUMBER OF IMM DEVICES (1-2)
+IMMTRACE	.EQU	1		; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IMMMODE		.EQU	IMMMODE_MG014	; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
+IMM0BASE	.EQU	LPT0BASE	; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
+IMM1BASE	.EQU	LPT1BASE	; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
+;
+SYQENABLE	.EQU	FALSE		; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
+SYQCNT		.EQU	1		; SYQ: NUMBER OF SYQ DEVICES (1-2)
+SYQTRACE	.EQU	1		; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SYQMODE		.EQU	IMMMODE_MG014	; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
+SYQ0BASE	.EQU	LPT0BASE	; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
+SYQ1BASE	.EQU	LPT1BASE	; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
+;
+PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
+PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
+PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
+;
+UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
+;
+SN76489ENABLE	.EQU	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+AUDIOTRACE	.EQU	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
+SN7CLK		.EQU	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
+SNMODE		.EQU	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
+;
+AY38910ENABLE	.EQU	TRUE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
+AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
+AYMODE		.EQU	AYMODE_NABU	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+;
+SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
+;
+DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
+DMAMODE		.EQU	DMAMODE_RC	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
+;
+YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER
+VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
--- a/Source/HBIOS/cfg_rcz180.asm
+++ b/Source/HBIOS/cfg_rcz180.asm
@ -86,7 +86,7 @@ FPSW_INV	.EQU	FALSE		; FP: SWITCH BITS ARE INVERTED
 DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
 ;
 LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED (SINGLE LED)
-LEDMODE		.EQU	LEDMODE_STD	; LEDMODE_[STD|RTC]
+LEDMODE		.EQU	LEDMODE_STD	; LEDMODE_[STD|SC|RTC|NABU]
 LEDPORT		.EQU	$0E		; STATUS LED PORT ADDRESS
 LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
 ;
@ -145,7 +145,7 @@ UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
 UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG | SER_RTS	; UART: LINE CONFIG FOR UART PORTS
-UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
+UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
 UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
@ -192,7 +192,7 @@ VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
 CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
 GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO]
+TMSMODE		.EQU	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO|NABU40|NABU80]
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
--- a/Source/HBIOS/cfg_rcz280.asm
+++ b/Source/HBIOS/cfg_rcz280.asm
@ -80,7 +80,7 @@ FPSW_INV	.EQU	FALSE		; FP: SWITCH BITS ARE INVERTED
 DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
 ;
 LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED (SINGLE LED)
-LEDMODE		.EQU	LEDMODE_STD	; LEDMODE_[STD|RTC]
+LEDMODE		.EQU	LEDMODE_STD	; LEDMODE_[STD|SC|RTC|NABU]
 LEDPORT		.EQU	$0E		; STATUS LED PORT ADDRESS
 LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
 ;
@ -139,7 +139,7 @@ UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
 UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG | SER_RTS	; UART: LINE CONFIG FOR UART PORTS
-UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
+UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
 UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
@ -196,7 +196,7 @@ VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
 CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
 GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO]
+TMSMODE		.EQU	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO|NABU40|NABU80]
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
@ -331,7 +331,7 @@ SNMODE		.EQU	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
 ;
 AY38910ENABLE	.EQU	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.EQU	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO]
+AYMODE		.EQU	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
 ;
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
--- a/Source/HBIOS/cfg_rcz80.asm
+++ b/Source/HBIOS/cfg_rcz80.asm
@ -80,7 +80,7 @@ FPSW_INV	.EQU	FALSE		; FP: SWITCH BITS ARE INVERTED
 DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
 ;
 LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED (SINGLE LED)
-LEDMODE		.EQU	LEDMODE_STD	; LEDMODE_[STD|RTC]
+LEDMODE		.EQU	LEDMODE_STD	; LEDMODE_[STD|SC|RTC|NABU]
 LEDPORT		.EQU	$0E		; STATUS LED PORT ADDRESS
 LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
 ;
@ -139,7 +139,7 @@ UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
 UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG | SER_RTS	; UART: LINE CONFIG FOR UART PORTS
-UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
+UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
 UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
@ -191,7 +191,7 @@ VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
 CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
 GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO]
+TMSMODE		.EQU	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO|NABU40|NABU80]
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
@ -326,7 +326,7 @@ SNMODE		.EQU	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
 ;
 AY38910ENABLE	.EQU	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.EQU	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO]
+AYMODE		.EQU	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
 ;
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
--- a/Source/HBIOS/cfg_rph.asm
+++ b/Source/HBIOS/cfg_rph.asm
@ -80,7 +80,7 @@ FPSW_INV	.EQU	FALSE		; FP: SWITCH BITS ARE INVERTED
 DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
 ;
 LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED
-LEDMODE		.EQU	LEDMODE_RTC	; LEDMODE_[STD|RTC]
+LEDMODE		.EQU	LEDMODE_RTC	; LEDMODE_[STD|SC|RTC|NABU]
 LEDPORT		.EQU	RTCIO		; STATUS LED PORT ADDRESS
 LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
 ;
@ -133,7 +133,7 @@ UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
 UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
-UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
+UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
 UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
@ -166,7 +166,7 @@ GDCENABLE	.EQU	TRUE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 GDCMODE		.EQU	GDCMODE_RPH	; GDC: GDC MODE: GDCMODE_[NONE|ECB|RPH]
 GDCMON		.EQU	GDCMON_EGA      ; GDC: GDC MONITOR SETUP: GDCMON_[NONE|CGA|EGA]
 TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_N8	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO]
+TMSMODE		.EQU	TMSMODE_N8	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO|NABU40|NABU80]
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VGASIZ		.EQU	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
@ -277,7 +277,7 @@ SNMODE		.EQU	SNMODE_NONE	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
 ;
 AY38910ENABLE	.EQU	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.EQU	AYMODE_N8	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO]
+AYMODE		.EQU	AYMODE_N8	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
 ;
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
--- a/Source/HBIOS/cfg_s100.asm
+++ b/Source/HBIOS/cfg_s100.asm
@ -80,7 +80,7 @@ FPSW_INV	.EQU	FALSE		; FP: SWITCH BITS ARE INVERTED
 DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
 ;
 LEDENABLE	.EQU	TRUE		; ENABLES STATUS LED (SINGLE LED)
-LEDMODE		.EQU	LEDMODE_STD	; LEDMODE_[STD|RTC]
+LEDMODE		.EQU	LEDMODE_SC	; LEDMODE_[STD|SC|RTC|NABU]
 LEDPORT		.EQU	$0E		; STATUS LED PORT ADDRESS
 LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
 ;
@ -139,7 +139,7 @@ UARTENABLE	.EQU	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
 UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG | SER_RTS	; UART: LINE CONFIG FOR UART PORTS
-UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
+UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
 UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
@ -186,7 +186,7 @@ VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
 CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
 GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO]
+TMSMODE		.EQU	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO|NABU40|NABU80]
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
@ -311,7 +311,7 @@ SNMODE		.EQU	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
 ;
 AY38910ENABLE	.EQU	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.EQU	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO]
+AYMODE		.EQU	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
 ;
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
--- a/Source/HBIOS/cfg_sbc.asm
+++ b/Source/HBIOS/cfg_sbc.asm
@ -75,7 +75,7 @@ FPSW_INV	.EQU	FALSE		; FP: SWITCH BITS ARE INVERTED
 DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
 ;
 LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED
-LEDMODE		.EQU	LEDMODE_RTC	; LEDMODE_[STD|RTC]
+LEDMODE		.EQU	LEDMODE_RTC	; LEDMODE_[STD|SC|RTC|NABU]
 LEDPORT		.EQU	RTCIO		; STATUS LED PORT ADDRESS
 LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
 ;
@ -128,7 +128,7 @@ UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
 UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
-UARTSBC		.EQU	TRUE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
+UARTSBC		.EQU	TRUE		; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
 UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
 UARTCAS		.EQU	TRUE		; UART: AUTO-DETECT ECB CASSETTE UART
@ -165,7 +165,7 @@ CVDUMODE	.EQU	CVDUMODE_ECB	; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC]
 CVDUMON		.EQU	CVDUMON_EGA	; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
 GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_SCG	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO]
+TMSMODE		.EQU	TMSMODE_SCG	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO|NABU40|NABU80]
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VGASIZ		.EQU	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
@ -277,7 +277,7 @@ SNMODE		.EQU	SNMODE_VGM	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
 ;
 AY38910ENABLE	.EQU	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.EQU	AYMODE_SCG	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO]
+AYMODE		.EQU	AYMODE_SCG	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
 ;
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
--- a/Source/HBIOS/cfg_scz180.asm
+++ b/Source/HBIOS/cfg_scz180.asm
@ -80,7 +80,7 @@ FPSW_INV	.EQU	FALSE		; FP: SWITCH BITS ARE INVERTED
 DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
 ;
 LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED (SINGLE LED)
-LEDMODE		.EQU	LEDMODE_STD	; LEDMODE_[STD|RTC]
+LEDMODE		.EQU	LEDMODE_SC	; LEDMODE_[STD|SC|RTC|NABU]
 LEDPORT		.EQU	$0E		; STATUS LED PORT ADDRESS
 LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
 ;
@ -139,7 +139,7 @@ UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
 UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG | SER_RTS	; UART: LINE CONFIG FOR UART PORTS
-UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
+UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
 UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
@ -186,7 +186,7 @@ VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
 CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
 GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO]
+TMSMODE		.EQU	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO|NABU40|NABU80]
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
@ -321,7 +321,7 @@ SNMODE		.EQU	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
 ;
 AY38910ENABLE	.EQU	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.EQU	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO]
+AYMODE		.EQU	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
 ;
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
--- a/Source/HBIOS/cfg_z80retro.asm
+++ b/Source/HBIOS/cfg_z80retro.asm
@ -78,7 +78,7 @@ FPSW_INV	.EQU	FALSE		; FP: SWITCH BITS ARE INVERTED
 DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
 ;
 LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED
-LEDMODE		.EQU	LEDMODE_RTC	; LEDMODE_[STD|RTC]
+LEDMODE		.EQU	LEDMODE_RTC	; LEDMODE_[STD|SC|RTC|NABU]
 LEDPORT		.EQU	$00		; STATUS LED PORT ADDRESS
 LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
 ;
@ -126,7 +126,7 @@ UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
 UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
-UARTSBC		.EQU	TRUE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
+UARTSBC		.EQU	TRUE		; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
 UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
@ -168,7 +168,7 @@ VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
 CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
 GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_NONE	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO]
+TMSMODE		.EQU	TMSMODE_NONE	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO|NABU40|NABU80]
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
--- a/Source/HBIOS/cfg_zeta.asm
+++ b/Source/HBIOS/cfg_zeta.asm
@ -67,7 +67,7 @@ FPSW_INV	.EQU	FALSE		; FP: SWITCH BITS ARE INVERTED
 DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
 ;
 LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED
-LEDMODE		.EQU	LEDMODE_RTC	; LEDMODE_[STD|RTC]
+LEDMODE		.EQU	LEDMODE_RTC	; LEDMODE_[STD|SC|RTC|NABU]
 LEDPORT		.EQU	RTCIO		; STATUS LED PORT ADDRESS
 LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
 ;
@ -115,7 +115,7 @@ UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
 UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
-UARTSBC		.EQU	TRUE		; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
+UARTSBC		.EQU	TRUE		; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
 UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
@ -138,7 +138,7 @@ VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
 CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
 GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_NONE	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO]
+TMSMODE		.EQU	TMSMODE_NONE	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO|NABU40|NABU80]
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
--- a/Source/HBIOS/cfg_zeta2.asm
+++ b/Source/HBIOS/cfg_zeta2.asm
@ -78,7 +78,7 @@ FPSW_INV	.EQU	FALSE		; FP: SWITCH BITS ARE INVERTED
 DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
 ;
 LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED
-LEDMODE		.EQU	LEDMODE_RTC	; LEDMODE_[STD|RTC]
+LEDMODE		.EQU	LEDMODE_STD	; LEDMODE_[STD|SC|RTC|NABU]
 LEDPORT		.EQU	RTCIO		; STATUS LED PORT ADDRESS
 LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
 ;
@ -126,7 +126,7 @@ UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
 UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
-UARTSBC		.EQU	TRUE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
+UARTSBC		.EQU	TRUE		; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
 UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
@ -149,7 +149,7 @@ VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
 CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
 GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_NONE	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
+TMSMODE		.EQU	TMSMODE_NONE	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO|NABU40|NABU80]
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
--- a/Source/HBIOS/ch.asm
+++ b/Source/HBIOS/ch.asm
@ -105,9 +105,9 @@ CH_CFG0:	; DEVICE 0
 	.DB	CH0SDENABLE		; ENABLE SD CARD SUB-DRIVER
 	.DW	CHSD_CFG0		; SD CARD SUB-DRIVER INIT ADR
 ;
-	.ECHO	"CH: IO="
-	.ECHO	CH0BASE
-	.ECHO	"\n"
+	DEVECHO	"CH: IO="
+	DEVECHO	CH0BASE
+	DEVECHO	"\n"
 #ENDIF
 ;
 #IF (CHCNT >= 2)
@ -120,9 +120,9 @@ CH_CFG1:	; DEVICE 1
 	.DB	CH1SDENABLE		; ENABLE SD CARD SUB-DRIVER
 	.DW	CHSD_CFG1		; SD CARD SUB-DRIVER INIT ADR
 ;
-	.ECHO	"CH: IO="
-	.ECHO	CH1BASE
-	.ECHO	"\n"
+	DEVECHO	"CH: IO="
+	DEVECHO	CH1BASE
+	DEVECHO	"\n"
 #ENDIF
 ;
 #IF ($ - CH_CFGTBL) != (CHCNT * CH_CFGSIZ)
--- a/Source/HBIOS/chsd.asm
+++ b/Source/HBIOS/chsd.asm
@ -60,9 +60,9 @@ CHSD_CFG0:
 	.DW	CH0_MODE		; POINTER TO MODE BYTE
 ;
  #IF (CH0SDENABLE)
-	.ECHO	"CHSD: IO="
-	.ECHO	CH0BASE
-	.ECHO	"\n"
+	DEVECHO	"CHSD: IO="
+	DEVECHO	CH0BASE
+	DEVECHO	"\n"
  #ENDIF
 #ENDIF
 ;
@ -77,9 +77,9 @@ CHSD_CFG1:
 	.DW	CH1_MODE		; POINTER TO MODE BYTE
 ;
  #IF (CH1SDENABLE)
-	.ECHO	"CHSD: IO="
-	.ECHO	CH1BASE
-	.ECHO	"\n"
+	DEVECHO	"CHSD: IO="
+	DEVECHO	CH1BASE
+	DEVECHO	"\n"
  #ENDIF
 #ENDIF
 ;
--- a/Source/HBIOS/chusb.asm
+++ b/Source/HBIOS/chusb.asm
@ -65,9 +65,9 @@ CHUSB_CFG0:
 	.DW	CH0_MODE		; POINTER TO MODE BYTE
 ;
  #IF (CH0USBENABLE)
-	.ECHO	"CHUSB: IO="
-	.ECHO	CH0BASE
-	.ECHO	"\n"
+	DEVECHO	"CHUSB: IO="
+	DEVECHO	CH0BASE
+	DEVECHO	"\n"
  #ENDIF
 #ENDIF
 ;
@ -82,9 +82,9 @@ CHUSB_CFG1:
 	.DW	CH1_MODE		; POINTER TO MODE BYTE
 ;
  #IF (CH1USBENABLE)
-	.ECHO	"CHUSB: IO="
-	.ECHO	CH1BASE
-	.ECHO	"\n"
+	DEVECHO	"CHUSB: IO="
+	DEVECHO	CH1BASE
+	DEVECHO	"\n"
  #ENDIF
 #ENDIF
 ;
--- a/Source/HBIOS/ctc.asm
+++ b/Source/HBIOS/ctc.asm
@ -28,19 +28,19 @@ CTC_TIM256CFG	.EQU	%00110111	; CTC TIMER/256 MODE CONFIG
 #IF (CTCTIMER & (INTMODE != 2))
 	.ECHO	"*** WARNING: CTC TIMER DISABLED -- INTMODE 2 REQUIRED!!!\n"
 #ENDIF
-	.ECHO	"CTC: IO="
-	.ECHO	CTCBASE
+	DEVECHO	"CTC: IO="
+	DEVECHO	CTCBASE
 ;
 #IF (CTCTIMER & (INTMODE == 2))
 ;
  #IF (INT_CTC0A % 4)
  
-	.ECHO	INT_CTC0A
-	.ECHO	"\n"
-	.ECHO	(INT_CTC0A % 4)
-	.ECHO	"\n"
+	DEVECHO	INT_CTC0A
+	DEVECHO	"\n"
+	DEVECHO	(INT_CTC0A % 4)
+	DEVECHO	"\n"
  
-	.ECHO	"*** ERROR: CTC BASE VECTOR NOT DWORD ALIGNED!!!\n"
+	DEVECHO	"*** ERROR: CTC BASE VECTOR NOT DWORD ALIGNED!!!\n"
 	!!!	; FORCE AN ASSEMBLY ERROR
  #ENDIF
 ;
@ -112,23 +112,23 @@ CTC_DIVHI	.EQU	CTCPRE
 CTC_DIVLO	.EQU	(CTC_DIV / CTC_DIVHI)
 ;

-	.ECHO	", TIMER MODE="
+	DEVECHO	", TIMER MODE="
  #IF (CTCMODE == CTCMODE_CTR)
-		.ECHO	"COUNTER"
+		DEVECHO	"COUNTER"
  #ENDIF
  #IF (CTCMODE == CTCMODE_TIM16)
-		.ECHO	"TIMER/16"
+		DEVECHO	"TIMER/16"
  #ENDIF
  #IF (CTCMODE == CTCMODE_TIM256)
-		.ECHO	"TIMER/256"
+		DEVECHO	"TIMER/256"
  #ENDIF
-	.ECHO ", DIVISOR="
-	.ECHO CTC_DIV
-	.ECHO ", HI="
-	.ECHO CTC_DIVHI
-	.ECHO ", LO="
-	.ECHO CTC_DIVLO
-	.ECHO ", INTERRUPTS ENABLED"
+	DEVECHO ", DIVISOR="
+	DEVECHO CTC_DIV
+	DEVECHO ", HI="
+	DEVECHO CTC_DIVHI
+	DEVECHO ", LO="
+	DEVECHO CTC_DIVLO
+	DEVECHO ", INTERRUPTS ENABLED"
 ;
  #IF ((CTC_DIV == 0) | (CTC_DIV > $FFFF))
 	.ECHO "COMPUTED CTC DIVISOR IS UNUSABLE!\n"
@ -148,7 +148,7 @@ CTCTIVT		.EQU	INT_CTC0A + CTCTIMCH
 ;
 #ENDIF
 ;
-	.ECHO "\n"
+	DEVECHO "\n"
 ;
 ;==================================================================================================
 ; CTC PRE-INITIALIZATION
--- a/Source/HBIOS/cvdu.asm
+++ b/Source/HBIOS/cvdu.asm
@ -18,7 +18,7 @@
 ;
 CVDU_BASE	.EQU	$E0
 ;
-		.ECHO	"CVDU: MODE="
+		DEVECHO	"CVDU: MODE="
 ;
 #IF (CVDUMODE == CVDUMODE_ECB)
 CVDU_KBDDATA	.EQU	CVDU_BASE + $02	; KBD CTLR DATA PORT
@ -26,7 +26,7 @@ CVDU_KBDST	.EQU	CVDU_BASE + $0A	; KBD CTLR STATUS/CMD PORT
 CVDU_STAT	.EQU	CVDU_BASE + $04	; READ M8563 STATUS
 CVDU_REG	.EQU	CVDU_BASE + $04	; SELECT M8563 REGISTER
 CVDU_DATA	.EQU	CVDU_BASE + $0C	; READ/WRITE M8563 DATA
-		.ECHO	"ECB"
+		DEVECHO	"ECB"
 #ENDIF
 ;
 #IF (CVDUMODE == CVDUMODE_MBC)
@ -35,15 +35,15 @@ CVDU_KBDST	.EQU	CVDU_BASE + $03	; KBD CTLR STATUS/CMD PORT
 CVDU_STAT	.EQU	CVDU_BASE + $04	; READ M8563 STATUS
 CVDU_REG	.EQU	CVDU_BASE + $04	; SELECT M8563 REGISTER
 CVDU_DATA	.EQU	CVDU_BASE + $05	; READ/WRITE M8563 DATA
-		.ECHO	"MBC"
+		DEVECHO	"MBC"
 #ENDIF
 ;
-		.ECHO	", IO="
-		.ECHO	CVDU_BASE
-		.ECHO	", KBD MODE=PS/2"
-		.ECHO	", KBD IO="
-		.ECHO	CVDU_KBDDATA
-		.ECHO	"\n"
+		DEVECHO	", IO="
+		DEVECHO	CVDU_BASE
+		DEVECHO	", KBD MODE=PS/2"
+		DEVECHO	", KBD IO="
+		DEVECHO	CVDU_KBDDATA
+		DEVECHO	"\n"
 ;
 CVDU_ROWS	.EQU	25
 CVDU_COLS	.EQU	80
--- a/Source/HBIOS/dma.asm
+++ b/Source/HBIOS/dma.asm
@ -3,17 +3,17 @@
 ;==================================================================================================
 ;
 ;
-	.ECHO	"DMA: MODE="
+	DEVECHO	"DMA: MODE="
 ;
 #IF ((DMAMODE == DMAMODE_ECB) | (DMAMODE == DMAMODE_MBC))
 DMA_IO		.EQU	DMABASE
 DMA_CTL		.EQU	DMABASE + 1
 DMA_USEHALF	.EQU	TRUE
  #IF (DMAMODE == DMAMODE_ECB)
-	.ECHO	"ECB"
+	DEVECHO	"ECB"
  #ENDIF
  #IF (DMAMODE == DMAMODE_MBC)
-	.ECHO	"MBC"
+	DEVECHO	"MBC"
  #ENDIF
 #ENDIF
 ;
@ -21,12 +21,12 @@ DMA_USEHALF	.EQU	TRUE
 DMA_IO		.EQU	DMABASE
 DMA_CTL		.EQU	DMABASE + 3
 DMA_USEHALF	.EQU	FALSE
-	.ECHO	"DUO"
+	DEVECHO	"DUO"
 #ENDIF
 ;S
-	.ECHO	", IO="
-	.ECHO	DMA_IO
-	.ECHO	"\n"
+	DEVECHO	", IO="
+	DEVECHO	DMA_IO
+	DEVECHO	"\n"
 ;
 DMA_CONTINUOUS			.equ 	%10111101	; + Pulse
 DMA_BYTE			.equ 	%10011101	; + Pulse
--- a/Source/HBIOS/ds1501rtc.asm
+++ b/Source/HBIOS/ds1501rtc.asm
@ -111,11 +111,11 @@ DS1501RTC_TE	.EQU	%10000000
 ;
 DS1501RTC_BUFSIZE	.EQU	6		; 6 BYTE BUFFER (YYMMDDHHMMSS)

-	.ECHO	"DS1501RTC: RTCIO="
-	.ECHO	DS1501RTC_BASE
-	.ECHO	", NVMIO="
-	.ECHO	DS1501NVM_BASE
-	.ECHO	"\n"
+	DEVECHO	"DS1501RTC: RTCIO="
+	DEVECHO	DS1501RTC_BASE
+	DEVECHO	", NVMIO="
+	DEVECHO	DS1501NVM_BASE
+	DEVECHO	"\n"
 ;
 ; RTC Device Initialization Entry
 ;
--- a/Source/HBIOS/ds7rtc.asm
+++ b/Source/HBIOS/ds7rtc.asm
@ -23,7 +23,7 @@ DS7_WRITE 	.EQU    (DS7_DS1307 | DS7_W)	; WRITE
 ;
 DS7_CTL		.EQU	(DS7_OUT | DS7_SQWE | DS7_RATE)
 ;
-		.ECHO	"DS1307: ENABLED\n"
+		DEVECHO	"DS1307: ENABLED\n"
 ;
 ;-----------------------------------------------------------------------------
 ; DS1307 INITIALIZATION
--- a/Source/HBIOS/dsrtc.asm
+++ b/Source/HBIOS/dsrtc.asm
@ -66,30 +66,30 @@
 ; RTC LATCH WRITE
 ; ---------------
 ;
-; BIT	SBC	RCBUS	SBC-004	MFPIC	K80W  	N8	N8-CSIO	MK4	SC130	SC131	SC126		MBC	RPH
-; -----	-------	-------	-------	-------	-------	-------	-------	-------	-------	-------	---------------	------- -------
-; D7	RTC_OUT RTC_OUT RTC_OUT	--	--	RTC_OUT RTC_OUT	RTC_OUT	--	--	RTC_OUT,I2C_SDA	RTC_OUT	RTC_OUT
-; D6	RTC_CLK RTC_CLK RTC_CLK	--	--	RTC_CLK RTC_CLK	RTC_CLK	--	--	RTC_CLK		RTC_CLK	RTC_CLK
-; D5	/RTC_WE /RTC_WE /RTC_WE	--	--	/RTC_WE /RTC_WE	/RTC_WE	--	--	/RTC_WE		/RTC_WE	/RTC_WE
-; D4	RTC_CE	RTC_CE	RTC_CE	--	--	RTC_CE  RTC_CE	RTC_CE	--	--	RTC_CE		RTC_CE	RTC_CE
-; D3	NC	NC	CLKSEL	/RTC_CE	/RTC_CE	NC	NC	NC	--	--	/SPI_CS2	CLKSEL	--
-; D2	NC	NC	SPK	RTC_CLK	RTC_CLK	SPI_CS	SPI_CS	NC	/SPI_CS1/SPI_CS1/SPI_CS1	SPK	--
-; D1	--	--	--	RTC_WE	RTC_WE	SPI_CLK	NC	NC	--	--	FS		LED1	--
-; D0	--	--	--	RTC_OUT	RTC_OUT	SPI_DI	NC	NC	--	--	I2C_SCL		LED0	--
-;
-; RTC LATCH READTCH READ
-; ----------------------
-;
-; D7	--	--	--	--	--	--	--	--	--	--	I2C_SDA		--	--
-; D6	CFG	--	CFG	--	--	SPI_DO	CFG	--	--	--	--		CFG	--
-; D5	--	--	--	--	--	--	--	--	--	--	--		--	--
-; D4	--	--	--	--	--	--	--	--	--	--	--		--	--
-; D3	--	--	--	--	--	--	--	--	--	--	--		--	--
-; D2	--	--	--	--	--	--	--	--	--	--	--		--	--
-; D1	--	--	--	--	--	--	--	--	--	--	--		CLKSEL	--
-; D0	RTC_IN	RTC_IN	RTC_IN	RTC_IN	RTC_IN	RTC_IN	RTC_IN	RTC_IN	--	--	RTC_IN		RTC_IN	RTC_IN
-;
-	.ECHO	"DSRTC: MODE="
+; BIT	SBC	RCBUS	SBC-004	MFPIC	K80W  	N8	N8-CSIO	MK4	SC126		SC130	SC131	SC140	SC503	SC722	MBC	RPH
+; -----	-------	-------	-------	-------	-------	-------	-------	-------	---------------	-------	-------	-------	-------	-------	------- -------
+; D7	RTC_OUT RTC_OUT RTC_OUT	--	--	RTC_OUT RTC_OUT	RTC_OUT	RTC_OUT,I2C_SDA	--	--	--	--	--	RTC_OUT	RTC_OUT
+; D6	RTC_CLK RTC_CLK RTC_CLK	--	--	RTC_CLK RTC_CLK	RTC_CLK	RTC_CLK		--	--	--	--	--	RTC_CLK	RTC_CLK
+; D5	/RTC_WE /RTC_WE /RTC_WE	--	--	/RTC_WE /RTC_WE	/RTC_WE	/RTC_WE		--	--	--	--	--	/RTC_WE	/RTC_WE
+; D4	RTC_CE	RTC_CE	RTC_CE	--	--	RTC_CE  RTC_CE	RTC_CE	RTC_CE		--	--	--	--	--	RTC_CE	RTC_CE
+; D3	NC	NC	CLKSEL	/RTC_CE	/RTC_CE	NC	NC	NC	/SPI_CS2	--	--	--	--	--	CLKSEL	--
+; D2	NC	NC	SPK	RTC_CLK	RTC_CLK	SPI_CS	SPI_CS	NC	/SPI_CS1	/SPI_CS1/SPI_CS1/SPI_CS1/SPI_CS1/SPI_CS1SPK	--
+; D1	--	--	--	RTC_WE	RTC_WE	SPI_CLK	NC	NC	FS		--	--	--	--	--	LED1	--
+; D0	--	--	--	RTC_OUT	RTC_OUT	SPI_DI	NC	NC	I2C_SCL		--	--	--	--	--	LED0	--
+;                                                                                                                       
+; RTC LATCH LATCH READ                                                                                                  
+; --------------------                                                                                                  
+;                                                                                                                       
+; D7	--	--	--	--	--	--	--	--	I2C_SDA		--	--	--	--	--	--	--
+; D6	CFG	--	CFG	--	--	SPI_DO	CFG	--	--		--	--	--	--	--	CFG	--
+; D5	--	--	--	--	--	--	--	--	--		--	--	--	--	--	--	--
+; D4	--	--	--	--	--	--	--	--	--		--	--	--	--	--	--	--
+; D3	--	--	--	--	--	--	--	--	--		--	--	--	--	--	--	--
+; D2	--	--	--	--	--	--	--	--	--		--	--	--	--	--	--	--
+; D1	--	--	--	--	--	--	--	--	--		--	--	--	--	--	CLKSEL	--
+; D0	RTC_IN	RTC_IN	RTC_IN	RTC_IN	RTC_IN	RTC_IN	RTC_IN	RTC_IN	RTC_IN		--	--	--	--	--	RTC_IN	RTC_IN
+;
+	DEVECHO	"DSRTC: MODE="
 ;
 #IF (DSRTCMODE == DSRTCMODE_STD)
 ;
@ -107,7 +107,7 @@ RTCDEF		.SET	RTCDEF | DSRTC_IDLE	; FOR HBIOS MAINLINE
 ;
 #DEFINE	DSRTC_OPRVAL	HB_RTCVAL
 ;
-		.ECHO	"STD"
+		DEVECHO	"STD"
 ;
 #ENDIF
 ;
@ -125,7 +125,7 @@ DSRTC_IDLE	.EQU	%00001000	; QUIESCENT STATE
 ;
 #DEFINE	DSRTC_OPRVAL	DSRTC_RTCVAL
 ;
-		.ECHO	"MFPIC"
+		DEVECHO	"MFPIC"
 ;
 #ENDIF
 ;
@ -143,13 +143,13 @@ DSRTC_IDLE	.EQU	%00001000	; QUIESCENT STATE
 ;
 #DEFINE	DSRTC_OPRVAL	HB_RTCVAL
 ;
-		.ECHO	"K80W"
+		DEVECHO	"K80W"
 ;
 #ENDIF
 ;
-		.ECHO	", IO="
-		.ECHO	DSRTC_IO
-		.ECHO	"\n"
+		DEVECHO	", IO="
+		DEVECHO	DSRTC_IO
+		DEVECHO	"\n"
 ;
 ; VALUES FOR DIFFERENT BATTERY OR SUPERCAPACITOR CHARGE RATES
 ;
--- a/Source/HBIOS/duart.asm
+++ b/Source/HBIOS/duart.asm
@ -823,9 +823,9 @@ DUART0A_CFG:
 	.DW	DUART0ACFG		; IY+8	LINE CONFIGURATION
 	.DB	1			; IY+10	MULTIPLIER WRT 3.6864MHZ CLOCK
 ;
-	.ECHO	"DUART: IO="
-	.ECHO	DUART0BASE + $00
-	.ECHO	", CHANNEL A\n"
+	DEVECHO	"DUART: IO="
+	DEVECHO	DUART0BASE + $00
+	DEVECHO	", CHANNEL A\n"
 ;
 DUART_CFGSIZ	.EQU	$ - DUART_CFG	; SIZE OF ONE CFG TABLE ENTRY
 ;
@ -840,9 +840,9 @@ DUART0B_CFG:
 	.DW	DUART0BCFG		; LINE CONFIGURATION
 	.DB	1			; MULTIPLIER WRT 3.6864MHZ CLOCK
 ;
-	.ECHO	"DUART: IO="
-	.ECHO	DUART0BASE + $08
-	.ECHO	", CHANNEL B\n"
+	DEVECHO	"DUART: IO="
+	DEVECHO	DUART0BASE + $08
+	DEVECHO	", CHANNEL B\n"
 ;
 #IF (DUARTCNT >= 2)
 ;
@ -857,9 +857,9 @@ DUART1A_CFG:
 	.DW	DUART1ACFG		; LINE CONFIGURATION
 	.DB	1			; MULTIPLIER WRT 3.6864MHZ CLOCK
 ;
-	.ECHO	"DUART: IO="
-	.ECHO	DUART1BASE + $00
-	.ECHO	", CHANNEL A\n"
+	DEVECHO	"DUART: IO="
+	DEVECHO	DUART1BASE + $00
+	DEVECHO	", CHANNEL A\n"
 ;
 DUART1B_CFG:
 	; 2ND DUART MODULE CHANNEL B
@ -872,9 +872,9 @@ DUART1B_CFG:
 	.DW	DUART1BCFG		; LINE CONFIGURATION
 	.DB	1			; MULTIPLIER WRT 3.6864MHZ CLOCK
 ;
-	.ECHO	"DUART: IO="
-	.ECHO	DUART1BASE + $08
-	.ECHO	", CHANNEL B\n"
+	DEVECHO	"DUART: IO="
+	DEVECHO	DUART1BASE + $08
+	DEVECHO	", CHANNEL B\n"
 ;
 #ENDIF
 ;
--- a/Source/HBIOS/ef.asm
+++ b/Source/HBIOS/ef.asm
@ -153,6 +153,10 @@ EF_FG_CYAN	.EQU	6
 EF_FG_WHITE	.EQU	7
 ;
 EF_SCREENSIZE	.EQU	EF_DROWS * EF_DLINES
+;
+	DEVECHO	"EF: IO="
+	DEVECHO	EF_BASE
+	DEVECHO	"\n"
 ;
 ;======================================================================
 ; VDU DRIVER - INITIALIZATION
--- a/Source/HBIOS/esp.asm
+++ b/Source/HBIOS/esp.asm
@ -54,9 +54,9 @@ ESP_CFG_ST	.EQU	2		; ESP STATUS PORT
 ESP_CFG_RDYMSK	.EQU	3		; ESP READY MASK
 ESP_CFG_BSYMSK	.EQU	4		; ESP BUSY MASK
 ;
-	.ECHO	"ESP: IO="
-	.ECHO	ESP_IOBASE
-	.ECHO	"\n"
+	DEVECHO	"ESP: IO="
+	DEVECHO	ESP_IOBASE
+	DEVECHO	"\n"
 ;
 ; GLOBAL ESP INITIALIZATION
 ;
@ -348,7 +348,7 @@ ESP_STR_UPGRADE		.TEXT	"!!!UPGRADE REQUIRED!!!$"
 ESPCON_ROWS	.EQU	25		; VGA DISPLAY ROWS
 ESPCON_COLS	.EQU	80		; VGA DISPLAY COLS
 ;
-	.ECHO	"ESPCON: ENABLED\n"
+	DEVECHO	"ESPCON: ENABLED\n"
 ;
 ;
 ;
@ -692,7 +692,7 @@ ESPSER0_CFG:
 	.DB	ESP_0_BUSY			; ESP BUSY BIT MASK
 	.DW	ESPSER_LINECFG			; LINE CONFIGURATION
 ;
-	.ECHO	"ESPSER: DEVICE=0\n"
+	DEVECHO	"ESPSER: DEVICE=0\n"
 ;
 ESPSER1_CFG:
 	.DB	0				; DEVICE NUMBER (UPDATED DURING INIT)
@ -702,7 +702,7 @@ ESPSER1_CFG:
 	.DB	ESP_1_BUSY			; ESP BUSY BIT MASK
 	.DW	ESPSER_LINECFG			; LINE CONFIGURATION
 ;
-	.ECHO	"ESPSER: DEVICE=1\n"
+	DEVECHO	"ESPSER: DEVICE=1\n"
 ;
 ;
 ;
--- a/Source/HBIOS/fd.asm
+++ b/Source/HBIOS/fd.asm
@ -152,31 +152,31 @@ FD_CFGTBL:
 	.DB	0			; HOST HEAD
 	.DB	FD0TYPE			; DRIVE TYPE
 ;
-	.ECHO	"FD: MODE="
-	.ECHO	FDMODE_STR
-	.ECHO	", IO="
-	.ECHO	FDC_MSR
-	.ECHO	", DRIVE 0"
-	.ECHO	", TYPE="
+	DEVECHO	"FD: MODE="
+	DEVECHO	FDMODE_STR
+	DEVECHO	", IO="
+	DEVECHO	FDC_MSR
+	DEVECHO	", DRIVE 0"
+	DEVECHO	", TYPE="
  #IF (FD0TYPE == FDT_NONE
-	.ECHO	"NONE"
+	DEVECHO	"NONE"
  #ENDIF
  #IF (FD0TYPE == FDT_3DD
-	.ECHO	"3.5\" DD"
+	DEVECHO	"3.5\" DD"
  #ENDIF
  #IF (FD0TYPE == FDT_3HD
-	.ECHO	"3.5\" HD"
+	DEVECHO	"3.5\" HD"
  #ENDIF
  #IF (FD0TYPE == FDT_5DD
-	.ECHO	"5.25\" DD"
+	DEVECHO	"5.25\" DD"
  #ENDIF
  #IF (FD0TYPE == FDT_5HD
-	.ECHO	"5.25\" HD"
+	DEVECHO	"5.25\" HD"
  #ENDIF
  #IF (FD0TYPE == FDT_8
-	.ECHO	"8\" DD"
+	DEVECHO	"8\" DD"
  #ENDIF
-	.ECHO	"\n"
+	DEVECHO	"\n"
 ;
 #IF (FD_DEVCNT >= 2)
 	; DEVICE 1, PRIMARY SLAVE
@ -189,31 +189,31 @@ FD_CFGTBL:
 	.DB	0			; HOST HEAD
 	.DB	FD1TYPE			; DRIVE TYPE
 ;
-	.ECHO	"FD: MODE="
-	.ECHO	FDMODE_STR
-	.ECHO	", IO="
-	.ECHO	FDC_MSR
-	.ECHO	", DRIVE 1"
-	.ECHO	", TYPE="
+	DEVECHO	"FD: MODE="
+	DEVECHO	FDMODE_STR
+	DEVECHO	", IO="
+	DEVECHO	FDC_MSR
+	DEVECHO	", DRIVE 1"
+	DEVECHO	", TYPE="
  #IF (FD1TYPE == FDT_NONE
-	.ECHO	"NONE"
+	DEVECHO	"NONE"
  #ENDIF
  #IF (FD1TYPE == FDT_3DD
-	.ECHO	"3.5\" DD"
+	DEVECHO	"3.5\" DD"
  #ENDIF
  #IF (FD1TYPE == FDT_3HD
-	.ECHO	"3.5\" HD"
+	DEVECHO	"3.5\" HD"
  #ENDIF
  #IF (FD1TYPE == FDT_5DD
-	.ECHO	"5.25\" DD"
+	DEVECHO	"5.25\" DD"
  #ENDIF
  #IF (FD1TYPE == FDT_5HD
-	.ECHO	"5.25\" HD"
+	DEVECHO	"5.25\" HD"
  #ENDIF
  #IF (FD1TYPE == FDT_8
-	.ECHO	"8\" DD"
+	DEVECHO	"8\" DD"
  #ENDIF
-	.ECHO	"\n"
+	DEVECHO	"\n"
 #ENDIF
 ;
 #IF ($ - FD_CFGTBL) != (FD_DEVCNT * FD_CFGSIZ)
--- a/Source/HBIOS/gdc.asm
+++ b/Source/HBIOS/gdc.asm
@ -37,32 +37,32 @@ GDC_COLS	.EQU	80
 ; BE USED TO ALLOW FOR MULTIPLE MONITOR TIMINGS AND/OR FONT
 ; DEFINITIONS.
 ;
-	.ECHO	"GDC: MODE="
+	DEVECHO	"GDC: MODE="
 ;
 #IF (GDCMODE == GDCMODE_ECB)
-	.ECHO	"ECB"
+	DEVECHO	"ECB"
 #ENDIF
 #IF (GDCMODE == GDCMODE_RPH)
-	.ECHO	"RPH"
+	DEVECHO	"RPH"
 #ENDIF
 ;
-	.ECHO	", DISPLAY="
+	DEVECHO	", DISPLAY="
 ;
 #IF (GDCMON == GDCMON_CGA)
  #DEFINE	USEFONTCGA
  #DEFINE	GDC_FONT FONTCGA
-	.ECHO	"CGA"
+	DEVECHO	"CGA"
 #ENDIF
 ;
 #IF (GDCMON == GDCMON_EGA)
  #DEFINE	USEFONT8X16
  #DEFINE	GDC_FONT FONT8X16
-	.ECHO	"EGA"
+	DEVECHO	"EGA"
 #ENDIF
 ;
-	.ECHO	", IO="
-	.ECHO	GDC_BASE
-	.ECHO	"\n"
+	DEVECHO	", IO="
+	DEVECHO	GDC_BASE
+	DEVECHO	"\n"
 ;
 TERMENABLE	.SET	TRUE		; INCLUDE TERMINAL PSEUDODEVICE DRIVER
 KBDENABLE	.SET	TRUE		; INCLUDE KBD KEYBOARD SUPPORT
--- a/Source/HBIOS/h8p.asm
+++ b/Source/HBIOS/h8p.asm
@ -11,6 +11,11 @@
 ;	20    08
 ;	+--10--+  80
 ;
+;
+	DEVECHO	"H8P: IO=??"
+	;DEVECHO	0
+	DEVECHO	"\n"
+;
 ;__H8P_PREINIT_______________________________________________________________________________________
 ;
 ;  CONFIGURE AND RESET PANEL
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
--- a/Source/HBIOS/hbios.inc
+++ b/Source/HBIOS/hbios.inc
@ -156,6 +156,8 @@ PLT_DUO		.EQU	17		; DUODYNE Z80 SYSTEM
 PLT_HEATH	.EQU	18		; HEATHKIT H8 Z80 SYSTEM
 PLT_EPITX	.EQU	19		; Z180 MINI-ITX
 PLT_MON		.EQU	20		; MONSPUTER
+PLT_STDZ180	.EQU	21		; GENESIS Z180 SYSTEM
+PLT_NABU	.EQU	22		; NABU PERSONAL COMPUTER
 ;
 ; HBIOS GLOBAL ERROR RETURN VALUES
 ;
--- a/Source/HBIOS/hdsk.asm
+++ b/Source/HBIOS/hdsk.asm
@ -22,11 +22,11 @@ HDSK_DEV	.EQU	0		; OFFSET OF DEVICE NUMBER (BYTE)
 HDSK_STAT	.EQU	1		; OFFSET OF STATUS (BYTE)
 HDSK_LBA	.EQU	2		; OFFSET OF LBA (DWORD)
 ;
-	.ECHO	"HDSK: IO="
-	.ECHO	HDSK_IO
-	.ECHO	", DEVICE COUNT="
-	.ECHO	HDSK_DEVCNT
-	.ECHO	"\n"
+	DEVECHO	"HDSK: IO="
+	DEVECHO	HDSK_IO
+	DEVECHO	", DEVICE COUNT="
+	DEVECHO	HDSK_DEVCNT
+	DEVECHO	"\n"
 ;
 HDSK_CFGTBL:
 	; DEVICE 0
--- a/Source/HBIOS/icm.asm
+++ b/Source/HBIOS/icm.asm
@ -31,6 +31,10 @@ ICM_PPIA		.EQU 	ICMPPIBASE + 0	; PORT A
 ICM_PPIB		.EQU 	ICMPPIBASE + 1	; PORT B
 ICM_PPIC		.EQU 	ICMPPIBASE + 2	; PORT C
 ICM_PPIX	 	.EQU 	ICMPPIBASE + 3	; PPI CONTROL PORT
+;
+	DEVECHO	"ICM: IO="
+	DEVECHO	ICMPPIBASE
+	DEVECHO	"\n"
 ;
 ;__ICM_INIT__________________________________________________________________________________________
 ;
--- a/Source/HBIOS/ide.asm
+++ b/Source/HBIOS/ide.asm
@ -214,26 +214,26 @@ IDE_DEV0M:	; DEVICE 0, MASTER
 	.DB	IDE0DATHI		; IO BASE ADDRESS
 	.DW	IDE_DEV0S		; PARTNER
 ;
-	.ECHO	"IDE: MODE="
+	DEVECHO	"IDE: MODE="
  #IF (IDE0MODE == IDEMODE_NONE)
-	.ECHO	"NONE"
+	DEVECHO	"NONE"
  #ENDIF
  #IF (IDE0MODE == IDEMODE_DIO)
-	.ECHO	"DIO"
+	DEVECHO	"DIO"
  #ENDIF
  #IF (IDE0MODE == IDEMODE_DIDE)
-	.ECHO	"DIDE"
+	DEVECHO	"DIDE"
  #ENDIF
  #IF (IDE0MODE == IDEMODE_MK4)
-	.ECHO	"MK4"
+	DEVECHO	"MK4"
  #ENDIF
  #IF (IDE0MODE == IDEMODE_RC)
-	.ECHO	"RC"
+	DEVECHO	"RC"
  #ENDIF
-	.ECHO	", IO="
-	.ECHO	IDE0BASE
-	.ECHO	", MASTER"
-	.ECHO	"\n"
+	DEVECHO	", IO="
+	DEVECHO	IDE0BASE
+	DEVECHO	", MASTER"
+	DEVECHO	"\n"
 ;
 IDE_DEV0S:	; DEVICE 0, SLAVE
 	.DB	$FE			; DRIVER DEVICE NUMBER (FILLED DYNAMICALLY)
@ -249,26 +249,26 @@ IDE_DEV0S:	; DEVICE 0, SLAVE
 	.DB	IDE0DATHI		; IO BASE ADDRESS
 	.DW	IDE_DEV0M		; PARTNER
 ;
-	.ECHO	"IDE: MODE="
+	DEVECHO	"IDE: MODE="
  #IF (IDE0MODE == IDEMODE_NONE)
-	.ECHO	"NONE"
+	DEVECHO	"NONE"
  #ENDIF
  #IF (IDE0MODE == IDEMODE_DIO)
-	.ECHO	"DIO"
+	DEVECHO	"DIO"
  #ENDIF
  #IF (IDE0MODE == IDEMODE_DIDE)
-	.ECHO	"DIDE"
+	DEVECHO	"DIDE"
  #ENDIF
  #IF (IDE0MODE == IDEMODE_MK4)
-	.ECHO	"MK4"
+	DEVECHO	"MK4"
  #ENDIF
  #IF (IDE0MODE == IDEMODE_RC)
-	.ECHO	"RC"
+	DEVECHO	"RC"
  #ENDIF
-	.ECHO	", IO="
-	.ECHO	IDE0BASE
-	.ECHO	", SLAVE"
-	.ECHO	"\n"
+	DEVECHO	", IO="
+	DEVECHO	IDE0BASE
+	DEVECHO	", SLAVE"
+	DEVECHO	"\n"
 #ENDIF
 ;
 #IF (IDECNT >= 2)
@ -287,26 +287,26 @@ IDE_DEV1M:	; DEVICE 1, MASTER
 	.DB	IDE1DATHI		; IO BASE ADDRESS
 	.DW	IDE_DEV1S		; PARTNER
 ;
-	.ECHO	"IDE: MODE="
+	DEVECHO	"IDE: MODE="
  #IF (IDE1MODE == IDEMODE_NONE)
-	.ECHO	"NONE"
+	DEVECHO	"NONE"
  #ENDIF
  #IF (IDE1MODE == IDEMODE_DIO)
-	.ECHO	"DIO"
+	DEVECHO	"DIO"
  #ENDIF
  #IF (IDE1MODE == IDEMODE_DIDE)
-	.ECHO	"DIDE"
+	DEVECHO	"DIDE"
  #ENDIF
  #IF (IDE1MODE == IDEMODE_MK4)
-	.ECHO	"MK4"
+	DEVECHO	"MK4"
  #ENDIF
  #IF (IDE1MODE == IDEMODE_RC)
-	.ECHO	"RC"
+	DEVECHO	"RC"
  #ENDIF
-	.ECHO	", IO="
-	.ECHO	IDE1BASE
-	.ECHO	", MASTER"
-	.ECHO	"\n"
+	DEVECHO	", IO="
+	DEVECHO	IDE1BASE
+	DEVECHO	", MASTER"
+	DEVECHO	"\n"
 ;
 IDE_DEV1S:	; DEVICE 1, SLAVE
 	.DB	$FE			; DRIVER DEVICE NUMBER (FILLED DYNAMICALLY)
@ -322,26 +322,26 @@ IDE_DEV1S:	; DEVICE 1, SLAVE
 	.DB	IDE1DATHI		; IO BASE ADDRESS
 	.DW	IDE_DEV1M		; PARTNER
 ;
-	.ECHO	"IDE: MODE="
+	DEVECHO	"IDE: MODE="
  #IF (IDE1MODE == IDEMODE_NONE)
-	.ECHO	"NONE"
+	DEVECHO	"NONE"
  #ENDIF
  #IF (IDE1MODE == IDEMODE_DIO)
-	.ECHO	"DIO"
+	DEVECHO	"DIO"
  #ENDIF
  #IF (IDE1MODE == IDEMODE_DIDE)
-	.ECHO	"DIDE"
+	DEVECHO	"DIDE"
  #ENDIF
  #IF (IDE1MODE == IDEMODE_MK4)
-	.ECHO	"MK4"
+	DEVECHO	"MK4"
  #ENDIF
  #IF (IDE1MODE == IDEMODE_RC)
-	.ECHO	"RC"
+	DEVECHO	"RC"
  #ENDIF
-	.ECHO	", IO="
-	.ECHO	IDE1BASE
-	.ECHO	", SLAVE"
-	.ECHO	"\n"
+	DEVECHO	", IO="
+	DEVECHO	IDE1BASE
+	DEVECHO	", SLAVE"
+	DEVECHO	"\n"
 #ENDIF
 ;
 #IF (IDECNT >= 3)
@ -360,26 +360,26 @@ IDE_DEV2M:	; DEVICE 2, MASTER
 	.DB	IDE2DATHI		; IO BASE ADDRESS
 	.DW	IDE_DEV2S		; PARTNER
 ;
-	.ECHO	"IDE: MODE="
+	DEVECHO	"IDE: MODE="
  #IF (IDE2MODE == IDEMODE_NONE)
-	.ECHO	"NONE"
+	DEVECHO	"NONE"
  #ENDIF
  #IF (IDE2MODE == IDEMODE_DIO)
-	.ECHO	"DIO"
+	DEVECHO	"DIO"
  #ENDIF
  #IF (IDE2MODE == IDEMODE_DIDE)
-	.ECHO	"DIDE"
+	DEVECHO	"DIDE"
  #ENDIF
  #IF (IDE2MODE == IDEMODE_MK4)
-	.ECHO	"MK4"
+	DEVECHO	"MK4"
  #ENDIF
  #IF (IDE2MODE == IDEMODE_RC)
-	.ECHO	"RC"
+	DEVECHO	"RC"
  #ENDIF
-	.ECHO	", IO="
-	.ECHO	IDE2BASE
-	.ECHO	", MASTER"
-	.ECHO	"\n"
+	DEVECHO	", IO="
+	DEVECHO	IDE2BASE
+	DEVECHO	", MASTER"
+	DEVECHO	"\n"
 ;
 IDE_DEV2S:	; DEVICE 2, SLAVE
 	.DB	$FE			; DRIVER DEVICE NUMBER (FILLED DYNAMICALLY)
@ -395,26 +395,26 @@ IDE_DEV2S:	; DEVICE 2, SLAVE
 	.DB	IDE2DATHI		; IO BASE ADDRESS
 	.DW	IDE_DEV1M		; PARTNER
 ;
-	.ECHO	"IDE: MODE="
+	DEVECHO	"IDE: MODE="
  #IF (IDE2MODE == IDEMODE_NONE)
-	.ECHO	"NONE"
+	DEVECHO	"NONE"
  #ENDIF
  #IF (IDE2MODE == IDEMODE_DIO)
-	.ECHO	"DIO"
+	DEVECHO	"DIO"
  #ENDIF
  #IF (IDE2MODE == IDEMODE_DIDE)
-	.ECHO	"DIDE"
+	DEVECHO	"DIDE"
  #ENDIF
  #IF (IDE2MODE == IDEMODE_MK4)
-	.ECHO	"MK4"
+	DEVECHO	"MK4"
  #ENDIF
  #IF (IDE2MODE == IDEMODE_RC)
-	.ECHO	"RC"
+	DEVECHO	"RC"
  #ENDIF
-	.ECHO	", IO="
-	.ECHO	IDE2BASE
-	.ECHO	", SLAVE"
-	.ECHO	"\n"
+	DEVECHO	", IO="
+	DEVECHO	IDE2BASE
+	DEVECHO	", SLAVE"
+	DEVECHO	"\n"
 #ENDIF
 ;
 #IF ($ - IDE_CFGTBL) != (IDE_DEVCNT * IDE_CFGSIZ)
--- a/Source/HBIOS/imm.asm
+++ b/Source/HBIOS/imm.asm
@ -1526,16 +1526,16 @@ IMM0_CFG:	; DEVICE 0
 	.DW	0,0			; DEVICE CAPACITY
 	.DW	0,0			; CURRENT LBA
 ;
-	.ECHO	"IMM: MODE="
+	DEVECHO	"IMM: MODE="
  #IF (IMMMODE == IMMMODE_SPP)
-	.ECHO	"SPP"
+	DEVECHO	"SPP"
  #ENDIF
  #IF (IMMMODE == IMMMODE_MG014)
-	.ECHO	"MG014"
+	DEVECHO	"MG014"
  #ENDIF
-	.ECHO	", IO="
-	.ECHO	IMM0BASE
-	.ECHO	"\n"
+	DEVECHO	", IO="
+	DEVECHO	IMM0BASE
+	DEVECHO	"\n"
 #ENDIF
 ;
 #IF (IMMCNT >= 2)
@ -1548,16 +1548,16 @@ IMM1_CFG:	; DEVICE 1
 	.DW	0,0			; DEVICE CAPACITY
 	.DW	0,0			; CURRENT LBA
 ;
-	.ECHO	"IMM: MODE="
+	DEVECHO	"IMM: MODE="
  #IF (IMMMODE == IMMMODE_SPP)
-	.ECHO	"SPP"
+	DEVECHO	"SPP"
  #ENDIF
  #IF (IMMMODE == IMMMODE_MG014)
-	.ECHO	"MG014"
+	DEVECHO	"MG014"
  #ENDIF
-	.ECHO	", IO="
-	.ECHO	IMM1BASE
-	.ECHO	"\n"
+	DEVECHO	", IO="
+	DEVECHO	IMM1BASE
+	DEVECHO	"\n"
 #ENDIF
 ;
 #IF ($ - IMM_CFG) != (IMMCNT * IMM_CFGSIZ)
--- a/Source/HBIOS/intrtc.asm
+++ b/Source/HBIOS/intrtc.asm
@ -5,7 +5,7 @@
 ;
 INTRTC_BUFSIZ	.EQU	6	; SIX BYTE BUFFER (YYMMDDHHMMSS)
 ;
-		.ECHO	"INTRTC: ENABLED\n"
+		DEVECHO	"INTRTC: ENABLED\n"
 ;
 ; RTC DEVICE INITIALIZATION ENTRY
 ;
--- a/Source/HBIOS/kbd.asm
+++ b/Source/HBIOS/kbd.asm
@ -56,7 +56,7 @@ KBD_STATUS	.DB	0	; CURRENT STATUS BITS (SEE ABOVE)
 KBD_REPEAT	.DB	0	; CURRENT REPEAT RATE
 KBD_IDLE	.DB	0	; IDLE COUNT
 ;
-	.ECHO	"KBD: ENABLED\n"
+	DEVECHO	"KBD: ENABLED\n"
 ;
 ;__________________________________________________________________________________________________
 ; KEYBOARD INITIALIZATION
--- a/Source/HBIOS/kio.asm
+++ b/Source/HBIOS/kio.asm
@ -25,6 +25,10 @@ KIO_KIOCMD	.EQU	KIOBASE + $0E
 KIO_KIOCMDB	.EQU	KIOBASE + $0F
 ;
 ;
+;
+	DEVECHO	"KIO: IO="
+	DEVECHO	KIOBASE
+	DEVECHO	"\n"
 ;
 KIO_PREINIT:
 	CALL	KIO_DETECT
--- a/Source/HBIOS/lpt.asm
+++ b/Source/HBIOS/lpt.asm
@ -421,16 +421,16 @@ LPT0_CFG:
 	.DB	LPT0BASE		; BASE PORT
 	.DW	0			; LINE CONFIGURATION
 ;
-	.ECHO	"LPT: MODE="
+	DEVECHO	"LPT: MODE="
  #IF (LPTMODE == LPTMODE_SPP)
-	.ECHO	"SPP"
+	DEVECHO	"SPP"
  #ENDIF
  #IF (LPTMODE == LPTMODE_MG014)
-	.ECHO	"MG014"
+	DEVECHO	"MG014"
  #ENDIF
-	.ECHO	", IO="
-	.ECHO	LPT0BASE
-	.ECHO	"\n"
+	DEVECHO	", IO="
+	DEVECHO	LPT0BASE
+	DEVECHO	"\n"
 ;
 LPT_CFGSIZ	.EQU	$ - LPT_CFG	; SIZE OF ONE CFG TABLE ENTRY
 ;
@ -444,16 +444,16 @@ LPT1_CFG:
 	.DB	LPT1BASE		; BASE PORT
 	.DW	0			; LINE CONFIGURATION
 ;
-	.ECHO	"LPT: MODE="
+	DEVECHO	"LPT: MODE="
  #IF (LPTMODE == LPTMODE_SPP)
-	.ECHO	"SPP"
+	DEVECHO	"SPP"
  #ENDIF
  #IF (LPTMODE == LPTMODE_MG014)
-	.ECHO	"MG014"
+	DEVECHO	"MG014"
  #ENDIF
-	.ECHO	", IO="
-	.ECHO	LPT1BASE
-	.ECHO	"\n"
+	DEVECHO	", IO="
+	DEVECHO	LPT1BASE
+	DEVECHO	"\n"
 ;
 #ENDIF
 ;
--- a/Source/HBIOS/md.asm
+++ b/Source/HBIOS/md.asm
@ -40,7 +40,7 @@ MD_CFGTBL:
 	.DB	MID_MDRAM		; DEVICE MEDIA ID
 	.DB	MD_ARAM			; DEVICE ATTRIBUTE
 ;
-	.ECHO	"MD: TYPE=RAM\n"
+	DEVECHO	"MD: TYPE=RAM\n"
 #ENDIF
 ;
 #IF (MDROM)
@ -51,7 +51,7 @@ MD_CFGTBL:
 	.DB	MID_MDROM		; DEVICE MEDIA ID
 	.DB	MD_AROM			; DEVICE ATTRIBUTE
 ;
-	.ECHO	"MD: TYPE=ROM\n"
+	DEVECHO	"MD: TYPE=ROM\n"
 #ENDIF
 ;
 MD_DEVCNT	.EQU	($ - MD_CFGTBL) / MD_CFGSIZ
--- a/Source/HBIOS/mky.asm
+++ b/Source/HBIOS/mky.asm
@ -177,6 +177,11 @@ SCANCODE_TBL:
 	.DB	S_RETURN,	S_SELECT,	S_BACKSPACE,	S_STOP,		S_TAB,		S_ESC,		S_F5,		S_F4		; 07
 	.DB	S_RIGHT,	S_DOWN,		S_UP,		S_LEFT,		S_DELETE,	S_INSERT,	S_HOME,		S_SPACE		; 08

+
+	DEVECHO	"MKY: IO="
+	DEVECHO	MKY_REGA
+	DEVECHO	"\n"
+
 ;__________________________________________________________________________________________________
 ; KEYBOARD INITIALIZATION
 ;__________________________________________________________________________________________________
--- a/Source/HBIOS/nabu.asm
+++ b/Source/HBIOS/nabu.asm
@ -0,0 +1,123 @@
+;
+;==================================================================================================
+; NABU INTERRUPT INTERCEPTOR
+;==================================================================================================
+;
+NABU_INT1CLR	.EQU	$68
+NABU_TICCNT	.EQU	$FFEA		; TICCNT AT $FFEA IS COPIED DOWN TO $000B
+;
+; NABU INTERRUPT ENABLE PORT AND STATUS PORTS ARE MANAGED BY THE
+; PSG IO PORTS.
+;
+; INTERRUPT ENABLE (OUTPUT) - PSG PORT A
+;
+;	D7 - HCCA Receive
+;	D6 - HCCA Send
+;	D5 - Keyboard
+;	D4 - Video Frame Sync
+;	D3 - Option Card 0 (J9)
+;	D2 - Option Card 1 (J10)
+;	D1 - Option Card 2 (J11)
+;	DO - Option Card 3 (J12)
+;
+; STATUS BYTE (INPUT) - PSG PORT B
+;
+;	D7 - N.C.
+;	D6 - Overrun Error (HCCA UART)
+;	D5 - Framing Error (HCCA UART)
+;	D4 - Printer Busy
+;	D3 - A2 Priority
+;	D2 - A1 Priority
+;	D1 - AO Priority
+;	DO - Interrupt Request
+;
+; PORTS TO MANAGE PSG
+;
+NABU_RSEL	.EQU	$41		; SELECT PSG REGISTER
+NABU_RDAT	.EQU	$40		; WRITE TO SELECTED REGISTER
+NABU_RIN	.EQU	$40		; READ FROM SELECTED REGISTER
+;
+	DEVECHO	"NABU: IO="
+	DEVECHO	NABU_INT1CLR
+	DEVECHO	"\n"
+;
+;
+; HARDWARE RESET PRIOR TO ROMWBW CONSOLE INITIALIZATION
+;
+NABU_PREINIT:
+	; INITIALIZE THE NABU PSG I/O PORTS
+	; PORT A IN WRITE MODE AND SET ALL BITS TO ZERO
+	; PORT B IN READ MODE
+;
+	CALL	NABU_SETPSG	
+;
+;#IF (INTMODE == 1)
+;	; ADD TO INTERRUPT CHAIN
+;	LD	HL,NABU_STAT
+;	CALL	HB_ADDIM1		; ADD TO IM1 CALL LIST
+;#ENDIF
+;
+;#IF (INTMODE == 2)
+;	LD	HL,NABU_STAT
+;	LD	(IVT(INT_NABUKB)),HL	; IVT INDEX
+;#ENDIF
+;	RET
+;
+NABU_INIT:
+	CALL	NEWLINE			; FORMATTING
+	PRTS("NABU: INT1$")
+;	XOR	A
+;	OUT	(NABU_INT1CLR),A
+	RET				; DONE
+;
+NABU_SETPSG:
+	; SET I/O PORT MODES
+	LD	A,7			; PSG R7 (ENABLE REG)
+	OUT	(NABU_RSEL),A		; SELECT IT
+	LD	A,%01111111		; PORT B INPUT, PORT A OUPUT
+	OUT	(NABU_RDAT),A		; SET IT
+;
+	; SET PORT A TO VALUE 0
+	LD	A,14			; PSG R14 (PORT A DATA)
+	OUT	(NABU_RSEL),A		; SELECT IT
+#IF (INTMODE > 0)
+  #IF (TMSTIMENABLE == TRUE)
+	LD	A,%00110000		; ENABLE NABU KB & VDP INTS
+  #ELSE
+	LD	A,%00100000		; ENABLE NABU KB INTS
+  #ENDIF
+#ELSE
+	XOR	A
+#ENDIF
+	OUT	(NABU_RDAT),A		; SET IT
+;
+	LD	A,15
+	OUT	(NABU_RSEL),A
+	IN	A,(NABU_RIN)
+	RET
+;
+;  INTERRUPT ENTRY POINT
+;
+NABU_STAT:
+;	CALL	NABU_SETPSG
+;	XOR	A
+;	OUT	(NABU_INT1CLR),A	; CLEAR THE INTERRUPT
+	LD	HL,(NABU_TICCNT)	; INCREMENT NABU TICK COUNTER
+	
+	
+	INC	HL			; ... IN HBIOS PROXY
+	LD	(NABU_TICCNT),HL
+;	LD	A,(NABU_HBTICK)		; INCREMENT INTERNAL TICK CTR
+;	INC	A
+;	LD	(NABU_HBTICK),A
+;	CP	$0A			; CALL HB_TICK EVERY 10 INTERRUPTS (50HZ)
+;	RET	NZ			; NOT TIME THEN JUST RETURN
+	CALL	HB_TICK			; DO NORMAL HBIOS TICK
+	XOR	A
+;	LD	(NABU_HBTICK),A		; RESET HBTICK COUNTER
+	INC	A			; INTERRUPT HANDLED
+	RET
+;
+NABU_HBTICK:
+	.DB	0			; INTERNAL TICK CTR
+;
--- a/Source/HBIOS/nabukb.asm
+++ b/Source/HBIOS/nabukb.asm
@ -0,0 +1,265 @@
+;======================================================================
+;	NABU KEYBOARD DRIVER
+;
+;	CREATED BY: LES BIRD
+;
+;======================================================================
+;
+; NABU KEYBOARD CODES:
+;
+;  $00-$7F	STANDARD ASCII CODES
+;  $80-$8F	JOYSTICK PREFIXES ($80 = JS1, $81 = JS2)
+;  $90-$9F	KEYBOARD ERROR CODES
+;  $A0-$BF	JOYSTICK DATA
+;  $C0-$DF	UNUSED
+;  $E0-$EF	SPECIAL KEYS
+;
+; NOTE THAT THE ERROR CODE $94 IS A WATCHDOG TIMER THAT WILL BE
+; SENT BY THE KEYBOARD EVERY 3.7 SECONDS.
+;
+; THE CODE BELOW WILL IGNORE (SWALLOW) THE ERROR CODES ($90-$9F) AND
+; WILL TRANSLATE SPECIAL KEYS ($E0-$FF) TO ROMWBW EQUIVALENTS.  ALL
+; OTHER KEYS WILL BE PASSED THROUGH AS IS.
+;
+; KBPORT EQU	$90
+;
+; POLL FOR INPUT
+; KBLOOP:
+;	IN	A,(KBPORT+1)
+;	BIT	1,A    
+;	JR	Z,KBLOOP
+;	IN	A,(KBPORT)
+;
+; INIT:
+;	XOR	A
+;	CALL	SUB12
+;	CALL	SUB12
+;	CALL	SUB12
+;	CALL	SUB12
+;	CALL	SUB12
+;	LD	A,40H
+;	CALL	SUB12
+;	LD	A,4EH
+;	CALL	SUB12
+;	LD	A,04H
+;	CALL	SUB12
+;
+NABUKB_IODAT	.EQU	$90		; KEYBOARD DATA (READ)
+NABUKB_IOSTAT	.EQU	$91		; STATUS (READ), CMD (WRITE)
+;
+	DEVECHO	"NABUKB: IO="
+	DEVECHO	NABUKB_IODAT
+	DEVECHO	"\n"
+;
+; SETUP INTERRUPT HANDLING, IF ENABLED
+;
+NABUKB_PREINIT:
+#IF (INTMODE == 1)
+	; ADD TO INTERRUPT CHAIN
+	LD	HL,NABUKB_INT
+	CALL	HB_ADDIM1		; ADD TO IM1 CALL LIST
+#ENDIF
+;
+#IF (INTMODE == 2)
+	; INSTALL VECTOR
+	LD	HL,NABUKB_INT
+	LD	(IVT(INT_NABUKB)),HL	; IVT INDEX
+#ENDIF
+	RET
+;
+; INITIALZIZE THE KEYBOARD CONTROLLER.
+;
+NABUKB_INIT:
+	CALL	NEWLINE
+	PRTS("NABUKB: IO=0x$")
+	LD	A,NABUKB_IODAT
+	CALL	PRTHEXBYTE
+;
+	XOR	A
+	CALL	NABUKB_PUT
+	CALL	NABUKB_PUT
+	CALL	NABUKB_PUT
+	CALL	NABUKB_PUT
+	CALL	NABUKB_PUT
+	LD	A,$40		; RESET 8251
+	CALL	NABUKB_PUT
+	LD	A,$4E		; 1 STOP BIT, 8 BITS, 64X CLK
+	CALL	NABUKB_PUT
+	LD	A,$04		; ENABLE RECV
+	CALL	NABUKB_PUT
+;
+	XOR	A
+	RET
+;
+#IF (INTMODE > 0)
+;
+; INTERRUPT HANDLER FOR NABU KEYBOARD.  HANDLES INTERRUPTS FOR EITHER
+; INT MODE 1 OR INT MODE 2.  THE KEYBOARD BUFFER IS JUST A SINGLE CHAR
+; AT THIS POINT.  NEW CHARACTERS ARRIVING WHEN THE BUFFER IS FULL WILL
+; BE DISCARDED.
+;
+NABUKB_INT:
+	IN	A,(NABUKB_IOSTAT)	; GET KBD STATUS
+	AND	$02			; CHECK DATA RDY BIT
+	RET	Z			; ABORT W/ Z (INT NOT HANDLED)
+;
+	;CALL	PC_LT			; *DEBUG*
+	IN	A,(NABUKB_IODAT)	; GET THE KEY
+	LD	E,A			; STASH IN REG E
+	;CALL	PRTHEXBYTE		; *DEBUG*
+	;CALL	PC_GT			; *DEBUG*
+;
+	LD	A,(NABUKB_KSTAT)	; GET KEY BUFFER STAT
+	OR	A			; SET FLAGS
+	RET	NZ			; BUFFER FULL, BAIL OUT W/ NZ (INT HANDLED), KEY DISCARDED
+;
+	LD	A,E			; RECOVER THE KEY CODE
+	CALL	NABUKB_XB		; TRANSLATE AND BUFFER KEY
+	OR	$FF			; SIGNAL INT HANDLED
+	RET				; DONE
+;
+#ENDIF
+;
+; NORMAL HBIOS CHAR INPUT STATUS.  IF INTERRUPTS ARE NOT ACTIVE, THEN
+; KEYBOARD POLLING IS IMPLEMENTED HERE.
+;
+NABUKB_STAT:
+	LD	A,(NABUKB_KSTAT)	; GET KEY WAITING STATUS
+	OR	A			; SET FLAGS
+#IF (INTMODE > 0)
+	JR	Z,NABUKB_STATX		; BAIL OUT W/ Z (NO KEY)
+	RET				; KEY WAITING, ALL SET
+#ELSE
+	RET	NZ			; KEY WAITING, ALL SET
+	IN	A,(NABUKB_IOSTAT)	; GET KBD STATUS
+	AND	$02			; CHECK DATA RDY BIT
+	JR	Z,NABUKB_STATX		; BAIL OUT W/ Z (NO KEY)
+	IN	A,(NABUKB_IODAT)	; GET THE KEY
+	CALL	NABUKB_XB		; TRANSLATE AND BUFFER KEY
+	LD	A,(NABUKB_KSTAT)	; GET NEW KEY WAITING STATUS
+	OR	A			; SET FLAGS
+	RET				; DONE
+#ENDIF
+;
+NABUKB_STATX:
+	XOR	A			; SIGNAL NO CHAR READY
+	JP	CIO_IDLE		; RETURN VIA IDLE PROCESSOR
+;
+; ROUTINE TO TRANSLATE AND BUFFER INCOMING NABU KEYBOARD KEYCODES
+;
+NABUKB_XB:
+	BIT	7,A			; HIGH BIT IS SPECIAL CHAR
+	JR	Z,NABUKB_XB2		; IF NORMAL CHAR, BUFFER IT
+	CP	$90			; START OF ERR CODES
+	JR	C,NABUKB_XB1		; NOT ERR CODE, CONTINUE
+	CP	$A0			; END OF ERR CODES
+	JR	NC,NABUKB_XB1		; NOT ERR CODE, CONTINUE
+	RET				; DISCARD ERR CODE AND RETURN
+NABUKB_XB1:
+	CP	$E0			; SPECIAL CHARACTER?
+	JR	C,NABUKB_XB2		; IF NOT, SKIP XLAT, BUFFER KEY
+	CALL	NABUKB_XLAT		; IF SO, TRANSLATE IT
+	RET	C			; CF INDICATES INVALID, DISCARD AND RETURN
+NABUKB_XB2:
+	LD	(NABUKB_KEY),A		; BUFFER IT
+	LD	A,1			; SIGNAL KEY WAITING
+	LD	(NABUKB_KSTAT),A	; SAVE IT
+	RET				; DONE
+;
+; ROUTINE TO TRANSLATE SPECIAL NABU KEYBOARD KEY CODES
+;
+NABUKB_XLAT:
+	; NABU KEYBOARD USES $E0-$FF FOR SPECIAL KEYS
+	; HERE WE TRANSLATE TO ROMWBW SPECIAL KEYS AS BEST WE CAN
+	; CF IS SET ON RETURN IF KEY IS INVALID (NO TRANSLATION)
+	SUB	$E0			; ZERO OFFSET
+	RET	C			; ABORT IF < $E0, CF SET!
+	LD	HL,NABUKB_XTBL		; POINT TO XLAT TABLE
+	CALL	ADDHLA			; OFFSET BY SPECIAL KEY VAL
+	LD	A,(HL)			; GET TRANSLATED VALUE
+	OR	A			; CHECK FOR N/A (0)
+	RET	NZ			; XLAT OK, RET W/ CF CLEAR
+	SCF				; SIGNAL INVALID
+	RET				; DONE
+;
+NABUKB_XLAT1:
+	SCF				; SIGNAL INVALID
+	RET				; AND DONE
+;
+; FLUSH KEYBOARD BUFFER
+;
+NABUKB_FLUSH:
+	XOR	A
+	LD	(NABUKB_KSTAT),A
+	RET
+;
+; WAIT FOR A KEY TO BE READY AND RETURN IT.
+;
+NABUKB_READ:
+	CALL	NABUKB_STAT		; CHECK FOR KEY READY
+	JR	Z,NABUKB_READ		; LOOP TIL ONE IS READY
+	LD	A,(NABUKB_KEY)		; GET THE BUFFERED KEY
+	LD	E,A			; PUT IN E FOR RETURN
+	XOR	A			; ZERO TO ACCUM
+	LD	C,A			; NO SCANCODE
+	LD	D,A			; NO KEYSTATE
+	LD	(NABUKB_KSTAT),A	; CLEAR KEY WAITING STATUS
+	RET				; AND RETURN
+;
+; HELPER ROUTINE TO WRITE 
+;
+NABUKB_PUT:
+	OUT	(NABUKB_IOSTAT),A
+	NOP
+	NOP
+	NOP
+	NOP
+	NOP
+	RET
+;
+;
+;
+NABUKB_KSTAT	.DB	0	; KEY STATUS
+NABUKB_KEY	.DB	0	; KEY BUFFER
+;
+; THIS TABLE TRANSLATES THE NABU KEYBOARD SPECIAL CHARS INTO
+; ANALOGOUS ROMWBW STANDARD SPECIAL CHARACTERS.  THE TABLE STARTS WITH
+; NABU KEY CODE $E0 AND HANDLES $20 POSSIBLE VALUES ($E0-$FF)
+; THE SPECIAL KEYS SEND A SPECIFIC KEYCODE TO INDICATE DOWN (KEY
+; PRESSED) AND UP (KEY RELEASED).  WE WILL ARBITRARILY CHOOSE TO
+; RESPOND TO KEY PRESSED.  a TRANSLATION VALUE OF $00 MEANS THAT THE
+; KEY CODE SHOULD BE DISCARDED.
+;
+NABUKB_XTBL:
+	.DB	$F9		; $E0, RIGHT ARROW (DN) -> RIGHT ARROW
+	.DB	$F8		; $E1, LEFT ARROW (DN) -> LEFT ARROW
+	.DB	$F6		; $E2, UP ARROW (DN) -> UP ARROW
+	.DB	$F7		; $E3, DOWN ARROW (DN) -> DOWN ARROW
+	.DB	$F5		; $E4, PAGE RIGHT (DN) -> PAGE DOWN
+	.DB	$F4		; $E5, PAGE LEFT (DN) -> PAGE UP
+	.DB	$F3		; $E6, NO (DN) -> END
+	.DB	$F2		; $E7, YES (DN) -> HOME
+	.DB	$EE		; $E8, SYM (DN) -> SYSRQ
+	.DB	$EF		; $E9, PAUSE (DN) -> PAUSE
+	.DB	$00		; $EA, TV/NABU (DN) -> APP
+	.DB	$00		; $EB, N/A
+	.DB	$00		; $EC, N/A
+	.DB	$00		; $ED, N/A
+	.DB	$00		; $EE, N/A
+	.DB	$00		; $EF, N/A
+	.DB	$00		; $F0, RIGHT ARROW (UP)
+	.DB	$00		; $F1, LEFT ARROW (UP)
+	.DB	$00		; $F2, UP ARROW (UP)
+	.DB	$00		; $F3, DOWN ARROW (UP)
+	.DB	$00		; $F4, PAGE RIGHT (UP)
+	.DB	$00		; $F5, PAGE LEFT (UP)
+	.DB	$00		; $F6, NO (UP)
+	.DB	$00		; $F7, YES (UP)
+	.DB	$00		; $F8, SYM (UP)
+	.DB	$00		; $F9, PAUSE (UP)
+	.DB	$00		; $FA, TV/NABU (UP)
+	.DB	$00		; $FB, N/A
+	.DB	$00		; $FC, N/A
+	.DB	$00		; $FD, N/A
+	.DB	$00		; $FE, N/A
+	.DB	$00		; $FF, N/A
--- a/Source/HBIOS/pcf.asm
+++ b/Source/HBIOS/pcf.asm
@ -94,9 +94,9 @@ PCF_ACKTO	.EQU	65000
 PCF_BBTO	.EQU	65000
 PCF_LABDLY	.EQU	65000
 ;
-	.ECHO	"PCF: IO="
-	.ECHO	PCF_BASE
-	.ECHO	"\n"
+	DEVECHO	"PCF: IO="
+	DEVECHO	PCF_BASE
+	DEVECHO	"\n"
 ;
 ; DATA PORT REGISTERS
 ;
--- a/Source/HBIOS/pio.asm
+++ b/Source/HBIOS/pio.asm
@ -308,9 +308,9 @@ PIO0A_CFG:
 	.DW	DEFSERCFG		; LINE CONFIGURATION
 	.DW	PIO0A_RCVBUF		; POINTER TO RCV BUFFER STRUCT
 ;
-	.ECHO	"PIO: IO="
-	.ECHO	PIO0BASE
-	.ECHO	", CHANNEL A\n"
+	DEVECHO	"PIO: IO="
+	DEVECHO	PIO0BASE
+	DEVECHO	", CHANNEL A\n"
 ;
 PIO_CFGSIZ	.EQU	$ - PIO_CFG	; SIZE OF ONE CFG TABLE ENTRY
 ;
@ -324,9 +324,9 @@ PIO0B_CFG:
 	.DW	DEFSERCFG		; LINE CONFIGURATION
 	.DW	PIO0B_RCVBUF		; POINTER TO RCV BUFFER STRUCT
 ;
-	.ECHO	"PIO: IO="
-	.ECHO	PIO0BASE
-	.ECHO	", CHANNEL B\n"
+	DEVECHO	"PIO: IO="
+	DEVECHO	PIO0BASE
+	DEVECHO	", CHANNEL B\n"
 ;
 #IF (PIOCNT >= 2)
 ;
@ -340,9 +340,9 @@ PIO1A_CFG:
 	.DW	DEFSERCFG		; LINE CONFIGURATION
 	.DW	PIO1A_RCVBUF		; POINTER TO RCV BUFFER STRUCT
 ;
-	.ECHO	"PIO: IO="
-	.ECHO	PIO1BASE
-	.ECHO	", CHANNEL A\n"
+	DEVECHO	"PIO: IO="
+	DEVECHO	PIO1BASE
+	DEVECHO	", CHANNEL A\n"
 ;
 	; PIO1 CHANNEL B
 PIO1B_CFG:
@ -354,9 +354,9 @@ PIO1B_CFG:
 	.DW	DEFSERCFG		; LINE CONFIGURATION
 	.DW	PIO1B_RCVBUF		; POINTER TO RCV BUFFER STRUCT
 ;
-	.ECHO	"PIO: IO="
-	.ECHO	PIO1BASE
-	.ECHO	", CHANNEL B\n"
+	DEVECHO	"PIO: IO="
+	DEVECHO	PIO1BASE
+	DEVECHO	", CHANNEL B\n"
 ;
 #ENDIF
 ;
--- a/Source/HBIOS/pkd.asm
+++ b/Source/HBIOS/pkd.asm
@ -66,9 +66,9 @@ PKD_CMD_FIFO	.EQU	%01000000		; READ FIFO
 ;
 PKD_PRESCL	.EQU	PKDOSC/100000		; PRESCALER
 ;
-	.ECHO	"PKD: IO="
-	.ECHO	PKDPPIBASE
-	.ECHO	"\n"
+	DEVECHO	"PKD: IO="
+	DEVECHO	PKDPPIBASE
+	DEVECHO	"\n"
 ;
 ;__PKD_PREINIT_______________________________________________________________________________________
 ;
--- a/Source/HBIOS/ppa.asm
+++ b/Source/HBIOS/ppa.asm
@ -1386,16 +1386,16 @@ PPA0_CFG:	; DEVICE 0
 	.DW	0,0			; DEVICE CAPACITY
 	.DW	0,0			; CURRENT LBA
 ;
-	.ECHO	"PPA: MODE="
+	DEVECHO	"PPA: MODE="
  #IF (PPAMODE == PPAMODE_SPP)
-	.ECHO	"SPP"
+	DEVECHO	"SPP"
  #ENDIF
  #IF (PPAMODE == PPAMODE_MG014)
-	.ECHO	"MG014"
+	DEVECHO	"MG014"
  #ENDIF
-	.ECHO	", IO="
-	.ECHO	PPA0BASE
-	.ECHO	"\n"
+	DEVECHO	", IO="
+	DEVECHO	PPA0BASE
+	DEVECHO	"\n"
 #ENDIF
 ;
 #IF (PPACNT >= 2)
@ -1408,16 +1408,16 @@ PPA1_CFG:	; DEVICE 1
 	.DW	0,0			; DEVICE CAPACITY
 	.DW	0,0			; CURRENT LBA
 ;
-	.ECHO	"PPA: MODE="
+	DEVECHO	"PPA: MODE="
  #IF (PPAMODE == PPAMODE_SPP)
-	.ECHO	"SPP"
+	DEVECHO	"SPP"
  #ENDIF
  #IF (PPAMODE == PPAMODE_MG014)
-	.ECHO	"MG014"
+	DEVECHO	"MG014"
  #ENDIF
-	.ECHO	", IO="
-	.ECHO	PPA1BASE
-	.ECHO	"\n"
+	DEVECHO	", IO="
+	DEVECHO	PPA1BASE
+	DEVECHO	"\n"
 #ENDIF
 ;
 #IF ($ - PPA_CFG) != (PPACNT * PPA_CFGSIZ)
--- a/Source/HBIOS/ppide.asm
+++ b/Source/HBIOS/ppide.asm
@ -230,10 +230,10 @@ PPIDE_DEV0M:	; DEVICE 0, MASTER
 	.DB	PPIDE0BASE+3		; PPI
 	.DW	PPIDE_DEV0S		; PARTNER
 ;
-	.ECHO	"PPIDE: IO="
-	.ECHO	PPIDE0BASE
-	.ECHO	", MASTER"
-	.ECHO	"\n"
+	DEVECHO	"PPIDE: IO="
+	DEVECHO	PPIDE0BASE
+	DEVECHO	", MASTER"
+	DEVECHO	"\n"
 ;
 PPIDE_DEV0S:	; DEVICE 0, SLAVE
 	.DB	$FE			; DRIVER DEVICE NUMBER (FILLED DYNAMICALLY)
@ -248,10 +248,10 @@ PPIDE_DEV0S:	; DEVICE 0, SLAVE
 	.DB	PPIDE0BASE+3		; PPI
 	.DW	PPIDE_DEV0M		; PARTNER
 ;
-	.ECHO	"PPIDE: IO="
-	.ECHO	PPIDE0BASE
-	.ECHO	", SLAVE"
-	.ECHO	"\n"
+	DEVECHO	"PPIDE: IO="
+	DEVECHO	PPIDE0BASE
+	DEVECHO	", SLAVE"
+	DEVECHO	"\n"
 ;
 #ENDIF
 ;
@ -270,10 +270,10 @@ PPIDE_DEV1M:	; DEVICE 1, MASTER
 	.DB	PPIDE1BASE+3		; PPI
 	.DW	PPIDE_DEV1S		; PARTNER
 ;
-	.ECHO	"PPIDE: IO="
-	.ECHO	PPIDE1BASE
-	.ECHO	", MASTER"
-	.ECHO	"\n"
+	DEVECHO	"PPIDE: IO="
+	DEVECHO	PPIDE1BASE
+	DEVECHO	", MASTER"
+	DEVECHO	"\n"
 ;
 PPIDE_DEV1S:	; DEVICE 1, SLAVE
 	.DB	$FE			; DRIVER DEVICE NUMBER (FILLED DYNAMICALLY)
@ -288,10 +288,10 @@ PPIDE_DEV1S:	; DEVICE 1, SLAVE
 	.DB	PPIDE1BASE+3		; PPI
 	.DW	PPIDE_DEV1M		; PARTNER
 ;
-	.ECHO	"PPIDE: IO="
-	.ECHO	PPIDE1BASE
-	.ECHO	", SLAVE"
-	.ECHO	"\n"
+	DEVECHO	"PPIDE: IO="
+	DEVECHO	PPIDE1BASE
+	DEVECHO	", SLAVE"
+	DEVECHO	"\n"
 ;
 #ENDIF
 ;
@ -310,10 +310,10 @@ PPIDE_DEV2M:	; DEVICE 2, MASTER
 	.DB	PPIDE2BASE+3		; PPI
 	.DW	PPIDE_DEV2S		; PARTNER
 ;
-	.ECHO	"PPIDE: IO="
-	.ECHO	PPIDE2BASE
-	.ECHO	", MASTER"
-	.ECHO	"\n"
+	DEVECHO	"PPIDE: IO="
+	DEVECHO	PPIDE2BASE
+	DEVECHO	", MASTER"
+	DEVECHO	"\n"
 ;
 PPIDE_DEV2S:	; DEVICE 2, SLAVE
 	.DB	$FE			; DRIVER DEVICE NUMBER (FILLED DYNAMICALLY)
@ -328,10 +328,10 @@ PPIDE_DEV2S:	; DEVICE 2, SLAVE
 	.DB	PPIDE2BASE+3		; PPI
 	.DW	PPIDE_DEV2M		; PARTNER
 ;
-	.ECHO	"PPIDE: IO="
-	.ECHO	PPIDE2BASE
-	.ECHO	", SLAVE"
-	.ECHO	"\n"
+	DEVECHO	"PPIDE: IO="
+	DEVECHO	PPIDE2BASE
+	DEVECHO	", SLAVE"
+	DEVECHO	"\n"
 ;
 #ENDIF
 ;
--- a/Source/HBIOS/ppk.asm
+++ b/Source/HBIOS/ppk.asm
@ -60,7 +60,7 @@ PPK_REPEAT	.DB	0	; CURRENT REPEAT RATE
 PPK_IDLE	.DB	0	; IDLE COUNT
 PPK_WAITTO	.DW	0	; TIMEOUT WAIT LOOP COUNT (COMPUTED IN INIT)
 ;
-	.ECHO	"PPK: ENABLED\n"
+	DEVECHO	"PPK: ENABLED\n"
 ;
 ;__________________________________________________________________________________________________
 ; KEYBOARD INITIALIZATION
--- a/Source/HBIOS/ppp.asm
+++ b/Source/HBIOS/ppp.asm
@ -9,9 +9,9 @@ PPP_IO		.EQU	PPPBASE + 0	; PPP DATA I/O (PPI PORT A)
 PPP_CTL		.EQU	PPPBASE + 2	; PPP CTL LINES (PPI PORT C)
 PPP_PPICTL	.EQU	PPPBASE + 3	; PPI CONTROL PORT
 ;
-		.ECHO	"PPP: IO="
-		.ECHO	PPP_IO
-		.ECHO	"\n"
+		DEVECHO	"PPP: IO="
+		DEVECHO	PPP_IO
+		DEVECHO	"\n"
 ;
 ; COMMAND BYTES
 ;
@ -253,7 +253,7 @@ PPP_FWVER		.DB	$00, $00, $00, $00	; MMNNBBB (M=MAJOR, N=MINOR, B=BUILD)
 PPPCON_ROWS	.EQU	29		; PROPELLER VGA DISPLAY ROWS (30 - 1 STATUS LINES)
 PPPCON_COLS	.EQU	80		; PROPELLER VGA DISPLAY COLS
 ;
-		.ECHO	"PPPCON: ENABLED\n"
+		DEVECHO	"PPPCON: ENABLED\n"
 ;
 PPPCON_INIT:
 	CALL	NEWLINE
@ -420,7 +420,7 @@ PPPSD_CFGTBL:
 ;
 	.DB	$FF			; END MARKER
 ;
-		.ECHO	"PPPSD: ENABLED\n"
+		DEVECHO	"PPPSD: ENABLED\n"
 ;
 ; SD CARD INITIALIZATION
 ;
--- a/Source/HBIOS/prp.asm
+++ b/Source/HBIOS/prp.asm
@ -7,9 +7,9 @@
 ;
 PRP_IOBASE	.EQU	$A8
 ;
-		.ECHO	"PRP: IO="
-		.ECHO	PRP_IOBASE
-		.ECHO	"\n"
+		DEVECHO	"PRP: IO="
+		DEVECHO	PRP_IOBASE
+		DEVECHO	"\n"
 ;
 ; GLOBAL PROPIO INITIALIZATION
 ;
@ -124,7 +124,7 @@ PRPCON_DSPRDY	.EQU	$10		; BIT SET WHEN DISPLAY BUF IS READY FOR A BYTE (BUF EMPT
 PRPCON_ROWS	.EQU	29		; PROPELLER VGA DISPLAY ROWS (30 - 1 STATUS LINES)
 PRPCON_COLS	.EQU	80		; PROPELLER VGA DISPLAY COLS
 ;
-		.ECHO	"PRPCON: ENABLED\n"
+		DEVECHO	"PRPCON: ENABLED\n"
 ;
 ;
 ;
@ -317,7 +317,7 @@ PRPSD_CFGTBL:
 ;
 	.DB	$FF			; END MARKER
 ;
-	.ECHO	"PRPSD: ENABLED\n"
+	DEVECHO	"PRPSD: ENABLED\n"
 ;
 ; SD CARD INITIALIZATION
 ;
--- a/Source/HBIOS/rf.asm
+++ b/Source/HBIOS/rf.asm
@ -43,9 +43,9 @@ RF_CFGTBL:
 	.DB	0			; UNUSED
 	.DB	RF_U0IO			; DEVICE BASE ADDR
 ;
-	.ECHO	"RF: IO="
-	.ECHO	RF_U0IO
-	.ECHO	"\n"
+	DEVECHO	"RF: IO="
+	DEVECHO	RF_U0IO
+	DEVECHO	"\n"
 ;
 #IF (RF_DEVCNT > 1)
 	; DEVICE 1
@ -56,9 +56,9 @@ RF_CFGTBL:
 	.DB	RF_U1IO			; DEVICE BASE ADDR
 #ENDIF
 ;
-	.ECHO	"RF: IO="
-	.ECHO	RF_U1IO
-	.ECHO	"\n"
+	DEVECHO	"RF: IO="
+	DEVECHO	RF_U1IO
+	DEVECHO	"\n"
 ;
 #IF (RF_DEVCNT > 2)
 	; DEVICE 2
@ -69,9 +69,9 @@ RF_CFGTBL:
 	.DB	RF_U2IO			; DEVICE BASE ADDR
 #ENDIF
 ;
-	.ECHO	"RF: IO="
-	.ECHO	RF_U2IO
-	.ECHO	"\n"
+	DEVECHO	"RF: IO="
+	DEVECHO	RF_U2IO
+	DEVECHO	"\n"
 ;
 #IF (RF_DEVCNT > 3)
 	; DEVICE 3
@ -81,9 +81,9 @@ RF_CFGTBL:
 	.DB	0			; UNUSED
 	.DB	RF_U3IO			; DEVICE BASE ADDR
 ;
-	.ECHO	"RF: IO="
-	.ECHO	RF_U3IO
-	.ECHO	"\n"
+	DEVECHO	"RF: IO="
+	DEVECHO	RF_U3IO
+	DEVECHO	"\n"
 ;
 #ENDIF
 ;
--- a/Source/HBIOS/romldr.asm
+++ b/Source/HBIOS/romldr.asm
@ -148,7 +148,7 @@ start:
 	ld	bc,$01FB		; UNA func: set bank
 	ld	de,BID_USR		; select user bank
 	rst	08			; do it
-	ld	(bid_ldr),de		; ... for later
+	ld	(bid_ldr),de		; save previous bank for later
 	bit	7,d			; starting from ROM?
 #endif
 ;
@ -156,6 +156,8 @@ start:
 	ld	hl,ra_tbl		; assume ROM startup
 	jr	z,start1		; if so, ra_tbl OK, skip ahead
 	ld	hl,ra_tbl_app		; not ROM boot, get app tbl loc
+	ld	a,$ff			; signal for app boot
+	ld	(appboot),a		; ... goes in flag
 start1:
 	ld	(ra_tbl_loc),hl		; and overlay pointer
 ;
@ -206,6 +208,10 @@ start1:
 	call	nl2			; formatting
 	ld	hl,str_banner		; display boot banner
 	call	pstr			; do it
+	ld	a,(appboot)		; get app boot flag
+	or	a			; set flags
+	ld	hl,str_appboot		; signal application boot mode
+	call	nz,pstr			; print if app boot active
 	call	clrbuf			; zero fill the cmd buffer
 ;
 #if ((BIOS == BIOS_WBW) & FPSW_ENABLE)
@ -398,7 +404,6 @@ conpoll4:
 ;=======================================================================
 ;
 concmd:
-	call	clrled			; clear LEDs
 ;
 #if (DSKYENABLE)
 	call	dsky_highlightkeysoff
@ -617,7 +622,6 @@ fp_flopboot2:
 #if (DSKYENABLE)
 ;
 dskycmd:
-	call	clrled			; clear LEDs
 ;
 	call	dsky_getkey		; get DSKY key
 	ld	a,e			; put in A
@ -1474,32 +1478,6 @@ str_s100con	.db	"\r\n\r\nConsole on S100 Bus",0
 ; Utility functions
 ;=======================================================================
 ;
-; Clear LEDs
-;
-clrled:
-#if (BIOS == BIOS_WBW)
-  #if (FPLED_ENABLE)
-	ld	b,BF_SYSSET		; HBIOS SysGet
-	ld	c,BF_SYSSET_PANEL	; ... Panel swiches value
-	ld	l,$00			; all LEDs off
-	rst	08			; do it
-  #endif
-  #if (LEDENABLE)
-    #if (LEDMODE == LEDMODE_STD)
-	ld	a,$FF			; led is inverted
-	out	(LEDPORT),a		; clear led
-    #endif
-    #if (LEDMODE == LEDMODE_RTC)
-	; Bits 0 and 1 of the RTC latch are for the LEDs.
-	ld	a,(HB_RTCVAL)
-	and	~%00000011
-	out	(RTCIO),a		; clear led
-	ld	(HB_RTCVAL),a
-    #endif
-  #endif
-#endif
-	ret
-;
 ; Print string at HL on console, null terminated
 ;
 pstr:
@ -2315,6 +2293,7 @@ acmd_to		.dw	BOOT_TIMEOUT	; auto cmd timeout
 ;=======================================================================
 ;
 str_banner	.db	PLATFORM_NAME," Boot Loader",0
+str_appboot	.db	" (App Boot)",0
 str_autoboot	.db	"AutoBoot: ",0
 str_prompt	.db	"Boot [H=Help]: ",0
 str_bs		.db	bs,' ',bs,0
@ -2430,7 +2409,7 @@ ra_ent		.equ	12
 ; be pre-loaded into the currently executing ram bank thereby allowing
 ; those images to be dynamically loaded as well.  To support this
 ; concept, a pseudo-bank called bid_cur is used to specify the images
-; normally found in BID_IMG0.  In romload, this special value will cause
+; normally found in BID_IMG0.  This special value will cause
 ; the associated image to be loaded from the currently executing bank
 ; which will be correct regardless of the load mode.  Images in other
 ; banks (BID_IMG1) will always be loaded directly from ROM.
@ -2509,6 +2488,7 @@ dma		.dw	0		; address for load
 sps		.dw	0		; sectors per slice
 mediaid		.db	0		; media id
 ;
+appboot		.db	0		; app boot if != 0
 ra_tbl_loc	.dw	0		; points to active ra_tbl
 bootunit	.db	0		; boot disk unit
 bootslice	.db	0		; boot disk slice
--- a/Source/HBIOS/rp5rtc.asm
+++ b/Source/HBIOS/rp5rtc.asm
@ -55,9 +55,9 @@ MODE_RAM1	.EQU	3
 MD_TIME		.EQU	8
 MD_ALRM		.EQU	4

-		.ECHO	"RP5C01: IO="
-		.ECHO	RP5RTC_REG
-		.ECHO	"\n"
+		DEVECHO	"RP5C01: IO="
+		DEVECHO	RP5RTC_REG
+		DEVECHO	"\n"

 RP5RTC_INIT:
 	LD	A, (RTC_DISPACT)	; RTC DISPATCHER ALREADY SET?
--- a/Source/HBIOS/scon.asm
+++ b/Source/HBIOS/scon.asm
@ -16,9 +16,9 @@ SCON_DSPRDY	.EQU	%00000100
 SCON_COLS	.EQU	80
 SCON_ROWS	.EQU	40
 ;
-		.ECHO	"SCON: IO="
-		.ECHO	SCON_IOBASE
-		.ECHO	"\n"
+		DEVECHO	"SCON: IO="
+		DEVECHO	SCON_IOBASE
+		DEVECHO	"\n"
 ;
 ;
 ;
--- a/Source/HBIOS/sd.asm
+++ b/Source/HBIOS/sd.asm
@ -117,7 +117,7 @@ SD_NOPULLUP	.EQU	TRUE		; ASSUME NO PULLUP
 ;
 SD_DEVCNT	.EQU	SDCNT		; SET SD_DEVCNT TO SDCNT CONFIG VAR
 ;
-		.ECHO	"SD: MODE="
+		DEVECHO	"SD: MODE="
 ;
 #IF (SDMODE == SDMODE_JUHA)		; JUHA MINI-BOARD
 SD_DEVMAX	.EQU	1		; NUMBER OF PHYSICAL UNITS (SOCKETS)
@ -131,7 +131,7 @@ SD_DI		.EQU	%00000001	; RTC:0 IS DATA IN (CARD <- CPU)
 SD_DO		.EQU	%10000000	; RTC:7 IS DATA OUT (CARD -> CPU)
 SD_IOBASE	.EQU	SD_OPRREG	; IOBASE
 SD_INVCS	.EQU	FALSE		; INVERT CS
-		.ECHO	"JUHA"
+		DEVECHO	"JUHA"
 ;
 RTCDEF		.SET	RTCDEF | SD_OPRDEF	; SET DEFAULT IN HBIOS MAINLINE
 #ENDIF
@ -148,7 +148,7 @@ SD_DI		.EQU	%00000001	; RTC:0 IS DATA IN (CARD <- CPU)
 SD_DO		.EQU	%01000000	; RTC:6 IS DATA OUT (CARD -> CPU)
 SD_IOBASE	.EQU	SD_OPRREG	; IOBASE
 SD_INVCS	.EQU	FALSE		; INVERT CS
-		.ECHO	"N8"
+		DEVECHO	"N8"
 ;
 RTCDEF		.SET	RTCDEF | SD_OPRDEF	; SET DEFAULT IN HBIOS MAINLINE
 #ENDIF
@ -163,7 +163,7 @@ SD_CNTR		.EQU	Z180_CNTR
 SD_TRDR		.EQU	Z180_TRDR
 SD_IOBASE	.EQU	SD_OPRREG	; IOBASE
 SD_INVCS	.EQU	FALSE		; INVERT CS
-		.ECHO	"CSIO"
+		DEVECHO	"CSIO"
 ;
 RTCDEF		.SET	RTCDEF | SD_OPRDEF	; SET DEFAULT IN HBIOS MAINLINE
 #ENDIF
@ -184,7 +184,7 @@ SD_DI		.EQU	%00000001	; PPIC:0 IS DATA IN (CARD <- CPU)
 SD_DO		.EQU	%10000000	; PPIB:7 IS DATA OUT (CARD -> CPU)
 SD_IOBASE	.EQU	SD_PPIBASE	; IOBASE
 SD_INVCS	.EQU	TRUE		; INVERT CS
-		.ECHO	"PPI"
+		DEVECHO	"PPI"
 #ENDIF
 ;
 #IF (SDMODE == SDMODE_UART)
@ -199,7 +199,7 @@ SD_DI		.EQU	%00000001	; UART MCR:0 IS DATA IN (CARD <- CPU)
 SD_DO		.EQU	%00100000	; UART MSR:5 IS DATA OUT (CARD -> CPU)
 SD_IOBASE	.EQU	UARTIOB		; IOBASE
 SD_INVCS	.EQU	TRUE		; INVERT CS
-		.ECHO	"UART"
+		DEVECHO	"UART"
 #ENDIF
 ;
 #IF (SDMODE == SDMODE_DSD)		; DUAL SD
@ -215,7 +215,7 @@ SD_DI		.EQU	%00000001	; RTC:6 IS DATA IN (CARD <- CPU)
 SD_DO		.EQU	%00000001	; RTC:0 IS DATA OUT (CARD -> CPU)
 SD_IOBASE	.EQU	SD_OPRREG	; IOBASE
 SD_INVCS	.EQU	FALSE		; INVERT CS
-		.ECHO	"DSD"
+		DEVECHO	"DSD"
 #ENDIF
 ;
 #IF (SDMODE == SDMODE_MK4)		; MARK IV (CSIO STYLE INTERFACE)
@ -227,7 +227,7 @@ SD_CNTR		.EQU	Z180_CNTR
 SD_TRDR		.EQU	Z180_TRDR
 SD_IOBASE	.EQU	SD_OPRREG	; IOBASE
 SD_INVCS	.EQU	FALSE		; INVERT CS
-		.ECHO	"MK4"
+		DEVECHO	"MK4"
 #ENDIF
 ;
 #IF (SDMODE == SDMODE_SC)		; SC
@ -241,16 +241,10 @@ SD_CNTR		.EQU	Z180_CNTR
 SD_TRDR		.EQU	Z180_TRDR
 SD_IOBASE	.EQU	SD_OPRREG	; IOBASE
 SD_INVCS	.EQU	TRUE		; INVERT CS
-		.ECHO	"SC"
+		DEVECHO	"SC"
 ;
 RTCDEF		.SET	RTCDEF | SD_OPRDEF	; SET DEFAULT IN HBIOS MAINLINE
 #ENDIF
-;
-		.ECHO	", IO="
-		.ECHO	SD_IOBASE
-		.ECHO	", UNITS="
-		.ECHO	SDCNT
-		.ECHO	"\n"
 ;
 #IF (SDMODE == SDMODE_MT)		; MT shift register for RCBUS (ref SDMODE_CSIO)
 ;
@ -300,6 +294,7 @@ SD_CS1		.EQU	%00010000	; IN/OUT:SD_OPREG:4 = CS1, SDCARD1 CS, IN=1 Card present
  #ENDIF
 SD_IOBASE	.EQU	SD_BASE		; IOBASE
 SD_INVCS	.EQU	FALSE		; INVERT CS
+		DEVECHO	"DUO"
 #ENDIF
 ;
 ;
@ -332,6 +327,7 @@ SD_CINIT	.EQU	TRUE		; INITIALIZE OUTPUT PORT
 SD_DDR		.EQU	$6B		; DATA DIRECTION REGISTER
 SD_DDRVAL	.EQU	%11100110	; DATA DIRECTION REGISTER VALUE
 SD_INVCS	.EQU	TRUE		; INVERT CS
+		DEVECHO	"PIO"
 #ENDIF
 ;
 ;
@ -355,6 +351,7 @@ SD_CINIT	.EQU	TRUE		; INITIALIZE OUTPUT PORT
 SD_DDR		.EQU	$03		; DATA DIRECTION REGISTER
 SD_DDRVAL	.EQU	%00001101	; DATA DIRECTION REGISTER VALUE
 SD_INVCS	.EQU	FALSE		; INVERT CS
+		DEVECHO	"USR"
 #ENDIF
 ;
 #IF (SDMODE == SDMODE_Z80R)		; Z80 Retro
@ -376,6 +373,7 @@ SD_DI		.EQU	%00000001	; DATA IN (CARD <- CPU) MOSI
 SD_DO		.EQU	%00000001	; DATA OUT (CARD -> CPU) MISO
 SD_CINIT	.EQU	FALSE		; INITIALIZE OUTPUT PORT
 SD_INVCS	.EQU	FALSE		; INVERT CS
+		DEVECHO	"Z80R"
 #ENDIF

 ; FOR NOW WE JUST HOOK UP ONE UNIT. THERE ARE EIGHT PORTS FOR DIFFERENT
@ -389,7 +387,14 @@ SD_CNTR		.EQU	Z180_CNTR
 SD_TRDR		.EQU	Z180_TRDR
 SD_IOBASE	.EQU	SD_OPRREG	; IOBASE
 SD_INVCS	.EQU	FALSE		; INVERT CS
+		DEVECHO	"EPITX"
 #ENDIF
+;
+		DEVECHO	", IO="
+		DEVECHO	SD_IOBASE
+		DEVECHO	", UNITS="
+		DEVECHO	SDCNT
+		DEVECHO	"\n"
 ;
 #IF (SD_DEVCNT > SD_DEVMAX)
 	.ECHO	"*** ERROR: SDCNT EXCEEDS MAXIMUM SUPPORTED BY INTERFACE!!!\n"
--- a/Source/HBIOS/simrtc.asm
+++ b/Source/HBIOS/simrtc.asm
@ -8,9 +8,9 @@ SIMRTC_CLKREAD	.EQU	7	; READ CLOCK COMMAND
 SIMRTC_CLKWRITE	.EQU	8	; WRITE CLOCK COMMAND
 SIMRTC_BUFSIZ	.EQU	6	; SIX BYTE BUFFER (YYMMDDHHMMSS)
 ;
-	.ECHO	"SIMRTC: IO="
-	.ECHO	SIMRTC_IO
-	.ECHO	"\n"
+	DEVECHO	"SIMRTC: IO="
+	DEVECHO	SIMRTC_IO
+	DEVECHO	"\n"
 ;
 ; RTC DEVICE INITIALIZATION ENTRY
 ;
--- a/Source/HBIOS/sio.asm
+++ b/Source/HBIOS/sio.asm
@ -1171,30 +1171,30 @@ SIO0A_CFG:
 	.DB	SIO0ACTCC		; CTC CHANNEL
 	.DB	SIO0MODE		; MODE
 ;
-	.ECHO	"SIO MODE="
+	DEVECHO	"SIO MODE="
 #IF (SIO0MODE == SIOMODE_STD)
-	.ECHO	"STD"
+	DEVECHO	"STD"
 #ENDIF
 #IF (SIO0MODE == SIOMODE_RC)
-	.ECHO	"RC"
+	DEVECHO	"RC"
 #ENDIF	

 #IF (SIO0MODE == SIOMODE_SMB)
-	.ECHO	"SMB"
+	DEVECHO	"SMB"
 #ENDIF
 #IF (SIO0MODE == SIOMODE_ZP)
-	.ECHO	"ZP"
+	DEVECHO	"ZP"
 #ENDIF
 #IF (SIO0MODE == SIOMODE_Z80R)
-	.ECHO	"Z80R"
+	DEVECHO	"Z80R"
 #ENDIF
-	.ECHO	", IO="
-	.ECHO	SIO0BASE
-	.ECHO	", CHANNEL A"
+	DEVECHO	", IO="
+	DEVECHO	SIO0BASE
+	DEVECHO	", CHANNEL A"
  #IF (INTMODE > 0)
-		.ECHO	", INTERRUPTS ENABLED"
+		DEVECHO	", INTERRUPTS ENABLED"
  #ENDIF
-		.ECHO	"\n"
+		DEVECHO	"\n"
 ;
 SIO_CFGSIZ	.EQU	$ - SIO_CFG	; SIZE OF ONE CFG TABLE ENTRY
 ;
@ -1212,29 +1212,29 @@ SIO0B_CFG:
 	.DB	SIO0BCTCC		; CTC CHANNEL
 	.DB	SIO0MODE		; MODE
 ;
-	.ECHO	"SIO MODE="
+	DEVECHO	"SIO MODE="
 #IF (SIO0MODE == SIOMODE_STD)
-	.ECHO	"STD"
+	DEVECHO	"STD"
 #ENDIF
 #IF (SIO0MODE == SIOMODE_RC)
-	.ECHO	"RC"
+	DEVECHO	"RC"
 #ENDIF	
 #IF (SIO0MODE == SIOMODE_SMB)
-	.ECHO	"SMB"
+	DEVECHO	"SMB"
 #ENDIF
 #IF (SIO0MODE == SIOMODE_ZP)
-	.ECHO	"ZP"
+	DEVECHO	"ZP"
 #ENDIF
 #IF (SIO0MODE == SIOMODE_Z80R)
-	.ECHO	"Z80R"
+	DEVECHO	"Z80R"
 #ENDIF
-	.ECHO	", IO="
-	.ECHO	SIO0BASE
-	.ECHO	", CHANNEL B"
+	DEVECHO	", IO="
+	DEVECHO	SIO0BASE
+	DEVECHO	", CHANNEL B"
  #IF (INTMODE > 0)
-		.ECHO	", INTERRUPTS ENABLED"
+		DEVECHO	", INTERRUPTS ENABLED"
  #ENDIF
-		.ECHO	"\n"
+		DEVECHO	"\n"
 ;
 #IF (SIOCNT >= 2)
 ;
@ -1252,30 +1252,30 @@ SIO1A_CFG:
 	.DB	SIO1ACTCC		; CTC CHANNEL
 	.DB	SIO1MODE		; MODE
 ;
-	.ECHO	"SIO MODE="
+	DEVECHO	"SIO MODE="
 #IF (SIO1MODE == SIOMODE_STD)
-	.ECHO	"STD"
+	DEVECHO	"STD"
 #ENDIF
 #IF (SIO1MODE == SIOMODE_RC)
-	.ECHO	"RC"
+	DEVECHO	"RC"
 #ENDIF	

 #IF (SIO1MODE == SIOMODE_SMB)
-	.ECHO	"SMB"
+	DEVECHO	"SMB"
 #ENDIF
 #IF (SIO1MODE == SIOMODE_ZP)
-	.ECHO	"ZP"
+	DEVECHO	"ZP"
 #ENDIF
 #IF (SIO1MODE == SIOMODE_Z80R)
-	.ECHO	"Z80R"
+	DEVECHO	"Z80R"
 #ENDIF
-	.ECHO	", IO="
-	.ECHO	SIO1BASE
-	.ECHO	", CHANNEL A"
+	DEVECHO	", IO="
+	DEVECHO	SIO1BASE
+	DEVECHO	", CHANNEL A"
  #IF (INTMODE > 0)
-		.ECHO	", INTERRUPTS ENABLED"
+		DEVECHO	", INTERRUPTS ENABLED"
  #ENDIF
-		.ECHO	"\n"
+		DEVECHO	"\n"
 ;
 	; SIO1 CHANNEL B
 SIO1B_CFG:
@ -1291,29 +1291,29 @@ SIO1B_CFG:
 	.DB	SIO1BCTCC		; CTC CHANNEL
 	.DB	SIO1MODE		; MODE
 ;
-	.ECHO	"SIO MODE="
+	DEVECHO	"SIO MODE="
 #IF (SIO1MODE == SIOMODE_STD)
-	.ECHO	"STD"
+	DEVECHO	"STD"
 #ENDIF
 #IF (SIO1MODE == SIOMODE_RC)
-	.ECHO	"RC"
+	DEVECHO	"RC"
 #ENDIF	
 #IF (SIO1MODE == SIOMODE_SMB)
-	.ECHO	"SMB"
+	DEVECHO	"SMB"
 #ENDIF
 #IF (SIO1MODE == SIOMODE_ZP)
-	.ECHO	"ZP"
+	DEVECHO	"ZP"
 #ENDIF
 #IF (SIO1MODE == SIOMODE_Z80R)
-	.ECHO	"Z80R"
+	DEVECHO	"Z80R"
 #ENDIF
-	.ECHO	", IO="
-	.ECHO	SIO1BASE
-	.ECHO	", CHANNEL B"
+	DEVECHO	", IO="
+	DEVECHO	SIO1BASE
+	DEVECHO	", CHANNEL B"
  #IF (INTMODE > 0)
-		.ECHO	", INTERRUPTS ENABLED"
+		DEVECHO	", INTERRUPTS ENABLED"
  #ENDIF
-		.ECHO	"\n"
+		DEVECHO	"\n"
 ;
 #ENDIF
 ;
--- a/Source/HBIOS/sn76489.asm
+++ b/Source/HBIOS/sn76489.asm
@ -17,33 +17,33 @@
 ;======================================================================
 ;

-	.ECHO	"SN76489 MODE="
+	DEVECHO	"SN76489 MODE="
 ;
 #IF (SNMODE == SNMODE_VGM)
 SN76489_PORT_LEFT	.EQU	$C6	; PORTS FOR ACCESSING THE SN76489 CHIP (LEFT)
 SN76489_PORT_RIGHT	.EQU	$C7	; PORTS FOR ACCESSING THE SN76489 CHIP (RIGHT)
-	.ECHO	"VGM"
+	DEVECHO	"VGM"
 #ENDIF
 ;
 #IF (SNMODE == SNMODE_RC)
 SN76489_PORT_LEFT	.EQU	$FF	; PORTS FOR ACCESSING THE SN76489 CHIP (LEFT)
 SN76489_PORT_RIGHT	.EQU	$FB	; PORTS FOR ACCESSING THE SN76489 CHIP (RIGHT)
-	.ECHO	"RC"
+	DEVECHO	"RC"
 #ENDIF
 ;
 #IF (SNMODE == SNMODE_DUO)
 SN76489_PORT_LEFT	.EQU	$BE	; PORTS FOR ACCESSING THE SN76489 CHIP (LEFT)
 SN76489_PORT_RIGHT	.EQU	$BF	; PORTS FOR ACCESSING THE SN76489 CHIP (RIGHT)
-	.ECHO	"RC"
+	DEVECHO	"RC"
 #ENDIF
 ;
-	.ECHO	", IO_LEFT="
-	.ECHO	SN76489_PORT_LEFT
-	.ECHO	", IO_RIGHT="
-	.ECHO	SN76489_PORT_RIGHT
-	.ECHO	", CLOCK="
-	.ECHO	SN7CLK
-	.ECHO	" HZ\n"
+	DEVECHO	", IO_LEFT="
+	DEVECHO	SN76489_PORT_LEFT
+	DEVECHO	", IO_RIGHT="
+	DEVECHO	SN76489_PORT_RIGHT
+	DEVECHO	", CLOCK="
+	DEVECHO	SN7CLK
+	DEVECHO	" HZ\n"
 ;
 SN7_IDAT		.EQU	0
 SN7_TONECNT		.EQU	3	; COUNT NUMBER OF TONE CHANNELS
--- a/Source/HBIOS/spk.asm
+++ b/Source/HBIOS/spk.asm
@ -41,9 +41,9 @@ SP_PENDING_PERIOD	.DW	SP_NOTE_C8	; PENDING PERIOD (16 BITS)
 SP_PENDING_VOLUME	.DB	$FF		; PENDING VOL (8 BITS)
 SP_PENDING_DURATION	.DW	0		; PENDING DURATION (16 BITS)
 ;
-	.ECHO	"SPK: IO="
-	.ECHO	RTCIO
-	.ECHO	"\n"
+	DEVECHO	"SPK: IO="
+	DEVECHO	RTCIO
+	DEVECHO	"\n"
 ;
 ;======================================================================
 ;	DRIVER INITIALIZATION
--- a/Source/HBIOS/std.asm
+++ b/Source/HBIOS/std.asm
@ -22,16 +22,24 @@
 ; 18. HEATH	Les Bird's Heath Z80 Board
 ; 19. EPITX	Alan Cox' Mini-ITX System
 ; 20. MON	Jacques Pelletier's Monsputer
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; 21. STDZ180	Genesis Z180 System
+; 22. NABU	NABU w/ Les Bird's RomWBW Option Board
 ;
-; INCLUDE VERSION
+; INCLUDE BUILD VERSION
 ;
 #INCLUDE "../ver.inc"			; ADD BIOSVER
 ;
 FALSE		.EQU	0
 TRUE		.EQU	~FALSE
 ;
+; CONTROLS PRINTING OF SYSTEM INFORMATION IN ASSEMBLY OUTPUT
+;
+#IFDEF SYSINFO
+  #DEFINE SYSECHO .ECHO
+#ELSE
+  #DEFINE SYSECHO \;
+#ENDIF
+;
 ; DEBUGGING OPTIONS
 ;
 USENONE		.EQU	0		; NO DEBUG
@ -145,7 +153,9 @@ CONBELL_IOBIT	.EQU	2
 ;
 LEDMODE_NONE	.EQU	0
 LEDMODE_STD	.EQU	1
-LEDMODE_RTC	.EQU	2
+LEDMODE_SC	.EQU	2
+LEDMODE_RTC	.EQU	3
+LEDMODE_NABU	.EQU	4
 ;
 ; DSKY MODE SELECTIONS
 ;
@ -216,6 +226,7 @@ AYMODE_MSX	.EQU	5		; RCBUS SOUND MODULE REV6 BY ED BRINDLEY ON Z80/Z180 AT MSX P
 AYMODE_LINC	.EQU	6		; LINC Z50 AY SOUND CARD
 AYMODE_MBC	.EQU	7		; MBC SOUND BOARD
 AYMODE_DUO	.EQU	8		; MBC SOUND BOARD
+AYMODE_NABU	.EQU	9		; NABU BUILT-IN SOUND
 ;
 ; SN SOUND CHIP MODE SELECTIONS
 ;
@ -234,7 +245,9 @@ TMSMODE_MSX9958	.EQU	4		; MSX PORTS, V9958 CHIP
 TMSMODE_MSXKBD	.EQU	5		; MSX PORTS + PS2 KEYBOARD
 TMSMODE_MBC	.EQU	6		; MBC V9938/58 VIDEO BOARD
 TMSMODE_COLECO	.EQU	7		; COLECOVISION PORT MAPPING
-TMSMODE_DUO	.EQU	8		; COLECOVISION PORT MAPPING
+TMSMODE_DUO	.EQU	8		; DUODYNE PORT MAPPING
+TMSMODE_NABU40	.EQU	9		; NABU V9918 + NABU KBD
+TMSMODE_NABU80	.EQU	10		; NABU V9958 + NABU KBD
 ;
 ; CVDU VIDEO MODE SELECTIONS
 ;
@ -469,6 +482,7 @@ TERMENABLE	.EQU	FALSE		; TERM PSEUDO DEVICE, WILL AUTO-ENABLE IF A VDA IS ENABLE
 ;
 KBDENABLE	.EQU	FALSE		; PS/2 KEYBOARD DRIVER
 PPKENABLE	.EQU	FALSE		; PPK KEYBOARD DRIVER
+NABUKBENABLE	.EQU	FALSE		; NABU KEYBOARD DRIVER
 ;
 ; VIDEO MODES
 ;
@ -557,24 +571,20 @@ CPUKHZ		.SET	CPUKHZ / 2	; Z180 PHI IS ALWAYS 1/2 OSC
 ;
 CPUMHZ		.EQU	CPUKHZ / 1000	; CPU FREQ IN MHZ
 ;
-	.ECHO	"ASSUMED CPU SPEED: "
-	.ECHO	CPUKHZ
-	.ECHO	" KHZ\n"
-;
-	.ECHO	"INTERRUPTS: "
+	SYSECHO	"INTERRUPTS: "
 #IF (INTMODE == 0)
-	.ECHO	"NONE"
+	SYSECHO	"NONE"
 #ENDIF
 #IF (INTMODE == 1)
-	.ECHO	"MODE 1"
+	SYSECHO	"MODE 1"
 #ENDIF
 #IF (INTMODE == 2)
-	.ECHO	"MODE 2"
+	SYSECHO	"MODE 2"
 #ENDIF
 #IF (INTMODE == 3)
-	.ECHO	"MODE 3"
+	SYSECHO	"MODE 3"
 #ENDIF
-	.ECHO	"\n"
+	SYSECHO	"\n"
 ;
 ; SYSTEM PERIODIC TIMER MODE
 ;
@ -587,110 +597,110 @@ TM_SIMH	.EQU	3
 TM_Z180	.EQU	4
 TM_Z280	.EQU	5
 ;
-	.ECHO "SYSTEM TIMER:"
+	SYSECHO "SYSTEM TIMER:"
 SYSTIM	.EQU	TM_NONE
 ;
  #IF (CTCENABLE & (INTMODE == 2))
    #IF (CTCTIMER)
 SYSTIM	.SET	TM_CTC
-	.ECHO	" CTC"
+	SYSECHO	" CTC"
    #ENDIF
  #ENDIF
 ;
  #IF (TMSENABLE & (INTMODE == 1))
    #IF (TMSTIMENABLE)
 SYSTIM	.SET	TM_TMS
-	.ECHO	" TMS9918/V9958"
+	SYSECHO	" TMS9918/V9958"
    #ENDIF
  #ENDIF
 ;
  #IF ((PLATFORM == PLT_SBC) & (INTMODE == 1))
    #IF (HTIMENABLE)
 SYSTIM	.SET	TM_SIMH
-	.ECHO	" SIMH"
+	SYSECHO	" SIMH"
    #ENDIF
  #ENDIF
 ;
  #IF ((CPUFAM == CPU_Z180) & (INTMODE == 2))
    #IF (Z180_TIMER)
 SYSTIM	.SET	TM_Z180
-	.ECHO	" Z180"
+	SYSECHO	" Z180"
    #ENDIF
  #ENDIF
 ;
  #IF ((CPUFAM == CPU_Z280) & (MEMMGR == MM_Z280))
    #IF (Z280_TIMER)
 SYSTIM	.SET	TM_Z280
-	.ECHO	" Z280"
+	SYSECHO	" Z280"
    #ENDIF
  #ENDIF
 ;
  #IF SYSTIM == TM_NONE
-	.ECHO " NONE"
+	SYSECHO " NONE"
  #ENDIF
 ;
-	.ECHO	"\n"
+	SYSECHO	"\n"
 ;
 #ENDIF
 ;
 #IF (BIOS == BIOS_WBW)
-	.ECHO	"DEFAULT SERIAL CONFIGURATION: "
+	SYSECHO	"DEFAULT SERIAL CONFIGURATION: "
  #IF ((DEFSERCFG & %1111100000000) == SER_BAUD9600
-	.ECHO	"9600"
+	SYSECHO	"9600"
  #ENDIF
  #IF ((DEFSERCFG & %1111100000000) == SER_BAUD38400
-	.ECHO	"38400"
+	SYSECHO	"38400"
  #ENDIF
  #IF ((DEFSERCFG & %1111100000000) == SER_BAUD57600
-	.ECHO	"57600"
+	SYSECHO	"57600"
  #ENDIF
  #IF ((DEFSERCFG & %1111100000000) == SER_BAUD115200
-	.ECHO	"115200"
+	SYSECHO	"115200"
  #ENDIF
-	.ECHO	" BAUD\n"
+	SYSECHO	" BAUD\n"
 #ENDIF
 ;
 ;
 ;
 #IF (BIOS == BIOS_WBW)
-	.ECHO	"MEMORY MANAGER: "
+	SYSECHO	"MEMORY MANAGER: "
  #IF (MEMMGR == MM_SBC)
-	.ECHO	"N8VEM (SBC)"
+	SYSECHO	"N8VEM (SBC)"
  #ENDIF
  #IF (MEMMGR == MM_Z2)
-	.ECHO	"ZETA 2 (Z2)"
+	SYSECHO	"ZETA 2 (Z2)"
  #ENDIF
  #IF (MEMMGR == MM_N8)
-	.ECHO	"N8 ONBOARD (N8)"
+	SYSECHO	"N8 ONBOARD (N8)"
  #ENDIF
  #IF (MEMMGR == MM_Z180)
-	.ECHO	"Z180 NATIVE (Z180)"
+	SYSECHO	"Z180 NATIVE (Z180)"
  #ENDIF
  #IF (MEMMGR == MM_Z280)
-	.ECHO	"Z280 NATIVE (Z280)"
+	SYSECHO	"Z280 NATIVE (Z280)"
  #ENDIF
  #IF (MEMMGR == MM_ZRC)
-	.ECHO	"ZRC ONBOARD (ZRC)"
+	SYSECHO	"ZRC ONBOARD (ZRC)"
  #ENDIF
  #IF (MEMMGR == MM_MBC)
-	.ECHO	"NHYODYNE (MBC)"
+	SYSECHO	"NHYODYNE (MBC)"
  #ENDIF
  #IF (MEMMGR == MM_RPH)
-	.ECHO	"RHYOPHYRE ONBOARD (RPH)"
+	SYSECHO	"RHYOPHYRE ONBOARD (RPH)"
  #ENDIF
  #IF (MEMMGR == MM_MON)
-	.ECHO	"MONSPUTER ONBOARD (MON)"
+	SYSECHO	"MONSPUTER ONBOARD (MON)"
  #ENDIF
-	.ECHO   "\n"
+	SYSECHO   "\n"
 #ENDIF
 ;
-	.ECHO	"ROM SIZE: "
-	.ECHO	ROMSIZE
-	.ECHO	" KB\n"
+	SYSECHO	"ROM SIZE: "
+	SYSECHO	ROMSIZE
+	SYSECHO	" KB\n"
 ;
-	.ECHO	"RAM SIZE: "
-	.ECHO	RAMSIZE
-	.ECHO	" KB\n"
+	SYSECHO	"RAM SIZE: "
+	SYSECHO	RAMSIZE
+	SYSECHO	" KB\n"
 ;
 ; MEMORY BANK CONFIGURATION
 ;
@ -825,11 +835,26 @@ BID_ROMD0	.EQU	0		; NO ROM DRIVE
 ;
 #ENDIF
 ;
+#IF ((!MDRAM) | (RAMD_BNKS <= 0))
+BID_RAMD0	.SET	$FF
+MDRAM		.SET	FALSE
+#ENDIF
+;
+#IF ((!MDROM) | (ROMD_BNKS <= 0))
+BID_ROMD0	.SET	$FF
+MDROM		.SET	FALSE
+#ENDIF
+;
 APP_BNKS	.SET	BID_BUF - BID_APP0
 ;
-BID_RAMDN	.EQU	BID_RAMD0 + RAMD_BNKS - 1	; LAST RAM DRIVE BANK
-BID_ROMDN	.EQU	BID_ROMD0 + ROMD_BNKS - 1	; LAST ROM DRIVE BANK
-BID_APPN	.EQU	BID_APP0 + APP_BNKS - 1		; LAST APP BANK
+#IF (APP_BNKS <= 0)
+BID_APP0	.SET	$FF
+APP_BNKS	.SET	0
+#ENDIF
+;
+;;;BID_RAMDN	.EQU	BID_RAMD0 + RAMD_BNKS - 1	; LAST RAM DRIVE BANK
+;;;BID_ROMDN	.EQU	BID_ROMD0 + ROMD_BNKS - 1	; LAST ROM DRIVE BANK
+;;;BID_APPN	.EQU	BID_APP0 + APP_BNKS - 1		; LAST APP BANK
 ;
 #IF TRUE
 	.ECHO "------------- CAPACITY -----------------\n"
@ -849,12 +874,12 @@ BID_APPN	.EQU	BID_APP0 + APP_BNKS - 1		; LAST APP BANK
 	.ECHO "BID_IMG1:  " \ .ECHO BID_IMG1  \ .ECHO "\n"
 	.ECHO "BID_IMG2:  " \ .ECHO BID_IMG2  \ .ECHO "\n"
 	.ECHO "BID_ROMD0: " \ .ECHO BID_ROMD0 \ .ECHO "\n"
-	.ECHO "BID_ROMDN: " \ .ECHO BID_ROMDN \ .ECHO "\n"
+;;;	.ECHO "BID_ROMDN: " \ .ECHO BID_ROMDN \ .ECHO "\n"
 	.ECHO "BID_BIOS:  " \ .ECHO BID_BIOS  \ .ECHO "\n"
 	.ECHO "BID_RAMD0: " \ .ECHO BID_RAMD0 \ .ECHO "\n"
-	.ECHO "BID_RAMDN: " \ .ECHO BID_RAMDN \ .ECHO "\n"
+;;;	.ECHO "BID_RAMDN: " \ .ECHO BID_RAMDN \ .ECHO "\n"
 	.ECHO "BID_APP0:  " \ .ECHO BID_APP0  \ .ECHO "\n"
-	.ECHO "BID_APPN:  " \ .ECHO BID_APPN  \ .ECHO "\n"
+;;;	.ECHO "BID_APPN:  " \ .ECHO BID_APPN  \ .ECHO "\n"
 	.ECHO "BID_BUF:   " \ .ECHO BID_BUF   \ .ECHO "\n"
 	.ECHO "BID_AUX:   " \ .ECHO BID_AUX   \ .ECHO "\n"
 	.ECHO "BID_USR:   " \ .ECHO BID_USR   \ .ECHO "\n"
@ -982,17 +1007,6 @@ INT_SIO1	.EQU	14	; ZILOG SIO 1, CHANNEL A & B

  #IF (PLATFORM == PLT_MBC)
 ;
-; MBC IM2 PINHEADER INTERRUPTS
-;
-;INT_IM2PH0	.EQU	0
-;INT_IM2PH1	.EQU	1
-;INT_IM2PH2	.EQU	2
-;INT_IM2PH3	.EQU	3
-;INT_IM2PH4	.EQU	4
-;INT_IM2PH5	.EQU	5
-;INT_IM2PH6	.EQU	6
-;INT_IM2PH7	.EQU	7
-;
 ; MBC Z80 INTERRUPTS
 ;
 ;INT_CTC0A	.EQU	0	; ZILOG CTC 0, CHANNEL A
@ -1017,17 +1031,6 @@ INT_CTC0D	.EQU	15	; ZILOG CTC 0, CHANNEL D
  #ENDIF

  #IF (PLATFORM == PLT_DUO)
-
-; DUO IM2 PINHEADER INTERRUPTS
-
-;INT_IM2PH0	.EQU	0
-;INT_IM2PH1	.EQU	1
-;INT_IM2PH2	.EQU	2
-;INT_IM2PH3	.EQU	3
-;INT_IM2PH4	.EQU	4
-;INT_IM2PH5	.EQU	5
-;INT_IM2PH6	.EQU	6
-;INT_IM2PH7	.EQU	7
 ;
 ; DUO Z80 IM2 INTERRUPTS
 ;
@ -1046,7 +1049,22 @@ INT_PIO1B	.EQU	12	; ZILOG PIO 1, CHANNEL B

  #ENDIF

-  #IF ((PLATFORM != PLT_MBC) & (PLATFORM != PLT_DUO))
+  #IF (PLATFORM == PLT_NABU)
+;
+; NABU Z80 IM2 INTERRUPTS
+;
+INT_HCAARCV	.EQU	0	; UART 0
+INT_HCAASND	.EQU	1	; UART 1 ?????
+INT_NABUKB	.EQU	2	; ZILOG CTC 0, CHANNEL A
+INT_VDP		.EQU	3	; ZILOG CTC 0, CHANNEL B
+INT_OPTCRD0	.EQU	4	; ZILOG CTC 0, CHANNEL C
+INT_OPTCRD1	.EQU	5	; ZILOG CTC 0, CHANNEL D
+INT_OPTCRD2	.EQU	6	; ZILOG SIO 0, CHANNEL A & B
+INT_OPTCRD3	.EQU	7	; ZILOG SIO 1, CHANNEL A & B
+
+  #ENDIF
+
+  #IF ((PLATFORM != PLT_MBC) & (PLATFORM != PLT_DUO) & (PLATFORM != PLT_NABU))

 ; GENERIC Z80 M2 INTERRUPTS

@ -1082,6 +1100,8 @@ Z180_CNTR_DEF	.EQU	$06	; DEFAULT VALUE FOR Z180 CSIO CONFIG
 ;
 ; HELPER MACROS
 ;
+#DEFINE ALIGN(N) .FILL	((($+(N-1)) & ~(N-1)) - $)
+;
 #DEFINE	PRTC(C)	CALL PRTCH \ .DB C			; PRINT CHARACTER C TO CONSOLE - PRTC('X')
 #DEFINE	PRTS(S)	CALL PRTSTRD \ .TEXT S			; PRINT STRING S TO CONSOLE - PRTD("HELLO")
 #DEFINE	PRTX(X) CALL PRTSTRI \ .DW X			; PRINT STRING AT ADDRESS X TO CONSOLE - PRTI(STR_HELLO)
--- a/Source/HBIOS/syq.asm
+++ b/Source/HBIOS/syq.asm
@ -1447,16 +1447,16 @@ SYQ0_CFG:	; DEVICE 0
 	.DW	0,0			; DEVICE CAPACITY
 	.DW	0,0			; CURRENT LBA
 ;
-	.ECHO	"SYQ: MODE="
+	DEVECHO	"SYQ: MODE="
  #IF (SYQMODE == SYQMODE_SPP)
-	.ECHO	"SPP"
+	DEVECHO	"SPP"
  #ENDIF
  #IF (SYQMODE == SYQMODE_MG014)
-	.ECHO	"MG014"
+	DEVECHO	"MG014"
  #ENDIF
-	.ECHO	", IO="
-	.ECHO	SYQ0BASE
-	.ECHO	"\n"
+	DEVECHO	", IO="
+	DEVECHO	SYQ0BASE
+	DEVECHO	"\n"
 #ENDIF
 ;
 #IF (SYQCNT >= 2)
@ -1469,16 +1469,16 @@ SYQ1_CFG:	; DEVICE 1
 	.DW	0,0			; DEVICE CAPACITY
 	.DW	0,0			; CURRENT LBA
 ;
-	.ECHO	"SYQ: MODE="
+	DEVECHO	"SYQ: MODE="
  #IF (SYQMODE == SYQMODE_SPP)
-	.ECHO	"SPP"
+	DEVECHO	"SPP"
  #ENDIF
  #IF (SYQMODE == SYQMODE_MG014)
-	.ECHO	"MG014"
+	DEVECHO	"MG014"
  #ENDIF
-	.ECHO	", IO="
-	.ECHO	SYQ1BASE
-	.ECHO	"\n"
+	DEVECHO	", IO="
+	DEVECHO	SYQ1BASE
+	DEVECHO	"\n"
 #ENDIF
 ;
 #IF ($ - SYQ_CFG) != (SYQCNT * SYQ_CFGSIZ)
--- a/Source/HBIOS/tms.asm
+++ b/Source/HBIOS/tms.asm
@ -43,32 +43,24 @@
 TMSCTRL1:       .EQU   1               ; CONTROL BITS
 TMSINTEN:       .EQU   5               ; INTERRUPT ENABLE BIT
 ;
-		.ECHO	"TMS: MODE="
+		DEVECHO	"TMS: MODE="
 ;
 #IF ((TMSMODE == TMSMODE_MSX) | (TMSMODE == TMSMODE_MSX9958))
 TMS_DATREG	.EQU	$98		; READ/WRITE DATA
 TMS_CMDREG	.EQU	$99		; READ STATUS / WRITE REG SEL
-TMS_PPIA	.EQU	0		; PPI PORT A
-TMS_PPIB	.EQU	0		; PPI PORT B
-TMS_PPIC	.EQU	0		; PPI PORT C
-TMS_PPIX	.EQU	0		; PPI CONTROL PORT
 ;
  #IF (TMSMODE == TMSMODE_MSX)
-		.ECHO	"MSX"
+		DEVECHO	"MSX"
  #ENDIF
  #IF (TMSMODE == TMSMODE_MSX9958)
-		.ECHO	"MSX9958"
+		DEVECHO	"MSX9958"
  #ENDIF
 #ENDIF
 ;
 #IF (TMSMODE == TMSMODE_COLECO)
 TMS_DATREG	.EQU	$BE		; READ/WRITE DATA
 TMS_CMDREG	.EQU	$BF		; READ STATUS / WRITE REG SEL
-TMS_PPIA	.EQU	0		; PPI PORT A
-TMS_PPIB	.EQU	0		; PPI PORT B
-TMS_PPIC	.EQU	0		; PPI PORT C
-TMS_PPIX	.EQU	0		; PPI CONTROL PORT
-		.ECHO	"COLECO"
+		DEVECHO	"COLECO"
 #ENDIF
 ;
 #IF (TMSMODE == TMSMODE_MSXKBD)
@ -76,7 +68,7 @@ TMS_DATREG	.EQU	$98		; READ/WRITE DATA
 TMS_CMDREG	.EQU	$99		; READ STATUS / WRITE REG SEL
 TMS_KBDDATA	.EQU	$E0		; KBD CTLR DATA PORT
 TMS_KBDST	.EQU	$E1		; KBD CTLR STATUS/CMD PORT
-		.ECHO	"MSXKBD"
+		DEVECHO	"MSXKBD"
 #ENDIF
 ;
 #IF (TMSMODE == TMSMODE_N8)
@ -86,56 +78,56 @@ TMS_PPIA	.EQU	$84		; PPI PORT A
 TMS_PPIB	.EQU	$85		; PPI PORT B
 TMS_PPIC	.EQU	$86		; PPI PORT C
 TMS_PPIX	.EQU	$87		; PPI CONTROL PORT
-		.ECHO	"N8"
+		DEVECHO	"N8"
 #ENDIF
 ;
 #IF (TMSMODE == TMSMODE_SCG)
 TMS_DATREG	.EQU	$98		; READ/WRITE DATA
 TMS_CMDREG	.EQU	$99		; READ STATUS / WRITE REG SEL
 TMS_ACR		.EQU	$9C		; AUX CONTROL REGISTER
-TMS_PPIA	.EQU	0		; PPI PORT A
-TMS_PPIB	.EQU	0		; PPI PORT B
-TMS_PPIC	.EQU	0		; PPI PORT C
-TMS_PPIX	.EQU	0		; PPI CONTROL PORT
-		.ECHO	"SCG"
+		DEVECHO	"SCG"
 #ENDIF
 ;
 #IF (TMSMODE == TMSMODE_MBC)
 TMS_DATREG	.EQU	$98		; READ/WRITE DATA
 TMS_CMDREG	.EQU	$99		; READ STATUS / WRITE REG SEL
 TMS_ACR		.EQU	$9C		; AUX CONTROL REGISTER
-TMS_PPIA	.EQU	0		; PPI PORT A
-TMS_PPIB	.EQU	0		; PPI PORT B
-TMS_PPIC	.EQU	0		; PPI PORT C
-TMS_PPIX	.EQU	0		; PPI CONTROL PORT
 TMS_KBDDATA	.EQU	$E2		; KBD CTLR DATA PORT
 TMS_KBDST	.EQU	$E3		; KBD CTLR STATUS/CMD PORT
-		.ECHO	"MBC"
+		DEVECHO	"MBC"
 #ENDIF

 #IF (TMSMODE == TMSMODE_DUO)
 TMS_DATREG	.EQU	$A0		; READ/WRITE DATA
 TMS_CMDREG	.EQU	$A1		; READ STATUS / WRITE REG SEL
 TMS_ACR		.EQU	$A6		; AUX CONTROL REGISTER
-TMS_PPIA	.EQU	0		; PPI PORT A
-TMS_PPIB	.EQU	0		; PPI PORT B
-TMS_PPIC	.EQU	0		; PPI PORT C
-TMS_PPIX	.EQU	0		; PPI CONTROL PORT
 TMS_KBDDATA	.EQU	$4C		; KBD CTLR DATA PORT
 TMS_KBDST	.EQU	$4D		; KBD CTLR STATUS/CMD PORT
-		.ECHO	"DUO"
+		DEVECHO	"DUO"
 #ENDIF
 ;
-		.ECHO	", IO="
-		.ECHO	TMS_DATREG
-#IF TMSTIMENABLE
-		.ECHO	", INTERRUPTS ENABLED"
+#IF ((TMSMODE == TMSMODE_NABU40) | (TMSMODE == TMSMODE_NABU80))
+TMS_DATREG	.EQU	$A0		; READ/WRITE DATA
+TMS_CMDREG	.EQU	$A1		; READ STATUS / WRITE REG SEL
+;
+  #IF (TMSMODE == TMSMODE_NABU40)
+		DEVECHO	"NABU-40"
+  #ENDIF
+  #IF (TMSMODE == TMSMODE_NABU80)
+		DEVECHO	"NABU-80"
+  #ENDIF
+#ENDIF
+;
+		DEVECHO	", IO="
+		DEVECHO	TMS_DATREG
+#IF (TMSTIMENABLE & (INTMODE > 0))
+		DEVECHO	", INTERRUPTS ENABLED"
 #ENDIF
-		.ECHO	"\n"
+		DEVECHO	"\n"
 ;
 TMS_ROWS	.EQU	24
 ;
-#IF ((TMSMODE == TMSMODE_MSX9958) | (TMSMODE == TMSMODE_MBC) | (TMSMODE == TMSMODE_DUO))
+#IF ((TMSMODE == TMSMODE_MSX9958) | (TMSMODE == TMSMODE_MBC) | (TMSMODE == TMSMODE_DUO) | (TMSMODE == TMSMODE_NABU80))
 TMS_FNTVADDR	.EQU	$1000		; VRAM ADDRESS OF FONT DATA
 TMS_FNTSIZE	.EQU	8*256		; ### JLC Mod for JBL compatibility ### = 8x8 Font 256 Chars
 TMS_CHRVADDR	.EQU	$0000		; VRAM ADDRESS OF CHAR SCREEN DATA (NEW CONSTANT) = REG2 * $400
@ -162,6 +154,10 @@ PPKENABLE	.SET	TRUE		; INCLUDE PPK KEYBOARD SUPPORT
 KBDENABLE	.SET	TRUE		; INCLUDE KBD KEYBOARD SUPPORT
 #ENDIF
 ;
+#IF ((TMSMODE == TMSMODE_NABU40) |(TMSMODE == TMSMODE_NABU80))
+NABUKBENABLE	.SET	TRUE		; INCLUDE NABU KEYBOARD SUPPORT
+#ENDIF
+;
 ; TMS_IODELAY IS USED TO ADD RECOVERY TIME TO TMS9918/V9958 ACCESSES
 ; IF YOU SEE SCREEN CORRUPTION, ADJUST THIS!!!
 ;
@ -171,7 +167,7 @@ KBDENABLE	.SET	TRUE		; INCLUDE KBD KEYBOARD SUPPORT
  ;#DEFINE	TMS_IODELAY	NOP \ NOP \ NOP \ NOP \ NOP ; 20 W/S ### JLC Mod for Clock/2 (9 MHz) ###
 #ELSE
  ; BELOW WAS TUNED FOR SBC AT 8MHZ
-  #IF ((TMSMODE == TMSMODE_MSX9958) | (TMSMODE == TMSMODE_MBC) | (TMSMODE == TMSMODE_DUO))
+  #IF ((TMSMODE == TMSMODE_MSX9958) | (TMSMODE == TMSMODE_MBC) | (TMSMODE == TMSMODE_DUO) | (TMSMODE == TMSMODE_NABU40) | (TMSMODE == TMSMODE_NABU80))
    #DEFINE	TMS_IODELAY	NOP \ NOP \ NOP \ NOP \ NOP \ NOP \ NOP ; V9958 NEEDS AT WORST CASE, APPROX 4us (28T) DELAY BETWEEN I/O (WHEN IN TEXT MODE)
  #ELSE
    #DEFINE	TMS_IODELAY	NOP \ NOP ; 8 W/S
@ -183,6 +179,9 @@ KBDENABLE	.SET	TRUE		; INCLUDE KBD KEYBOARD SUPPORT
 ;======================================================================
 ;
 TMS_PREINIT:
+#IF (NABUKBENABLE == TRUE)
+	CALL NABUKB_PREINIT
+#ENDIF
 	; DISABLE INTERRUPT GENERATION
 	LD	A, (TMS_INITVDU_REG_1)
        RES	TMSINTEN, A             ; RESET INTERRUPT ENABLE BIT
@ -234,6 +233,12 @@ TMS_INIT:
 #IF (TMSMODE == TMSMODE_MSX9958)
 	PRTS("RC_V9958$")
 #ENDIF
+#IF (TMSMODE == TMSMODE_NABU40)
+	PRTS("NABU-40$")
+#ENDIF
+#IF (TMSMODE == TMSMODE_NABU80)
+	PRTS("NABU-80$")
+#ENDIF
 ;
 	PRTS(" IO=0x$")
 	LD	A,TMS_DATREG
@ -259,18 +264,30 @@ TMS_INIT1:
 #IF MKYENABLE
 	CALL	MKY_INIT		; INITIALIZE MKY KEYBOARD DRIVER
 #ENDIF
+#IF ((TMSMODE == TMSMODE_NABU40) | (TMSMODE == TMSMODE_NABU80))
+	CALL	NABUKB_INIT		; INITIALIZE NABU KEYBOARD DRIVER
+#ENDIF

-#IF (INTMODE == 1 & TMSTIMENABLE)
+#IF (TMSTIMENABLE & (INTMODE > 0))
+;
+  #IF (INTMODE == 1)
 	; ADD IM1 INT CALL LIST ENTRY
-	LD	HL, TMS_TSTINT		; GET INT VECTOR
+	LD	HL,TMS_TSTINT		; GET INT VECTOR
 	CALL	HB_ADDIM1		; ADD TO IM1 CALL LIST
-
+  #ELSE
+	; INSTALL VECTOR
+	LD	HL,TMS_TSTINT
+	LD	(IVT(INT_VDP)),HL	; IVT INDEX
+  #ENDIF
+;
 	LD	A, (TMS_INITVDU_REG_1)
 	SET	TMSINTEN,A		; SET INTERRUPT ENABLE BIT
 	LD	(TMS_INITVDU_REG_1),A
 	LD	C, TMSCTRL1
 	CALL	TMS_SET
+;
 #ENDIF
+
 ;
 	; ADD OURSELVES TO VDA DISPATCH TABLE
 	LD	BC,TMS_FNTBL		; BC := FUNCTION TABLE ADDRESS
@ -307,22 +324,26 @@ TMS_FNTBL:
 	.DW	PPK_STAT
 	.DW	PPK_FLUSH
 	.DW	PPK_READ
-#ELSE
-  #IF  ((TMSMODE == TMSMODE_MSXKBD) | (TMSMODE == TMSMODE_MBC) | (TMSMODE == TMSMODE_DUO))
+#ENDIF
+#IF  ((TMSMODE == TMSMODE_MSXKBD) | (TMSMODE == TMSMODE_MBC) | (TMSMODE == TMSMODE_DUO))
  	.DW	KBD_STAT
  	.DW	KBD_FLUSH
  	.DW	KBD_READ
-  #ELSE
-    #IF MKYENABLE
+#ENDIF
+#IF ((TMSMODE == TMSMODE_NABU40) | (TMSMODE == TMSMODE_NABU80))
+	.DW	NABUKB_STAT
+	.DW	NABUKB_FLUSH
+	.DW	NABUKB_READ
+#ENDIF
+#IF ((TMSMODE == TMSMODE_MSX) | (TMSMODE == TMSMODE_MSX9958) | (TMSMODE == TMSMODE_SCG) | (TMSMODE == TMSMODE_COLECO))
+  #IF MKYENABLE
  	.DW	MKY_STAT
  	.DW	MKY_FLUSH
  	.DW	MKY_READ
-
-    #ELSE
+  #ELSE
  	.DW	TMS_STAT
  	.DW	TMS_FLUSH
  	.DW	TMS_READ
-    #ENDIF
  #ENDIF
 #ENDIF
 	.DW	TMS_VDARDC
@ -352,15 +373,11 @@ TMS_VDARES:
 	CALL	TMS_Z180IO
 #ENDIF
 	CALL	TMS_CRTINIT1A
-#IF (!USELZSA2)
-	; WE WANT TO RELOAD THE FONT ON RESET, BUT THIS IS NOT CURRENTLY
-	; POSSIBLE WHEN FONT COMPRESSION IS IN USE.
 	CALL	TMS_CLRCUR		; CLEAR CURSOR
 	CALL	TMS_LOADFONT		; RELOAD FONT
 	LD	A,$FF			; REMOVE
 	LD	(TMS_CURSAV),A		; ... SAVED CURSOR CHAR
 	CALL	TMS_SETCUR		; RESTORE CURSOR
-#ENDIF
 	XOR	A
 	RET

@ -526,12 +543,14 @@ TMS_READ:
 ;----------------------------------------------------------------------
 ;
 TMS_SET:
+	HB_DI
 	OUT	(TMS_CMDREG),A		; WRITE IT
 	TMS_IODELAY
 	LD	A,C			; GET THE DESIRED REGISTER
 	OR	$80			; SET BIT 7
 	OUT	(TMS_CMDREG),A		; SELECT THE DESIRED REGISTER
 	TMS_IODELAY
+	HB_EI
 	RET
 ;
 ;----------------------------------------------------------------------
@ -541,14 +560,16 @@ TMS_SET:
 ;----------------------------------------------------------------------
 ;
 TMS_WR:
-#IF ((TMSMODE == TMSMODE_MSX9958)  | (TMSMODE == TMSMODE_MBC) | (TMSMODE == TMSMODE_DUO))
+#IF ((TMSMODE == TMSMODE_MSX9958)  | (TMSMODE == TMSMODE_MBC) | (TMSMODE == TMSMODE_DUO) | (TMSMODE == TMSMODE_NABU80))
        ; CLEAR R#14 FOR V9958
+	HB_DI
        XOR     A
        OUT     (TMS_CMDREG), A
 	TMS_IODELAY
        LD      A, $80 | 14
        OUT     (TMS_CMDREG), A
 	TMS_IODELAY
+	HB_EI
 #ENDIF

 	PUSH	HL
@ -558,12 +579,14 @@ TMS_WR:
 	RET
 ;
 TMS_RD:
+	HB_DI
 	LD	A,L
 	OUT	(TMS_CMDREG),A
 	TMS_IODELAY
 	LD	A,H
 	OUT	(TMS_CMDREG),A
 	TMS_IODELAY
+	HB_EI
 	RET
 ;
 ;----------------------------------------------------------------------
@ -637,7 +660,7 @@ TMS_CRTINIT2:
 	DJNZ	TMS_CRTINIT2		; LOOP
 ;
 	; ENABLE WAIT SIGNAL IF 9938/58
-#IF ((TMSMODE == TMSMODE_MSX9958) | (TMSMODE == TMSMODE_MBC) | (TMSMODE == TMSMODE_DUO))
+#IF ((TMSMODE == TMSMODE_MSX9958) | (TMSMODE == TMSMODE_MBC) | (TMSMODE == TMSMODE_DUO) | (TMSMODE == TMSMODE_NABU80))
 	LD	C,25			; REGISTER 25
 	LD	A,%00000100		; ONLY WTE BIT SET
 	CALL	TMS_SET			; DO IT
@ -672,8 +695,15 @@ TMS_LOADFONT:
 	; SET WRITE ADDRESS TO TMS_FNTVADDR
 	LD	HL,TMS_FNTVADDR
 	CALL	TMS_WR
-
-#IF USELZSA2
+;
+; THE USE OF COMPRESSED FONT STORAGE FOR THE TMS DRIVER IS DISABLED
+; SO THAT WE CAN RELOAD THE FONT DATA ON USER RESET.  THE TMS CHIP
+; IS FREQUENTLY REPROGRAMMED BY GAMES, ETC., SO IT IS NECESSARY TO
+; REINIT AND RELOAD FONTS.  RELOADING A COMPRESSED FONT AFTER
+; SYSTEM INITIALIZATION REQUIRES A LARGE DECOMPRESSION BUFFER THAT WE
+; HAVE NO WAY TO ACCOMMODATE WITHOUT TRASHING OS/APP MEMORY.
+;
+#IF USELZSA2 & FALSE
 	LD	(TMS_STACK),SP		; SAVE STACK
 	LD	HL,(TMS_STACK)		; AND SHIFT IT
 	LD	DE,$2000		; DOWN 4KB TO
@ -701,7 +731,7 @@ TMS_LOADFONT1:
 	OR	E
 	JR	NZ,TMS_LOADFONT1
 ;
-#IF USELZSA2
+#IF USELZSA2 & FALSE
 	LD	HL,(TMS_STACK)		; ERASE DECOMPRESS BUFFER
 	LD	SP,HL			; BY RESTORING THE STACK
 	RET				; DONE
@ -1030,11 +1060,11 @@ TMS_Z180IOX:
 ;
 #ENDIF

-#IF (INTMODE == 1 & TMSTIMENABLE)
+#IF (TMSTIMENABLE & (INTMODE > 0))
 TMS_TSTINT:
- 	IN      A, (TMS_CMDREG)		; TEST FOR INT FLAG
+ 	IN      A,(TMS_CMDREG)		; TEST FOR INT FLAG
 	AND	$80
-	JR	NZ, TMS_INTHNDL
+	JR	NZ,TMS_INTHNDL
 	AND	$00			; RETURN Z - NOT HANDLED
 	RET

@ -1066,7 +1096,7 @@ TMS_COLOR_TBL	.DB	$01,$08,$02,$0A,$04,$06,$0C,$0F,$0E,$09,$03,$0B,$05,$0D,$07,$0
 ;==================================================================================================
 ;
 TMS_IDAT:
-#IF ((TMSMODE == TMSMODE_MSX) | (TMSMODE == TMSMODE_MSX9958) | (TMSMODE == TMSMODE_N8) | (TMSMODE == TMSMODE_SCG))
+#IF ((TMSMODE == TMSMODE_N8))
 	.DB	TMS_PPIA		; PPI PORT A
 	.DB	TMS_PPIB		; PPI PORT B
 	.DB	TMS_PPIC		; PPI PORT C
@ -1078,6 +1108,9 @@ TMS_IDAT:
 	.DB	TMS_KBDDATA		; 8242 DATA PORT
 	.DB	0			; FILLER
 #ENDIF
+#IF ((TMSMODE == TMSMODE_MSX) | (TMSMODE == TMSMODE_MSX9958) | (TMSMODE == TMSMODE_SCG) | (TMSMODE == TMSMODE_COLECO) | (TMSMODE == TMSMODE_NABU40) | (TMSMODE == TMSMODE_NABU80))
+	.FILL	4,0			; DUMMY KEYBOARD CONFIG DATA
+#ENDIF
 ;
 	.DB	TMS_DATREG
 	.DB	TMS_CMDREG
@ -1124,7 +1157,7 @@ TMS_IDAT:
 ; 5S		Fifth sprite (not displayed) detected. Value in FS* is valid.
 ; INT		Set at each screen update, used for interrupts.
 ;
-#IF ((TMSMODE == TMSMODE_MSX9958) | (TMSMODE == TMSMODE_MBC) | (TMSMODE == TMSMODE_DUO))
+#IF ((TMSMODE == TMSMODE_MSX9958) | (TMSMODE == TMSMODE_MBC) | (TMSMODE == TMSMODE_DUO) | (TMSMODE == TMSMODE_NABU80))
 ;
 ; NOTE: YAMAHA 9938/58 DOCUMENTATION SAYS R3 IS SAME AS 9918 (ADR >> 10),
 ; BUT THIS SEEMS TO BE WRONG AND CORRECTLY DOCUMENTED AT
--- a/Source/HBIOS/uart.asm
+++ b/Source/HBIOS/uart.asm
@ -57,7 +57,14 @@ UART_CTSBAD		.EQU	4	; CTS STALL DETECTED
 #IF (PLATFORM == PLT_DUO)
 UARTSBASE		.EQU	$58
 UARTDBASE		.EQU	$70
-#ELSE
+#ENDIF
+;
+#IF (PLATFORM == PLT_NABU)
+UARTSBASE		.EQU	$48
+UARTDBASE		.EQU	$80
+#ENDIF
+;
+#IF ((PLATFORM != PLT_DUO) & (PLATFORM != PLT_NABU))
 UARTSBASE		.EQU	$68
 UARTDBASE		.EQU	$80
 #ENDIF
@ -78,7 +85,6 @@ UART1_IVT	.EQU	IVT(INT_UART1)
  #ENDIF
 ;
 #ENDIF
-
 ;
 #DEFINE	UART_INP(RID)	CALL UART_INP_IMP \ .DB RID
 #DEFINE	UART_OUTP(RID)	CALL UART_OUTP_IMP \ .DB RID
@ -1032,12 +1038,12 @@ UART_CFG_SBC:
 	.DW	UARTCFG				; LINE CONFIGURATION
 	.DW	UARTSBC_RCVBUF			; POINTER TO RCV BUFFER STRUCT
 ;
-	.ECHO	"UART: MODE=SBC, IO="
-	.ECHO	UARTSBASE
+	DEVECHO	"UART: MODE=SBC, IO="
+	DEVECHO	UARTSBASE
  #IF ((UARTINTS) & (INTMODE > 0))
-	.ECHO	", INTERRUPTS ENABLED"
+	DEVECHO	", INTERRUPTS ENABLED"
  #ENDIF
-	.ECHO	"\n"
+	DEVECHO	"\n"
 #ENDIF
 #IF (UARTAUX)
 UART_CFG_AUX:
@ -1049,9 +1055,9 @@ UART_CFG_AUX:
 	.DW	UARTCFG				; LINE CONFIGURATION
 	.DW	0				; NO INT HANDLER
 ;
-	.ECHO	"UART: MODE=AUX, IO="
-	.ECHO	UARTABASE
-	.ECHO	"\n"
+	DEVECHO	"UART: MODE=AUX, IO="
+	DEVECHO	UARTABASE
+	DEVECHO	"\n"
 #ENDIF
 #IF (UARTCAS)
 UART_CFG_CAS:
@ -1063,12 +1069,12 @@ UART_CFG_CAS:
 	.DW	UARTCASSPD			; LINE CONFIGURATION
 	.DW	UARTCAS_RCVBUF			; POINTER TO RCV BUFFER STRUCT
 ;
-	.ECHO	"UART: MODE=CAS, IO="
-	.ECHO	UARTCBASE
+	DEVECHO	"UART: MODE=CAS, IO="
+	DEVECHO	UARTCBASE
  #IF ((UARTINTS) & (INTMODE > 0))
-	.ECHO	", INTERRUPTS ENABLED"
+	DEVECHO	", INTERRUPTS ENABLED"
  #ENDIF
-	.ECHO	"\n"
+	DEVECHO	"\n"
 #ENDIF
 #IF (UARTMFP)
 UART_CFG_MFP:
@ -1080,9 +1086,9 @@ UART_CFG_MFP:
 	.DW	UARTCFG				; LINE CONFIGURATION
 	.DW	0				; SHOULD NEVER NEED INT HANDLER
 ;
-	.ECHO	"UART: MODE=MFP, IO="
-	.ECHO	UARTSBASE
-	.ECHO	"\n"
+	DEVECHO	"UART: MODE=MFP, IO="
+	DEVECHO	UARTSBASE
+	DEVECHO	"\n"
 #ENDIF
 #IF (UART4)
 	; 4UART SERIAL PORT A
@ -1093,9 +1099,9 @@ UART_CFG_MFP:
 	.DW	UARTCFG				; LINE CONFIGURATION
 	.DW	0				; SHOULD NEVER NEED INT HANDLER
 ;
-	.ECHO	"UART: MODE=4UART, IO="
-	.ECHO	UART4BASE+0
-	.ECHO	"\n"
+	DEVECHO	"UART: MODE=4UART, IO="
+	DEVECHO	UART4BASE+0
+	DEVECHO	"\n"
 ;
 	; 4UART SERIAL PORT B
 	.DB	0				; DEVICE NUMBER (UPDATED DURING INIT)
@ -1105,9 +1111,9 @@ UART_CFG_MFP:
 	.DW	UARTCFG				; LINE CONFIGURATION
 	.DW	0				; SHOULD NEVER NEED INT HANDLER
 ;
-	.ECHO	"UART: MODE=4UART, IO="
-	.ECHO	UART4BASE+8
-	.ECHO	"\n"
+	DEVECHO	"UART: MODE=4UART, IO="
+	DEVECHO	UART4BASE+8
+	DEVECHO	"\n"
 ;
 	; 4UART SERIAL PORT C
 	.DB	0				; DEVICE NUMBER (UPDATED DURING INIT)
@ -1117,9 +1123,9 @@ UART_CFG_MFP:
 	.DW	UARTCFG				; LINE CONFIGURATION
 	.DW	0				; SHOULD NEVER NEED INT HANDLER
 ;
-	.ECHO	"UART: MODE=4UART, IO="
-	.ECHO	UART4BASE+16
-	.ECHO	"\n"
+	DEVECHO	"UART: MODE=4UART, IO="
+	DEVECHO	UART4BASE+16
+	DEVECHO	"\n"
 ;
 	; 4UART SERIAL PORT D
 	.DB	0				; DEVICE NUMBER (UPDATED DURING INIT)
@ -1129,9 +1135,9 @@ UART_CFG_MFP:
 	.DW	UARTCFG				; LINE CONFIGURATION
 	.DW	0				; SHOULD NEVER NEED INT HANDLER
 ;
-	.ECHO	"UART: MODE=4UART, IO="
-	.ECHO	UART4BASE+24
-	.ECHO	"\n"
+	DEVECHO	"UART: MODE=4UART, IO="
+	DEVECHO	UART4BASE+24
+	DEVECHO	"\n"
 #ENDIF
 #IF (UARTRC)
 	; UARTRC SERIAL PORT A
@ -1142,9 +1148,9 @@ UART_CFG_MFP:
 	.DW	UARTCFG				; LINE CONFIGURATION
 	.DW	0				; SHOULD NEVER NEED INT HANDLER
 ;
-	.ECHO	"UART: MODE=RC, IO="
-	.ECHO	UARTRBASE+0
-	.ECHO	"\n"
+	DEVECHO	"UART: MODE=RC, IO="
+	DEVECHO	UARTRBASE+0
+	DEVECHO	"\n"
 ;
 	; UARTRC SERIAL PORT B
 	.DB	0				; DEVICE NUMBER (UPDATED DURING INIT)
@ -1154,9 +1160,9 @@ UART_CFG_MFP:
 	.DW	UARTCFG				; LINE CONFIGURATION
 	.DW	0				; SHOULD NEVER NEED INT HANDLER
 ;
-	.ECHO	"UART: MODE=RC, IO="
-	.ECHO	UARTRBASE+8
-	.ECHO	"\n"
+	DEVECHO	"UART: MODE=RC, IO="
+	DEVECHO	UARTRBASE+8
+	DEVECHO	"\n"
 ;
 #ENDIF
 #IF (UARTDUAL)
@ -1175,13 +1181,13 @@ UART_CFG_MFP:
 	.DW	UARTCFG				; LINE CONFIGURATION
 	.DW	0				; SHOULD NEVER NEED INT HANDLER
 ;
-	.ECHO	"UART: MODE=DUAL, IO="
-	.ECHO	UARTDBASE+8
-	.ECHO	"\n"
+	DEVECHO	"UART: MODE=DUAL, IO="
+	DEVECHO	UARTDBASE+8
+	DEVECHO	"\n"
 ;
-	.ECHO	"UART: MODE=DUAL, IO="
-	.ECHO	UARTDBASE+0
-	.ECHO	"\n"
+	DEVECHO	"UART: MODE=DUAL, IO="
+	DEVECHO	UARTDBASE+0
+	DEVECHO	"\n"
 ;
 #ENDIF
 ;