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Merge pull request #19 from wwarthen/master

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Dynamic DS-1302 Detection
This commit is contained in:
b1ackmai1er
2019-09-30 13:32:40 +08:00
committed by GitHub
parent 866449c8ee 341c55945c
commit 88940645c0
16 changed files with 135 additions and 469 deletions
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2
Source/CBIOS/ver.inc
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@@ -2,4 +2,4 @@
#DEFINE RMN 9
#DEFINE RUP 2
#DEFINE RTP 0
#DEFINE BIOSVER "2.9.2-pre.11"
#DEFINE BIOSVER "2.9.2-pre.12"

2
Source/HBIOS/Config/RCZ180_ext.asm
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@@ -32,8 +32,6 @@ Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3)
Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
;
DSRTCENABLE .SET FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
;
ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)

2
Source/HBIOS/Config/RCZ180_nat.asm
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@@ -32,8 +32,6 @@ Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3)
Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
;
DSRTCENABLE .SET FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
;
ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)

2
Source/HBIOS/Config/RCZ80_kio.asm
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@@ -33,8 +33,6 @@ KIOENABLE .SET TRUE ; ENABLE ZILOG KIO SUPPORT
CTCENABLE .SET TRUE ; ENABLE ZILOG CTC SUPPORT
CTCBASE .SET KIOBASE+$04 ; CTC BASE I/O ADDRESS
;
DSRTCENABLE .SET FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
;
ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
SIOCNT .SET 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP

2
Source/HBIOS/Config/RCZ80_std.asm
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@@ -27,8 +27,6 @@
CPUOSC .SET 7372800 ; CPU OSC FREQ IN MHZ
DEFSERCFG .SET SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
DSRTCENABLE .SET FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
;
ACIAENABLE .SET TRUE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
;

2
Source/HBIOS/cfg_ezz80.asm
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@@ -56,7 +56,7 @@ ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT
SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
;
DSRTCENABLE .EQU FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
DSRTCENABLE .EQU TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
;

2
Source/HBIOS/cfg_rcz180.asm
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@@ -60,7 +60,7 @@ ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT
SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
;
DSRTCENABLE .EQU FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
DSRTCENABLE .EQU TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
;

2
Source/HBIOS/cfg_rcz80.asm
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@@ -55,7 +55,7 @@ ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT
SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
;
DSRTCENABLE .EQU FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
DSRTCENABLE .EQU TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
;

134
Source/HBIOS/dsrtc.asm
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@@ -122,6 +122,34 @@ DSRTC_IDLE .EQU %00101000 ; QUIESCENT STATE
;
DSRTC_BUFSIZ .EQU 7 ; 7 BYTE BUFFER (YYMMDDHHMMSSWW)
;
; RTC DEVICE PRE-INITIALIZATION ENTRY
;
DSRTC_PREINIT:
;
; SET RELEVANT BITS IN RTC LATCH SHADOW REGISTER
; TO THEIR QUIESENT STATE
LD A,(RTCVAL) ; GET CURRENT SHADOW REG VAL
AND DSRTC_MASK ; CLEAR OUR BITS
OR DSRTC_IDLE ; SET OUR IDLE BITS
LD (RTCVAL),A ; SAVE IT
;
CALL DSRTC_DETECT ; HARDWARE DETECTION
LD (DSRTC_STAT),A ; SAVE RESULT
RET NZ ; ABORT IF ERROR
;
; CHECK FOR CLOCK HALTED
CALL DSRTC_TSTCLK
JR Z,DSRTC_PREINIT1
;PRTS(" INIT CLOCK $")
LD HL,DSRTC_TIMDEF
CALL DSRTC_TIM2CLK
LD HL,DSRTC_BUF
CALL DSRTC_WRCLK
;
DSRTC_PREINIT1:
XOR A ; SIGNAL SUCCESS
RET ; DONE
;
; RTC DEVICE INITIALIZATION ENTRY
;
DSRTC_INIT:
@@ -135,21 +163,16 @@ DSRTC_INIT:
PRTS("MFPIC$")
#ENDIF
;
; SET RELEVANT BITS IN RTC LATCH SHADOW REGISTER
; TO THEIR QUIESENT STATE
LD A,(RTCVAL)
AND DSRTC_MASK
OR DSRTC_IDLE
LD (RTCVAL),A
LD A,(DSRTC_STAT)
OR A
JR Z,DSRTC_INIT0
;
; CHECK FOR CLOCK HALTED
CALL DSRTC_TSTCLK
JR Z,DSRTC_INIT1
PRTS(" INIT CLOCK $")
LD HL,DSRTC_TIMDEF
CALL DSRTC_TIM2CLK
LD HL,DSRTC_BUF
CALL DSRTC_WRCLK
; HARDWARE NOT PRESENT
PRTS(" NOT PRESENT$")
OR $FF ; SIGNAL FAILURE
RET
;
DSRTC_INIT0:
;
DSRTC_INIT1:
; DISPLAY CURRENT TIME
@@ -214,8 +237,6 @@ DSRTC_DISPATCH:
;
; NVRAM FUNCTIONS ARE NOT AVAILABLE IN SIMULATOR
;
DSRTC_GETBYT:
DSRTC_SETBYT:
DSRTC_GETBLK:
DSRTC_SETBLK:
CALL PANIC
@@ -289,6 +310,56 @@ DSRTC_SETTIM:
XOR A ; SIGNAL SUCCESS
RET ; AND RETURN
;
; RTC GET NVRAM BYTE
; C: INDEX
; E: VALUE (OUTPUT)
;
DSRTC_GETBYT:
LD A,C ; INDEX
SLA A ; SHIFT TO INDEX BITS
ADD A,$C1 ; CMD OFFSET
LD E,A
CALL DSRTC_CMD
CALL DSRTC_GET
CALL DSRTC_END
XOR A
RET
;
; RTC SET NVRAM BYTE
; C: INDEX
; E: VALUE
;
DSRTC_SETBYT:
PUSH DE ; SAVE INCOMING INDEX
;
; TURN OFF WRITE PROTECT
LD E,$8E ; ACCESS WRITE PROT REG
CALL DSRTC_CMD ;
LD E,$00 ; WRITE PROTECT OFF
CALL DSRTC_PUT ;
CALL DSRTC_END ; FINISH CMD
;
; SET REGISTER VALUE
LD A,C ; INDEX
SLA A ; SHIFT TO INDEX BITS
ADD A,$C0 ; CMD OFFSET
LD E,A ; INTO E
CALL DSRTC_CMD
POP DE
CALL DSRTC_PUT
CALL DSRTC_END
;
; TURN ON WRITE PROTECT
LD E,$8E ; ACCESS WRITE PROT REG
CALL DSRTC_CMD ;
LD E,$80 ; WRITE PROTECT ON
CALL DSRTC_PUT ;
CALL DSRTC_END ; FINISH CMD
;
; SIGNAL SUCCESS
XOR A
RET
;
; CONVERT DATA IN CLOCK BUFFER TO TIME BUFFER AT HL
;
DSRTC_CLK2TIM:
@@ -350,6 +421,34 @@ DSRTC_TSTCHG:
CP %10100000 ; ENABLED FLAG
RET
;
; DETECT RTC HARDWARE PRESENCE
;
DSRTC_DETECT:
LD C,31 ; NVRAM INDEX 31
CALL DSRTC_GETBYT ; GET VALUE
LD A,E ; TO ACCUM
LD (DSRTC_TEMP),A ; SAVE IT
XOR $FF ; FLIP ALL BITS
LD E,A ; TO E
LD C,31 ; NVRAM INDEX 31
CALL DSRTC_SETBYT ; WRITE IT
LD C,31 ; NVRAM INDEX 31
CALL DSRTC_GETBYT ; GET VALUE
LD A,(DSRTC_TEMP) ; GET SAVED VALUE
XOR $FF ; FLIP ALL BITS
CP E ; COMPARE WITH VALUE READ
LD A,0 ; ASSUME OK
JR Z,DSRTC_DETECT1 ; IF MATCH, GO AHEAD
LD A,$FF ; ELSE STATUS IS ERROR
DSRTC_DETECT1:
PUSH AF ; SAVE STATUS
LD A,(DSRTC_TEMP) ; GET SAVED VALUE
LD C,31 ; NVRAM INDEX 31
CALL DSRTC_SETBYT ; SAVE IT
POP AF ; RECOVER STATUS
OR A ; SET FLAGS
RET ; DONE
;
; TEST CLOCK FOR VALID DATA
; READ CLOCK HALT BIT AND RETURN ZF BASED ON BIT VALUE
; 0 = RUNNING
@@ -524,6 +623,9 @@ DSRTC_END:
;
; WORKING VARIABLES
;
DSRTC_STAT .DB 0 ; DEVICE STATUS (0=OK)
DSRTC_TEMP .DB 0 ; TEMP VALUE STORAGE
;
; DSRTC_BUF IS USED FOR BURST READ/WRITE OF CLOCK DATA TO DS-1302
; FIELDS BELOW MATCH ORDER OF DS-1302 FIELDS (BCD)
;

17
Source/HBIOS/hbios.asm
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@@ -1273,6 +1273,10 @@ HB_CPU1:
;
#ENDIF
;
#IF (DSRTCENABLE)
CALL DSRTC_PREINIT
#ENDIF
;
#IF (CPUFAM == CPU_Z180)
;
; AT BOOT, Z180 PHI IS OSC / 2
@@ -1351,7 +1355,6 @@ HB_CPU2:
;
; PRE-CONSOLE INITIALIZATION
;
LD A,FORCECON ; CALCULATE PRE-INIT TABLE ; A IS INDEX OF CONSOLE DEVICE ENTRY
RLCA ; ENTRY THAT WE WANT TO ; A IS OFFSET OF CONSOLE DEVICE ENTRY
LD DE,(PC_INITTBL) ; EXECUTE FIRST ; DE IS VALUE OF TOP ENTRY
@@ -3195,15 +3198,9 @@ HB_CPUSPD:
;
#IF (DSRTCENABLE)
;
CALL DSRTC_TSTCLK ; IS CLOCK RUNNING?
JR Z,HB_CPUSPD1 ; YES, CONTINUE
; MAKE SURE CLOCK IS RUNNING
LD HL,DSRTC_TIMDEF
CALL DSRTC_TIM2CLK
LD HL,DSRTC_BUF
CALL DSRTC_WRCLK
CALL DSRTC_TSTCLK ; NOW IS CLOCK RUNNING?
RET NZ
LD A,(DSRTC_STAT) ; GET RTC STATUS
OR A ; SET FLAGS
RET NZ ; NOT ZERO IS ERROR
;
HB_CPUSPD1:
#IF (CPUFAM == CPU_Z180)

2
Source/HBIOS/ver.inc
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@@ -2,4 +2,4 @@
#DEFINE RMN 9
#DEFINE RUP 2
#DEFINE RTP 0
#DEFINE BIOSVER "2.9.2-pre.11"
#DEFINE BIOSVER "2.9.2-pre.12"

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Source/ZSDOS/Distribution/ZCAL.COM
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