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Bug Fixes

pull/199/head
Wayne Warthen 5 years ago
parent
78b668687d
commit
a1a25465da
14 changed files with 107 additions and 97 deletions
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  1. 33
      Source/Apps/RTC.asm
  2. 17
      Source/Apps/Tune/Tune.asm
  3. 3
      Source/HBIOS/Config/RCZ280_nat_zz.asm
  4. 2
      Source/HBIOS/cfg_dyno.asm
  5. 2
      Source/HBIOS/cfg_master.asm
  6. 2
      Source/HBIOS/cfg_mk4.asm
  7. 2
      Source/HBIOS/cfg_rcz180.asm
  8. 2
      Source/HBIOS/cfg_rcz280.asm
  9. 2
      Source/HBIOS/cfg_scz180.asm
  10. 16
      Source/HBIOS/dbgmon.asm
  11. 56
      Source/HBIOS/hbios.asm
  12. 19
      Source/HBIOS/util.asm
  13. 2
      Source/ver.inc
  14. 2
      Source/ver.lib

33
Source/Apps/RTC.asm
View File

@ -39,8 +39,11 @@ PORT_N8 .EQU $88 ; RTC port for N8
PORT_MK4 .EQU $8A ; RTC port for MK4
PORT_RCZ80 .EQU $C0 ; RTC port for RC2014
PORT_RCZ180 .EQU $0C ; RTC port for RC2014
PORT_SCZ180 .EQU $0C ; RTC port for SBCZ180
PORT_EZZ80 .EQU $C0 ; RTC port for EZZ80 (actually does not have one!!!)
PORT_SCZ180 .EQU $0C ; RTC port for SCZ180
PORT_DYNO .EQU $0C ; RTC port for DYNO
PORT_RCZ280 .EQU $C0 ; RTC port for RCZ280
BDOS .EQU 5 ; BDOS invocation vector
FCB .EQU 05CH ; Start of command line
@ -1075,30 +1078,46 @@ HINIT:
JR Z,RTC_INIT2
CP $03 ; ZETA 2
JR Z,RTC_INIT2
;
LD C,PORT_N8
LD DE,PLT_N8
CP $04 ; N8
JR Z,RTC_INIT2
;
LD C,PORT_MK4
LD DE,PLT_MK4
CP $05 ; Mark IV
JR Z,RTC_INIT2
;
LD C,PORT_RCZ80
LD DE,PLT_RCZ80
CP $07 ; RC2014 w/ Z80
JR Z,RTC_INIT2
;
LD C,PORT_RCZ180
LD DE,PLT_RCZ180
CP $08 ; RC2014 w/ Z180
JR Z,RTC_INIT2
;
LD C,PORT_EZZ80
LD DE,PLT_EZZ80
CP $09 ; Easy Z80
JR Z,RTC_INIT2
;
LD C,PORT_SCZ180
LD DE,PLT_SCZ180
CP $0A ; SCZ180
JR Z,RTC_INIT2
;LD C,PORT_EZZ80
;LD DE,PLT_EZZ80
;CP $09 ; Easy Z80
;JR Z,RTC_INIT2
;
LD C,PORT_DYNO
LD DE,PLT_DYNO
CP 11 ; DYNO
JR Z,RTC_INIT2
;
LD C,PORT_RCZ280
LD DE,PLT_RCZ280
CP 12 ; RCZ280
JR Z,RTC_INIT2
;
; Unknown platform
LD DE,PLTERR ; BIOS error message
@ -1719,8 +1738,10 @@ PLT_N8 .TEXT ", N8 RTC Latch Port 0x88\r\n$"
PLT_MK4 .TEXT ", Mark 4 RTC Latch Port 0x8A\r\n$"
PLT_RCZ80 .TEXT ", RC2014 Z80 RTC Module Latch Port 0xC0\r\n$"
PLT_RCZ180 .TEXT ", RC2014 Z180 RTC Module Latch Port 0x0C\r\n$"
PLT_SCZ180 .TEXT ", SC Z180 RTC Module Latch Port 0x0C\r\n$"
PLT_EZZ80 .TEXT ", Easy Z80 RTC Module Latch Port 0xC0\r\n$"
PLT_SCZ180 .TEXT ", SC Z180 RTC Module Latch Port 0x0C\r\n$"
PLT_DYNO .TEXT ", DYNO RTC Module Latch Port 0x0C\r\n$"
PLT_RCZ280 .TEXT ", RC2014 Z280 RTC Module Latch Port 0xC0\r\n$"
;
; Generic FOR-NEXT loop algorithm

17
Source/Apps/Tune/Tune.asm
View File

@ -64,8 +64,8 @@ TYPMYM .EQU 3 ; FILTYP value for MYM sound file
;
; HIGH SPEED CPU CONTROL
;
SBCV2004 .EQU 0 ; USE SBC-V2-004 HALF CLOCK DIVIDER
CPUFAMZ180 .EQU 1 ; USE Z180 WAIT STATE MANAGEMENT
SBCV2004 .EQU 0 ; ENABLE SBC-V2-004 HALF CLOCK DIVIDER
CPUFAMZ180 .EQU 1 ; ENABLE Z180 WAIT STATE MANAGEMENT
;
;Conditional assembly - use -D switch on TASM or uz80as assembler to control
_ZX .EQU 0 ; 1) Version of ROUT (ZX or MSX standards)
@ -596,6 +596,15 @@ CFGTBL: ; PLT RSEL RDAT RIN Z180 ACR
;
.DB $0A, $61, $60, $60, $C0, $FF ; SCZ180 W/ RC SOUND MODULE (MF)
.DW HWSTR_RCMF
;
.DB $0B, $D8, $D0, $D8, $FF, $FF ; RCZ280 W/ RC SOUND MODULE (EB)
.DW HWSTR_RCEB
;
.DB $0B, $A0, $A1, $A2, $FF, $FF ; RCZ280 W/ RC SOUND MODULE (EB Rev 6)
.DW HWSTR_RCEB6
;
.DB $0B, $D1, $D0, $D0, $FF, $FF ; RCZ280 W/ RC SOUND MODULE (MF)
.DW HWSTR_RCMF
;
.DB $FF ; END OF TABLE MARKER
;
@ -2478,10 +2487,6 @@ upsg:
ERRWITHMSG(MSGERR)
upsg0:
ld a,(WMOD) ; if WMOD = 1, CPU is z180
or a ; set flags
jr z,upsg1 ; skip z180 stuff
di
call SLOWIO

3
Source/HBIOS/Config/RCZ280_nat_zz.asm
View File

@ -26,4 +26,5 @@
;
#include "Config/RCZ280_nat.asm"
;
RAMLOC .SET 23 ; START OF RAM AS POWER OF 2 (2^N)
RAMLOC .SET 23 ; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
RAMBIAS .SET (1 << (RAMLOC - 10)) ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE

2
Source/HBIOS/cfg_dyno.asm
View File

@ -29,8 +29,8 @@ DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
MEMMGR .EQU MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
RAMBIAS .EQU 512 ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
RAMLOC .EQU 19 ; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
RAMBIAS .EQU (1 << (RAMLOC - 10)) ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
MPGSEL_1 .EQU $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)

2
Source/HBIOS/cfg_master.asm
View File

@ -26,8 +26,8 @@ DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
MEMMGR .SET MM_NONE ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
RAMBIAS .EQU 0 ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
RAMLOC .EQU 19 ; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
RAMBIAS .EQU (1 << (RAMLOC - 10)) ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
MPCL_RAM .EQU $78 ; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
MPCL_ROM .EQU $7C ; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)

2
Source/HBIOS/cfg_mk4.asm
View File

@ -29,8 +29,8 @@ DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
MEMMGR .EQU MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
RAMBIAS .EQU 512 ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
RAMLOC .EQU 19 ; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
RAMBIAS .EQU (1 << (RAMLOC - 10)) ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
;
Z180_BASE .EQU $40 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
Z180_CLKDIV .EQU 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2

2
Source/HBIOS/cfg_rcz180.asm
View File

@ -29,8 +29,8 @@ DEFSERCFG .EQU SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
MEMMGR .EQU MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
RAMBIAS .EQU 512 ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
RAMLOC .EQU 19 ; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
RAMBIAS .EQU (1 << (RAMLOC - 10)) ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
MPGSEL_1 .EQU $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)

2
Source/HBIOS/cfg_rcz280.asm
View File

@ -29,8 +29,8 @@ DEFSERCFG .EQU SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
MEMMGR .EQU MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
RAMBIAS .EQU 512 ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
RAMLOC .EQU 19 ; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
RAMBIAS .EQU (1 << (RAMLOC - 10)) ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
MPGSEL_1 .EQU $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)

2
Source/HBIOS/cfg_scz180.asm
View File

@ -29,8 +29,8 @@ DEFSERCFG .EQU SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
MEMMGR .EQU MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
RAMBIAS .EQU 512 ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
RAMLOC .EQU 19 ; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
RAMBIAS .EQU (1 << (RAMLOC - 10)) ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
;
Z180_BASE .EQU $C0 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
Z180_CLKDIV .EQU 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2

16
Source/HBIOS/dbgmon.asm
View File

@ -44,7 +44,7 @@ BUFLEN .EQU 40 ; INPUT LINE LENGTH
;
UART_ENTRY:
LD SP,MON_STACK ; SET THE STACK POINTER
EI ; INTS OK NOW
;EI ; INTS OK NOW
LD HL,UART_ENTRY ; RESTART ADDRESS
CALL INITIALIZE ; INITIALIZE SYSTEM
@ -132,10 +132,14 @@ INITIALIZE:
LD (9),HL ; STORE AT 0x0009
#ENDIF
;#IF (BIOS == BIOS_WBW)
; CALL DELAY_INIT
;#ENDIF
#IF DSKYENABLE
LD B,BF_SYSGET ; HBIOS FUNC=GET SYS INFO
LD C,BF_SYSGET_CPUINFO ; HBIOS SUBFUNC=GET CPU INFO
RST 08 ; CALL HBIOS
LD A,L ; PUT SPEED IN MHZ IN ACCUM
CALL DELAY_INIT
#ENDIF
;
RET
;
;__BOOT_______________________________________________________________________
@ -962,7 +966,7 @@ KY_PW .EQU KY_BK ; USE [BW] FOR [PW] (PORT WRITE)
;
DSKY_ENTRY:
LD SP,MON_STACK ; SET THE STACK POINTER
EI ; INTS OK NOW
;EI ; INTS OK NOW
LD HL,DSKY_ENTRY ; RESTART ADDRESS
CALL INITIALIZE
;

56
Source/HBIOS/hbios.asm
View File

@ -64,10 +64,6 @@
; - dsky.asm
; - unlzsa2s.asm
;
; TODO:
; - DELAY_INIT MAKES A SYSTEM CALL VIA RST 08 EARLIER THAN
; WE REALLY EXPECT SYSTEM CALLS TO HAPPEN
;
; INCLUDE GENERIC STUFF
;
#INCLUDE "std.asm"
@ -563,7 +559,7 @@ HBX_BC_SP .EQU $ - 2 ; ... TO ORIGINAL VALUE
#ELSE
POP AF
JP PO,$+4
HB_EI
EI ; *** DO NOT USE HB_EI HERE ***
#ENDIF
RET
;
@ -1060,14 +1056,14 @@ Z280_BOOTPDRTBL:
.DW ($006 << 4) | $A
.DW ($007 << 4) | $A
; UPPER 32 K (COMMON)
.DW (($78 + (1 << (RAMLOC - 12))) << 4) | $A
.DW (($79 + (1 << (RAMLOC - 12))) << 4) | $A
.DW (($7A + (1 << (RAMLOC - 12))) << 4) | $A
.DW (($7B + (1 << (RAMLOC - 12))) << 4) | $A
.DW (($7C + (1 << (RAMLOC - 12))) << 4) | $A
.DW (($7D + (1 << (RAMLOC - 12))) << 4) | $A
.DW (($7E + (1 << (RAMLOC - 12))) << 4) | $A
.DW (($7F + (1 << (RAMLOC - 12))) << 4) | $A
.DW (((((BID_COM & $7F) * 8) + 0) + (1 << (RAMLOC - 12))) << 4) | $A
.DW (((((BID_COM & $7F) * 8) + 1) + (1 << (RAMLOC - 12))) << 4) | $A
.DW (((((BID_COM & $7F) * 8) + 2) + (1 << (RAMLOC - 12))) << 4) | $A
.DW (((((BID_COM & $7F) * 8) + 3) + (1 << (RAMLOC - 12))) << 4) | $A
.DW (((((BID_COM & $7F) * 8) + 4) + (1 << (RAMLOC - 12))) << 4) | $A
.DW (((((BID_COM & $7F) * 8) + 5) + (1 << (RAMLOC - 12))) << 4) | $A
.DW (((((BID_COM & $7F) * 8) + 6) + (1 << (RAMLOC - 12))) << 4) | $A
.DW (((((BID_COM & $7F) * 8) + 7) + (1 << (RAMLOC - 12))) << 4) | $A
;
Z280_INITZ:
;
@ -1125,7 +1121,7 @@ Z280_INITZ:
;#ENDIF
LD A,(RAMSIZE + RAMBIAS - 64) >> 2
OUT0 (Z180_CBR),A ; COMMON BASE = LAST (TOP) BANK
;
; SET DEFAULT CSIO SPEED (INTERNAL CLOCK, SLOW AS POSSIBLE)
LD A,Z180_CNTR_DEF ; DIV 1280, 14KHZ @ 18MHZ CLK
OUT0 (Z180_CNTR),A
@ -1168,6 +1164,8 @@ Z280_INITZ:
;
DIAG(%00000011)
LED($00)
; ok
;
; CHECK BATTERY BACKUP STATUS BEFORE WE COPY PROXY TO UPPER MEMORY
;
@ -1362,7 +1360,7 @@ SAVE_REC_M:
CALL MIO_INIT ; WE GET TO BOOT MESSAGE
#ENDIF
;
#IF 0
#IF FALSE
;
; TEST DEBUG ***************************************************************************************
;
@ -1492,7 +1490,8 @@ HB_CPU2:
;
CALL HB_CPUSPD ; CPU SPEED DETECTION
;
CALL DELAY_INIT ; INITIALIZE SPEED COMPENSATED DELAY FUNCTIONS
LD A,(CB_CPUMHZ) ; CPU SPEED TO ACCUM AND INIT
CALL DELAY_INIT ; .. SPEED COMPENSATED DELAY
;
#IF (CPUFAM == CPU_Z180)
;
@ -1658,7 +1657,7 @@ Z280_TC .EQU CPUOSC / 4 / 50 / 2 ; TIME CONSTANT
CALL FILL ; DO IT
;
DIAG(%00111111)
#IF 0
#IF FALSE
;
; TEST DEBUG ***************************************************************************************
;
@ -1702,7 +1701,7 @@ NOT_REC_M0:
#ENDIF
CALL CALLLIST ; PROCESS THE PRE-INIT CALL TABLE
;
#IF 0
#IF FALSE
;
; TEST DEBUG ***************************************************************************************
;
@ -1741,7 +1740,7 @@ NXTMIO: LD A,(HL)
; CALL WRITESTR ; WRITESTR WILL WORK WILL ONLY PRINT UP TO FIRST $
#ENDIF
;
#IF 0
#IF FALSE
;
; TEST DEBUG ***************************************************************************************
;
@ -1771,7 +1770,7 @@ NXTMIO: LD A,(HL)
;
; IO PORT SCAN
;
#IF 0
#IF FALSE
PSCN:
LD C,0 ; IO PORT NUMBER
LD B,0 ; LOOP COUNTER
@ -1798,7 +1797,7 @@ PSCNX .EQU $ + 1
DJNZ PSCN1
#ENDIF
;
#IF 0
#IF FALSE
HB_SPDTST:
CALL HB_CPUSPD ; CPU SPEED DETECTION
CALL NEWLINE
@ -2355,7 +2354,7 @@ HB_DISPATCH:
#ENDIF
;
;
#IF 0 ; *DEBUG* START
#IF FALSE ; *DEBUG* START
;
CALL HB_DISPATCH1 ; DO THE WORK
;
@ -2461,7 +2460,7 @@ CIO_TBL .FILL CIO_SIZ,0 ; SPACE FOR ENTRIES
;
DIO_DISPATCH:
;
#IF 0 ; *DEBUG* START
#IF FALSE ; *DEBUG* START
;
; DUMP INCOMING CALL
CALL NEWLINE
@ -3374,7 +3373,7 @@ SYS_PEEK:
#ELSE
POP AF ; RECALL INITIAL INTERRUPT STATUS
JP PO,$+4 ; RETURN TO INITIAL STATE
HB_EI
EI ; *** DO NOT USE HB_EI HERE ***
#ENDIF
#ENDIF
XOR A
@ -3411,7 +3410,7 @@ SYS_POKE:
#ELSE
POP AF ; RECALL INITIAL INTERRUPT STATUS
JP PO,$+4 ; RETURN TO INITIAL STATE
HB_EI
EI ; *** DO NOT USE HB_EI HERE ***
#ENDIF
#ENDIF
XOR A
@ -3617,7 +3616,7 @@ Z280_TIMINT:
;
;
HB_TIMINT:
#IF 0 ; *DEBUG*
#IF FALSE ; *DEBUG*
LD HL,HB_TIMDBGCNT
INC (HL)
LD A,(HL)
@ -3673,7 +3672,7 @@ HB_SECOND:
;
HB_BADINT:
#IF 0 ; *DEBUG*
#IF FALSE ; *DEBUG*
LD HL,HB_BADINTCNT
INC (HL)
LD A,(HL)
@ -4158,8 +4157,6 @@ Z280_BNKSEL:
; PDR: R000 0BBB B000 1010 (RC2014)
; PDR: 0000 RBBB B000 1010 (ZZ80MB)
;
;MULTU A,$80 ; HL=0R00 0BBB B000 0000
;.DB $FD,$ED,$F9,$80 ; MULTU A,$80
MULTU A,$80 ; HL=0R00 0BBB B000 0000
BIT 6,H ; RAM BIT SET?
JR Z,Z280_BNKSEL2 ; IF NOT, ALL DONE
@ -5321,7 +5318,6 @@ PS_SOUND:
LD E,BF_SNDQ_DEV
RST 08
LD A,B
;DEC A
RLCA
RLCA
RLCA

19
Source/HBIOS/util.asm
View File

@ -643,26 +643,9 @@ LDELAY:
RET
;
; INITIALIZE DELAY SCALER BASED ON OPERATING CPU SPEED
; HBIOS *MUST* BE INSTALLED AND AVAILABLE VIA RST 8!!!
; CPU SCALER := MAX(1, (PHIMHZ - 2))
; ENTER WITH A = CPU SPEED IN MHZ
;
DELAY_INIT:
#IF (BIOS == BIOS_UNA)
LD C,$F8 ; UNA BIOS GET PHI FUNCTION
RST 08 ; RETURNS SPEED IN HZ IN DE:HL
LD B,4 ; DIVIDE MHZ IN DE:HL BY 100000H
DELAY_INIT0:
SRL D ; ... TO GET APPROX CPU SPEED IN
RR E ; ...MHZ. THROW AWAY HL, AND
DJNZ DELAY_INIT0 ; ...RIGHT SHIFT DE BY 4.
INC E ; FIX UP FOR VALUE TRUNCATION
LD A,E ; PUT IN A
#ELSE
LD B,BF_SYSGET ; HBIOS FUNC=GET SYS INFO
LD C,BF_SYSGET_CPUINFO ; HBIOS SUBFUNC=GET CPU INFO
RST 08 ; CALL HBIOS, RST 08 NOT YET INSTALLED
LD A,L ; PUT SPEED IN MHZ IN ACCUM
#ENDIF
CP 3 ; TEST FOR <= 2 (SPECIAL HANDLING)
JR C,DELAY_INIT1 ; IF <= 2, SPECIAL PROCESSING
SUB 2 ; ADJUST AS REQUIRED BY DELAY FUNCTIONS

2
Source/ver.inc
View File

@ -2,4 +2,4 @@
#DEFINE RMN 1
#DEFINE RUP 1
#DEFINE RTP 0
#DEFINE BIOSVER "3.1.1-pre.49"
#DEFINE BIOSVER "3.1.1-pre.50"

2
Source/ver.lib
View File

@ -3,5 +3,5 @@ rmn equ 1
rup equ 1
rtp equ 0
biosver macro
db "3.1.1-pre.49"
db "3.1.1-pre.50"
endm

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