MirrorRepos
/
RomWBW
mirror of https://github.com/wwarthen/RomWBW.git
1
0
Fork 1
Code Issues Projects Releases Wiki Activity
Browse Source

EaZy80-512 & K80W Fixes 

Minor fixes from Bill Shen.
pull/491/head
Wayne Warthen 1 year ago
parent
f50ae14f9e
commit
a27f2479af
4 changed files with 28 additions and 13 deletions
Whitespace
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
Split View
Diff Options
Show Stats Download Patch File Download Diff File
  1. 16
      Source/HBIOS/Config/RCZ80_ez512_std.asm
  2. 2
      Source/HBIOS/Config/SBC_std.asm
  3. 5
      Source/HBIOS/kio.asm
  4. 16
      Source/HBIOS/sd.asm

16
Source/HBIOS/Config/RCZ80_ez512_std.asm
View File

@ -59,20 +59,20 @@ KIOBASE .SET $00 ; KIO BASE I/O ADDRESS
RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
ROMSIZE .SET 0 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
MEMMGR .SET MM_EZ512 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON|EZ512]
FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS
FPSW_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL SWITCHES
FPLED_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL LEDS
FPSW_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL SWITCHES
CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
;
CTCENABLE .SET TRUE ; ENABLE ZILOG CTC SUPPORT
CTCBASE .SET KIOBASE+$04 ; CTC BASE I/O ADDRESS
CTCTIMER .SET TRUE ; ENABLE CTC PERIODIC TIMER
CTCOSC .SET 3686400 ; CTC CLOCK FREQUENCY
CTCOSC .SET 1843200 ; CTC CLOCK FREQUENCY
;
DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
;
UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
ACIAENABLE .SET TRUE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
UARTENABLE .SET FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
;
SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
SIOCNT .SET 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
@ -87,12 +87,14 @@ TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
VRCENABLE .SET TRUE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
;
MDROM .SET FALSE ; MD: ENABLE ROM DISK
;
FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
CHENABLE .SET FALSE ; CH: ENABLE CH375/376 USB SUPPORT
;
FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
;
IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)

2
Source/HBIOS/Config/SBC_std.asm
View File

@ -50,7 +50,7 @@
CPUOSC .SET 8000000 ; CPU OSC FREQ IN MHZ
INTMODE .SET 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
VDAEMU_SERKBD .SET 0 ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
;
UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)

5
Source/HBIOS/kio.asm
View File

@ -37,9 +37,14 @@ KIO_PREINIT:
; RECORD PRESENCE
LD A,$FF
LD (KIO_EXISTS),A
;HCS initialize KIO if NOT EZ512
;HCS do not write to KIO command register, if EZ512
;HCS because it is already done in monitor and will upset the bank register
#IF (SDMODE != SDMODE_EZ512) ; Z80 PIO ON EAZY80-512
; INITIALIZE KIO
LD A,%11111001 ; RESET ALL DEVICES, SET DAISYCHAIN
OUT (KIO_KIOCMD),A ; DO IT
#ENDIF
;
XOR A
RET

16
Source/HBIOS/sd.asm
View File

@ -741,6 +741,14 @@ SD_INIT:
LD A,SD_IOBASE
CALL PRTHEXBYTE
#ENDIF
;
#IF (SDMODE == SDMODE_K80W)
PRTS(" MODE=K80W$")
PRTS(" IO=0x$")
LD A,SD_IOBASE
CALL PRTHEXBYTE
#ENDIF
;
CALL SD_PROBE ; CHECK FOR HARDWARE
JR Z,SD_INIT00 ; CONTINUE IF PRESENT
@ -1985,7 +1993,7 @@ SD_SETUP:
OUT (SD_OPRREG),A ; OPRREG == SIO_MCR
#ENDIF
;
#IF (SDMODE == SDMODE_PIO)
#IF ((SDMODE == SDMODE_PIO) | (SDMODE == SDMODE_EZ512) | (SDMODE == SDMODE_K80W))
LD A,SD_OPRDEF ; All output bits high
LD (SD_OPRVAL),A ; WBW
OUT (SD_OPRREG),A
@ -2247,7 +2255,7 @@ SD_PUT:
OUT (SD_IOCLK),A
#ENDIF
;
#IF ((SDMODE == SDMODE_JUHA) | (SDMODE == SDMODE_N8) | (SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_UART) | (SDMODE == SDMODE_DSD) | (SDMODE == SDMODE_USR) | (SDMODE == SDMODE_PIO))
#IF ((SDMODE == SDMODE_JUHA) | (SDMODE == SDMODE_N8) | (SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_UART) | (SDMODE == SDMODE_DSD) | (SDMODE == SDMODE_USR) | (SDMODE == SDMODE_PIO) | (SDMODE == SDMODE_EZ512) | (SDMODE == SDMODE_K80W))
#IF (SDMODE == SDMODE_UART)
XOR $FF ; DI IS INVERTED ON UART
#ENDIF
@ -2347,14 +2355,14 @@ SD_GET:
POP DE
#ENDIF
;
#IF ((SDMODE == SDMODE_JUHA) | (SDMODE == SDMODE_N8) | (SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_UART) | (SDMODE == SDMODE_DSD) | (SDMODE == SDMODE_USR) | (SDMODE == SDMODE_PIO))
#IF ((SDMODE == SDMODE_JUHA) | (SDMODE == SDMODE_N8) | (SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_UART) | (SDMODE == SDMODE_DSD) | (SDMODE == SDMODE_USR) | (SDMODE == SDMODE_PIO) | (SDMODE == SDMODE_EZ512) | (SDMODE == SDMODE_K80W))
LD B,8 ; RECEIVE 8 BITS (LOOP 8 TIMES)
LD A,(SD_OPRVAL) ; LOAD CURRENT OPR VALUE
SD_GET1:
XOR SD_CLK ; TOGGLE CLOCK
OUT (SD_OPRREG),A ; UPDATE CLOCK
IN A,(SD_INPREG) ; READ THE DATA WHILE CLOCK IS ACTIVE
#IF ((SDMODE == SDMODE_JUHA) | (SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_PIO))
#IF ((SDMODE == SDMODE_JUHA) | (SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_PIO) | (SDMODE == SDMODE_EZ512) | (SDMODE == SDMODE_K80W))
RLA ; ROTATE INP:7 INTO CF
#ENDIF
#IF (SDMODE == SDMODE_N8)

Write Preview
Loading…
Cancel
Save