reorganize test applications. Improve dmamon

linux build to be fixed yet
4 years ago · abee120b4e
38 changed files with 2924 additions and 12 deletions
--- a/Source/Apps/Build.cmd
+++ b/Source/Apps/Build.cmd
@ -19,10 +19,7 @@ call :asm talk || exit /b
 call :asm mode || exit /b
 call :asm rtc || exit /b
 call :asm timer || exit /b
-call :asm180 inttest || exit /b
 call :asm rtchb || exit /b
-call :asm ppidetst || exit /b
-call :asm tstdskng || exit /b

 zx Z80ASM -SYSGEN/F || exit /b

@ -34,7 +31,7 @@ pushd FDU && call Build || exit /b & popd
 pushd Tune && call Build || exit /b & popd
 pushd FAT && call Build || exit /b & popd
 pushd I2C && call Build || exit /b & popd
-pushd ramtest && call Build || exit /b & popd
+pushd TEST && call Build || exit /b & popd
 pushd ZMP && call Build || exit /b & popd

 copy *.com %APPBIN%\ || exit /b
--- a/Source/Apps/Clean.cmd
+++ b/Source/Apps/Clean.cmd
@ -12,5 +12,5 @@ pushd FDU && call Clean || exit /b 1 & popd
 pushd Tune && call Clean || exit /b 1 & popd
 pushd FAT && call Clean || exit /b 1 & popd
 pushd I2C && call Clean || exit /b 1 & popd
-pushd ramtest && call Clean || exit /b 1 & popd
+pushd TEST && call Clean || exit /b 1 & popd
 pushd ZMP && call Clean || exit /b 1 & popd
--- a/Source/Apps/TEST/Build.cmd
+++ b/Source/Apps/TEST/Build.cmd
@ -0,0 +1,33 @@
+@echo off
+setlocal
+
+set TOOLS=../../../Tools
+set APPBIN=..\..\Binary\Apps
+
+set PATH=%TOOLS%\tasm32;%TOOLS%\zx;%PATH%
+
+set TASMTABS=%TOOLS%\tasm32
+
+set ZXBINDIR=%TOOLS%/cpm/bin/
+set ZXLIBDIR=%TOOLS%/cpm/lib/
+set ZXINCDIR=%TOOLS%/cpm/include/
+
+pushd DMAmon && call Build || exit /b & popd
+pushd dskyng && call Build || exit /b & popd
+pushd inttst && call Build || exit /b & popd
+pushd ppidetst && call Build || exit /b & popd
+pushd ramtest && call Build || exit /b & popd
+
+goto :eof
+
+:asm
+echo.
+echo Building %1...
+tasm -t80 -g3 -fFF %1.asm %1.com %1.lst || exit /b
+goto :eof
+
+:asm180
+echo.
+echo Building %1...
+tasm -t180 -g3 -fFF %1.asm %1.com %1.lst || exit /b
+goto :eof
--- a/Source/Apps/TEST/Clean.cmd
+++ b/Source/Apps/TEST/Clean.cmd
@ -0,0 +1,14 @@
+@echo off
+setlocal
+
+if exist *.bin del *.bin
+if exist *.com del *.com
+if exist *.lst del *.lst
+if exist *.hex del *.hex
+if exist *.prn del *.prn
+
+pushd DMAmon && call Clean || exit /b 1 & popd
+pushd dskyng && call Clean || exit /b 1 & popd
+pushd inttst && call Clean || exit /b 1 & popd
+pushd ppidetst && call Clean || exit /b 1 & popd
+pushd ramtest && call Clean || exit /b 1 & popd
--- a/Source/Apps/TEST/DMAmon/Build.cmd
+++ b/Source/Apps/TEST/DMAmon/Build.cmd
@ -0,0 +1,11 @@
+@echo off
+setlocal
+
+set TOOLS=../../../../Tools
+set PATH=%TOOLS%\tasm32;%PATH%
+set TASMTABS=%TOOLS%\tasm32
+
+tasm -t180 -g3 -fFF dmamon.asm dmamon.com dmamon.lst || exit /b
+
+copy /Y dmamon.com ..\..\..\..\Binary\Apps\ || exit /b
+
--- a/Source/Apps/TEST/DMAmon/Clean.cmd
+++ b/Source/Apps/TEST/DMAmon/Clean.cmd
@ -0,0 +1,6 @@
+@echo off
+setlocal
+
+if exist *.com del *.com
+if exist *.lst del *.lst
+if exist *.bin del *.bin
--- a/Source/Apps/TEST/DMAmon/MBC_std.asm
+++ b/Source/Apps/TEST/DMAmon/MBC_std.asm
@ -0,0 +1,41 @@
+;
+;==================================================================================================
+;   MBC CONFIGURATION
+;==================================================================================================
+;
+; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
+; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
+; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
+; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
+; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
+; YOUR FILE IN THE BUILD PROCESS.
+;
+; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
+; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
+; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
+; SETTINGS.
+;
+; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
+; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
+; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
+; DIRECTORIES ABOVE THIS ONE).
+;
+#DEFINE PLATFORM_NAME "Multi Board Computer"
+#DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
+;
+#include "cfg_mbc.asm"
+;
+BATCOND		.SET	FALSE
+;
+FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+;
+PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+;
+DSKYENABLE	.SET	FALSE		; ENABLES DSKY
+DSKYMODE	.SET	DSKYMODE_NG	; DSKY VERTSION: DSKYMODE_[V1|NG]
+;
+DMAENABLE	.SET	TRUE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+DMABASE		.SET	$E0		; DMA: DMA BASE ADDRESS
+DMAMODE		.SET	DMAMODE_MBC	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC)
--- a/Source/Apps/TEST/DMAmon/Readme.txt
+++ b/Source/Apps/TEST/DMAmon/Readme.txt
--- a/Source/Apps/TEST/DMAmon/build.inc
+++ b/Source/Apps/TEST/DMAmon/build.inc
@ -0,0 +1,8 @@
+; RomWBW Configured for MBC std, 2021-09-03T14:52:50
+;
+#DEFINE		TIMESTAMP	"2021-09-03"
+;
+ROMSIZE		.EQU		512
+;
+#INCLUDE "MBC_std.asm"
+;
--- a/Source/Apps/TEST/DMAmon/cfg_mbc.asm
+++ b/Source/Apps/TEST/DMAmon/cfg_mbc.asm
@ -0,0 +1,235 @@
+;
+;==================================================================================================
+;   ROMWBW 2.X CONFIGURATION DEFAULTS FOR MBC
+;==================================================================================================
+;
+; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD, YOU SHOULD
+; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
+; UNDER THIS DIRECTORY.
+;
+; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
+; FOR THE PLATFORM.
+;
+#DEFINE PLATFORM_NAME "Multi Board Computer"
+;
+PLATFORM	.EQU	PLT_MBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
+CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
+BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
+BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
+HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
+USELZSA2	.EQU	TRUE		; ENABLE FONT COMPRESSION
+TICKFREQ	.EQU	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
+;
+BOOT_TIMEOUT	.EQU	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
+;
+CPUOSC		.EQU	8000000		; CPU OSC FREQ IN MHZ
+INTMODE		.EQU	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
+DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+;
+RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+RAM_RESERVE	.EQU	0		; RESERVE FIRST N KB OF RAM (USUALLY 0)
+ROM_RESERVE	.EQU	0		; RESERVE FIRST N KB OR ROM (USUALLY 0)
+MEMMGR		.EQU	MM_MBC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
+MPCL_RAM	.EQU	$78		; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
+MPCL_ROM	.EQU	$7C		; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
+;
+RTCIO		.EQU	$70		; RTC LATCH REGISTER ADR
+;
+KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT
+KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
+;
+CTCENABLE	.EQU	FALSE		; ENABLE ZILOG CTC SUPPORT
+CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
+CTCBASE		.EQU	$B0		; CTC BASE I/O ADDRESS
+CTCTIMER	.EQU	TRUE		; ENABLE CTC PERIODIC TIMER
+CTCMODE		.EQU	CTCMODE_CTR	; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
+CTCPRE		.EQU	256		; PRESCALE CONSTANT (1-256)
+CTCPRECH	.EQU	2		; PRESCALE CHANNEL (0-3)
+CTCTIMCH	.EQU	3		; TIMER CHANNEL (0-3)
+CTCOSC		.EQU	614400		; CTC CLOCK FREQUENCY
+;
+EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
+;
+SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
+;
+WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
+;
+DIAGENABLE	.EQU	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
+DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
+DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
+;
+LEDENABLE	.EQU	TRUE		; ENABLES STATUS LED
+LEDMODE		.EQU	LEDMODE_RTC	; LEDMODE_[STD|RTC]
+LEDPORT		.EQU	RTCIO		; STATUS LED PORT ADDRESS
+LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
+;
+DSKYENABLE	.EQU	FALSE		; ENABLES DSKY
+DSKYMODE	.EQU	DSKYMODE_V1	; DSKY VERSION: DSKYMODE_[V1|NG]
+DSKYPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF DSKY PPI
+DSKYOSC		.EQU	3000000		; OSCILLATOR FREQ FOR DSKYNG (IN HZ)
+;
+BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
+CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
+ANSITRACE	.EQU	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKTRACE	.EQU	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+KBDTRACE	.EQU	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKKBLOUT	.EQU	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
+KBDKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+MKYENABLE	.EQU	FALSE		; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
+MKYKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+;
+DSRTCENABLE	.EQU	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
+DSRTCCHG	.EQU	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
+;
+BQRTCENABLE	.EQU	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
+BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
+;
+INTRTCENABLE	.EQU	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
+;
+RP5RTCENABLE	.EQU	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+;
+HTIMENABLE	.EQU	FALSE		; ENABLE SIMH TIMER SUPPORT
+SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
+;
+DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
+DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
+;
+DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
+;
+UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
+UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
+UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
+UARTSBC		.EQU	TRUE		; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
+UARTCAS		.EQU	TRUE		; UART: AUTO-DETECT ECB CASSETTE UART
+UARTMFP		.EQU	TRUE		; UART: AUTO-DETECT MF/PIC UART
+UART4		.EQU	TRUE		; UART: AUTO-DETECT 4UART UART
+UARTRC		.EQU	FALSE		; UART: AUTO-DETECT RC UART
+;
+ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+;
+Z2UENABLE	.EQU	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
+;
+ACIAENABLE	.EQU	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+;
+SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
+SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
+SIOCNT		.EQU	1		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIO0MODE	.EQU	SIOMODE_ZP	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
+SIO0BASE	.EQU	$B0		; SIO 0: REGISTERS BASE ADR
+SIO0ACLK	.EQU	(4915200/8)	; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0ACFG	.EQU	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
+SIO0ACTCC	.EQU	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO0BCLK	.EQU	(4915200/8)	; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0BCFG	.EQU	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
+SIO0BCTCC	.EQU	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+;
+XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
+;
+VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
+VDUSIZ		.EQU	V80X25		; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30]
+CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
+NECENABLE	.EQU	FALSE		; NEC: ENABLE NEC UPD7220 VIDEO/KBD DRIVER (NEC.ASM)
+TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSMODE		.EQU	TMSMODE_SCG	; TMS: DRIVER MODE: TMSMODE_[SCG/N8/RC/RCV9958]
+TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
+VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
+VGASIZ		.EQU	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
+;
+MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
+MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
+MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
+MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM 
+;
+;
+FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE		.EQU	FDMODE_MBC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
+FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
+FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
+FDMEDIA		.EQU	FDM144		; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
+FDMEDIAALT	.EQU	FDM720		; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
+FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+;
+RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
+RFCNT		.EQU	1		; RF: NUMBER OF RAM FLOPPY UNITS (1-4)
+;
+IDEENABLE	.EQU	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+IDETRACE	.EQU	1		; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IDECNT		.EQU	1		; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
+IDE0MODE	.EQU	IDEMODE_DIO	; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE0BASE	.EQU	$20		; IDE 0: IO BASE ADDRESS
+IDE0DATLO	.EQU	$20		; IDE 0: DATA LO PORT FOR 16-BIT I/O
+IDE0DATHI	.EQU	$28		; IDE 0: DATA HI PORT FOR 16-BIT I/O
+IDE0A8BIT	.EQU	FALSE		; IDE 0A (MASTER): 8 BIT XFER
+IDE0B8BIT	.EQU	FALSE		; IDE 0B (MASTER): 8 BIT XFER
+IDE1MODE	.EQU	IDEMODE_NONE	; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE1BASE	.EQU	$00		; IDE 1: IO BASE ADDRESS
+IDE1DATLO	.EQU	$00		; IDE 1: DATA LO PORT FOR 16-BIT I/O
+IDE1DATHI	.EQU	$00		; IDE 1: DATA HI PORT FOR 16-BIT I/O
+IDE1A8BIT	.EQU	TRUE		; IDE 1A (MASTER): 8 BIT XFER
+IDE1B8BIT	.EQU	TRUE		; IDE 1B (MASTER): 8 BIT XFER
+IDE2MODE	.EQU	IDEMODE_NONE	; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE2BASE	.EQU	$00		; IDE 2: IO BASE ADDRESS
+IDE2DATLO	.EQU	$00		; IDE 2: DATA LO PORT FOR 16-BIT I/O
+IDE2DATHI	.EQU	$00		; IDE 2: DATA HI PORT FOR 16-BIT I/O
+IDE2A8BIT	.EQU	TRUE		; IDE 2A (MASTER): 8 BIT XFER
+IDE2B8BIT	.EQU	TRUE		; IDE 2B (MASTER): 8 BIT XFER
+;
+PPIDEENABLE	.EQU	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+PPIDETRACE	.EQU	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPIDECNT	.EQU	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
+PPIDE0BASE	.EQU	$60		; PPIDE 0: PPI REGISTERS BASE ADR
+PPIDE0A8BIT	.EQU	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
+PPIDE0B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE1BASE	.EQU	$20		; PPIDE 1: PPI REGISTERS BASE ADR
+PPIDE1A8BIT	.EQU	FALSE		; PPIDE 1A (MASTER): 8 BIT XFER
+PPIDE1B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE2BASE	.EQU	$44		; PPIDE 2: PPI REGISTERS BASE ADR
+PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
+PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+;
+SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDMODE		.EQU	SDMODE_JUHA	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT]
+SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
+SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
+SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+;
+PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
+PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
+PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
+;
+PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
+;
+HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
+HDSKTRACE	.EQU	1		; HDSK: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+;
+PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
+PIO4BASE	.EQU	$90		; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
+PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
+PIOZBASE	.EQU	$88		; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD
+PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
+PIOSBASE	.EQU	$60		; PIO: PIO REGISTERS BASE ADR FOR SBC PPI
+;
+UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
+UFBASE		.EQU	$0C		; UF: REGISTERS BASE ADR
+;
+SN76489ENABLE	.EQU	FALSE		; SN76489 SOUND DRIVER
+AUDIOTRACE	.EQU	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
+SN7CLK		.EQU	CPUOSC / 4	; DEFAULT TO CPUOSC / 4
+;
+AY38910ENABLE	.EQU	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
+AY_CLK		.EQU	CPUOSC / 4	; DEFAULT TO CPUOSC / 4
+AYMODE		.EQU	AYMODE_NONE	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC]
+;
+SPKENABLE	.EQU	TRUE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
+;
+DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
+DMAMODE		.EQU	DMAMODE_NONE	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC)
--- a/Source/Apps/TEST/DMAmon/dmamon.asm
+++ b/Source/Apps/TEST/DMAmon/dmamon.asm
@ -0,0 +1,595 @@
+;==================================================================================================
+; Z80 DMA DRIVER
+;==================================================================================================
+;
+#INCLUDE "std.asm"
+;
+;
+DMA_CONTINUOUS			.equ 	%10111101	; + Pulse
+DMA_BYTE			.equ 	%10011101	; + Pulse
+DMA_BURST 			.equ	%11011101	; + Pulse
+DMA_LOAD			.equ	$cf 		; %11001111
+DMA_ENABLE			.equ	$87		; %10000111
+DMA_FORCE_READY 		.equ 	$b3
+DMA_DISABLE			.equ	$83
+DMA_START_READ_SEQUENCE		.equ	$a7
+DMA_READ_STATUS_BYTE		.equ	$bf
+DMA_READ_MASK_FOLLOWS		.equ	$bb
+DMA_RESET			.equ	$c3
+;DMA_RESET_PORT_A_TIMING	.equ	$c7
+;DMA_RESET_PORT_B_TIMING	.equ	$cb
+;DMA_CONTINUE			.equ	$d3
+;DMA_DISABLE_INTERUPTS		.equ	$af
+;DMA_ENABLE_INTERUPTS		.equ	$ab
+;DMA_RESET_DISABLE_INTERUPTS	.equ 	$a3
+;DMA_ENABLE_AFTER_RETI		.equ	$b7
+;DMA_REINIT_STATUS_BYTE		.equ	$8b
+;
+DMA_FBACK			.equ	TRUE	; ALLOW FALLBACK TO SOFTWARE
+DMA_USEHS			.equ	TRUE	; USE CLOCK DIVIDER
+;
+DMAMODE				.SET	DMAMODE_ECB
+;
+#IF (DMAMODE=DMAMODE_MBC)
+DMA_RDY				.EQU	%00000000
+DMA_FORCE			.EQU	1
+DMA_USEHS			.SET	FALSE
+#ENDIF
+#IF (DMAMODE=DMAMODE_ECB)
+DMA_RDY				.EQU	%00001000
+DMA_FORCE			.EQU	0
+DMA_USEHS			.SET	TRUE
+#ENDIF
+;
+;==================================================================================================
+; MAIN DMA MONITOR ROUTINE
+;==================================================================================================
+;
+	.ORG		$0100
+;
+MAIN:
+	LD	(SAVSTK),SP		; SETUP LOCAL
+	LD	SP,STACK		; STACK
+;
+	call	PRTSTRD			; WELCOME
+	.db	"DMA MONITOR\n\r$"
+;
+MENULP:	CALL	DISPM			; DISPLAY MENU
+	CALL	CIN			; GET SELECTION
+;
+	CP	'D'
+	JP	Z,DMATST_D
+	CP	'I'
+	JP	Z,DMATST_I
+	CP	'M'
+	JP	Z,DMATST_M
+	CP	'R'
+	JP	Z,DMATST_R
+	CP	'Y'
+	JP	Z,DMATST_Y
+	CP	'X'
+	JR	Z,DMABYE
+;
+	JR	MENULP
+;
+DMABYE:	LD	SP,(SAVSTK)		; RESTORE CP/M STACK
+	RET
+;
+DMATST_I:
+	call	PRTSTRD
+	.db	"\n\rSTART DMA_INIT\n\r$"
+	CALL	DMA_INIT
+	JP	MENULP
+;
+DMATST_M:
+	call	PRTSTRD
+	.db	"\n\rSTART DMAMemMove\n\r$"
+	CALL	DMAMemMove
+	JP	MENULP
+;
+DMATST_D:
+	call	PRTSTRD
+	.db	"\n\rSTART DMARegDump\n\r$"
+	CALL	DMARegDump
+	JP	MENULP
+;
+DMATST_Y:
+	call	PRTSTRD
+	.db	"\n\r\Y READY\n\r$"
+;	CALL	
+	JP	MENULP
+;
+DMATST_R:
+	call	PRTSTRD
+	.db	"R RESET\n\r$"
+;	CALL	
+	JP	MENULP
+
+;
+DISPM:	call	PRTSTRD
+	.db	"\n\rDMA DEVICE: $"
+	LD	C,DMAMODE_MBC		; DISPLAY
+	LD	A,00000011B		; TARGET
+	LD	DE,DMA_DEV_STR		; DEVICE
+	CALL	PRTIDXMSK
+	CALL	NEWLINE
+;
+	call	PRTSTRD
+	.db	"DMA PORT: $"
+	LD	A,DMABASE		; DISPLAY
+	CALL	PRTHEXBYTE		; DMA PORT
+	CALL	NEWLINE
+;
+	LD	HL,MENU_OPT		; DISPLAY
+	CALL	PRTSTR			; MENU OPTIONS
+;
+	RET
+;
+#INCLUDE "util.asm"
+;
+;==================================================================================================
+; DMA INITIALIZATION CODE
+;==================================================================================================
+;
+DMA_INIT:
+	CALL	NEWLINE
+	PRTS("DMA: IO=0x$")		; announce
+	LD	A, DMABASE
+	CALL	PRTHEXBYTE
+;
+	LD	A,DMA_FORCE
+	out	(DMABASE+1),a		; force ready off
+;
+#IF (DMA_USEHS)
+	ld	a,(HB_RTCVAL)
+	or	%00001000		; half
+	out	(RTCIO),a		; clock
+#ENDIF
+;
+	call	DMAProbe		; do we have a dma?
+	jr	nz,DMA_NOTFOUND
+;
+	call	PRTSTRD
+	.db	" DMA FOUND\n\r$"
+;
+	ld	hl,DMACode		; program the
+	ld	b,DMACode_Len		; dma command
+	ld	c,DMABASE		; block
+;
+	di
+	otir				; load dma
+	ei
+	xor	a			; set status
+;
+DMA_EXIT:
+#IF (DMA_USEHS)
+	push	af
+	ld	a,(HB_RTCVAL)
+	and	%11110111		; full
+	out	(RTCIO),a		; clock
+	pop	af
+#ENDIF
+	ret
+;
+DMA_NOTFOUND:
+	push	af
+	call	PRTSTRD
+	.db	" NOT PRESENT$"
+
+#IF (DMA_FBACK)
+	call	PRTSTRD
+	.db	". USING SOFTWARE$"
+	LD	A,ERR_NOHW
+	LD	(DMA_FAIL_FLAG),A
+#ENDIF
+	pop	af
+	jr	DMA_EXIT
+;
+DMA_FAIL_FLAG:
+	.db	0
+;	
+DMA_DEV_STR:
+	.TEXT	"NONE$"
+	.TEXT	"ECB$"
+	.TEXT	"Z180"
+	.TEXT	"Z280$"
+	.TEXT	"MBC$"
+;
+MENU_OPT:
+	.TEXT	"\n\r"
+	.TEXT	"I) Initialize DMA\n\r"
+	.TEXT	"M) Memory to Memory test\n\r"
+	.TEXT	"P) Port select test\n\r"
+	.TEXT	"R) Reset bit test\n\r"
+	.TEXT	"Y) Ready bit test\n\r"
+	.TEXT	"X) Exit\n\r"
+
+	.TEXT	">$"
+;
+;==================================================================================================
+; DMA MEMORY MOVE
+;==================================================================================================
+;
+DMAMemMove:
+;
+	LD	HL,$8000	; PREFILL DESTINATION WITH $55
+	LD	A,$55
+	LD	(HL),A
+	LD	DE,$8001
+	LD	BC,4096-1
+	LDIR
+;
+	LD	HL,PROEND	; FILL SOURCE WITH $AA
+	LD	A,$AA
+	LD	(HL),A
+	LD	DE,PROEND+1
+	LD	BC,4096-1
+	LDIR
+;
+	LD	HL,PROEND	; DMA COPY
+	LD	DE,$8000
+	LD	BC,4096-1
+	CALL	DMALDIR
+
+;
+;	LD	HL,$8400	; PLANT
+;	LD	A,$00		; BAD
+;	LD	(HL),A		; SEED
+;
+	LD	A,$AA		; CHECK COPY SUCCESSFULL
+	LD	HL,$8000
+	LD	BC,4096
+NXTCMP:	CPI
+	JP	PO,CMPOK
+	JR	Z,NXTCMP
+
+	call	PRTHEXWORD
+	call	PRTSTRD
+	.db	" TEST MEMORY MOVE FAILED\n\r$"
+	RET
+
+CMPOK:	call	PRTSTRD
+	.db	"TEST MEMORY MOVE SUCCEEDED\n\r$"
+	RET
+;
+;==================================================================================================
+; DMA PROBE - WRITE TO ADDRESS REGISTER AND READ BACK
+;==================================================================================================
+;
+DMAProbe:
+	ld	a,DMA_RESET	
+	out	(DMABASE),a
+	ld	a,%01111101 		; R0-Transfer mode, A -> B, start address follows
+	out	(DMABASE),a
+	ld	a,$cc
+	out	(DMABASE),a
+	ld	a,$dd
+	out	(DMABASE),a
+	ld	a,$e5
+	out	(DMABASE),a
+	ld	a,$1a
+	out	(DMABASE),a
+	ld	a,DMA_LOAD
+	out	(DMABASE),a
+;
+	ld	a,DMA_READ_MASK_FOLLOWS	; set up
+	out	(DMABASE),a		; for 
+	ld	a,%00011000		; register
+	out	(DMABASE),a		; read
+	ld	a,DMA_START_READ_SEQUENCE
+	out	(DMABASE),a
+;
+	in	a,(DMABASE)		; read in 
+	ld	c,a			; address
+	in	a,(DMABASE)
+	ld	b,a
+;
+	xor	a			; is it
+	ld	hl,$ddcc		; a match
+	sbc	hl,bc			; return with
+	ret	z			; status
+	cpl
+	ret
+;
+DMACode		;.db	DMA_DISABLE	; R6-Command Disable DMA
+		.db	%01111101 	; R0-Transfer mode, A -> B, start address, block length follow
+		.dw	0		; R0-Port A, Start address
+		.dw	0 		; R0-Block length
+		.db	%00010100	; R1-No timing bytes follow, address increments, is memory
+		.db	%00010000 	; R2-No timing bytes follow, address increments, is memory
+		.db	%10000000 	; R3-DMA, interrupt, stop on match disabled
+		.db	DMA_CONTINUOUS	; R4-Continuous mode, destination address, interrupt and control byte follow
+		.dw	0 		; R4-Port B, Destination address
+		.db	%00001100	; R4-Pulse byte follows, Pulse generated
+		.db	0		; R4-Pulse offset
+		.db	%10010010+DMA_RDY; R5-Stop on end of block, ce/wait multiplexed, READY active config
+		.db	DMA_LOAD 	; R6-Command Load
+;		.db	DMA_FORCE_READY	; R6-Command Force ready
+;		.db	DMA_ENABLE 	; R6-Command Enable DMA
+DMACode_Len 	.equ	$-DMACode
+;
+;==================================================================================================
+; DMA COPY BLOCK CODE -  ASSUMES DMA PREINITIALIZED
+;==================================================================================================
+;
+DMALDIR:
+	ld	(DMASource),hl		; populate the dma
+	ld	(DMADest),de		; register template
+	ld	(DMALength),bc
+;
+	ld	hl,DMACopy		; program the
+	ld	b,DMACopy_Len		; dma command
+	ld	c,DMABASE		; block
+;
+#IF (DMA_USEHS)
+	ld	a,(HB_RTCVAL)
+	or	%00001000		; half
+	out	(RTCIO),a		; clock
+#ENDIF
+	di
+	otir				; load and execute dma
+	ei
+;
+	ld	a,DMA_READ_STATUS_BYTE	; check status
+	out	(DMABASE),a		; of transfer
+	in	a,(DMABASE)		; set non-zero
+	and	%00111011		; if failed
+	sub	%00011011
+#IF (DMA_USEHS)
+	push	af
+	ld	a,(HB_RTCVAL)
+	and	%11110111		; full
+	out	(RTCIO),a		; clock
+	pop	af
+#ENDIF
+	ret
+;
+DMACopy 	;.db	DMA_DISABLE	; R6-Command Disable DMA
+		.db	%01111101 	; R0-Transfer mode, A -> B, start address, block length follow
+DMASource	.dw	0 		; R0-Port A, Start address
+DMALength	.dw	0 		; R0-Block length
+		.db	%00010100	; R1-No timing bytes follow, address increments, is memory
+		.db	%00010000 	; R2-No timing bytes follow, address increments, is memory
+		.db	%10000000 	; R3-DMA, interrupt, stop on match disabled
+		.db	DMA_CONTINUOUS	; R4-Continuous mode, destination address, interrupt and control byte follow
+DMADest		.dw	0 		; R4-Port B, Destination address
+		.db	%00001100	; R4-Pulse byte follows, Pulse generated
+		.db	0		; R4-Pulse offset
+;		.db	%10010010+DMA_RDY;R5-Stop on end of block, ce/wait multiplexed, READY active config
+		.db	DMA_LOAD 	; R6-Command Load
+		.db	DMA_FORCE_READY	; R6-Command Force ready
+		.db	DMA_ENABLE 	; R6-Command Enable DMA
+DMACopy_Len 	.equ	$-DMACopy
+;
+;==================================================================================================
+; DMA I/O OUT BLOCK CODE - ADDRESS TO I/O PORT
+;==================================================================================================
+;
+DMAOTIR:
+	ld	(DMAOutSource),hl	; populate the dma
+	ld	(DMAOutDest),a		; register template
+	ld	(DMAOutLength),bc	
+;
+	ld	hl,DMAOutCode		; program the
+	ld	b,DMAOut_Len		; dma command
+	ld	c,DMABASE		; block
+;
+#IF (DMA_USEHS)
+	ld	a,(HB_RTCVAL)
+	or	%00001000		; half
+	out	(RTCIO),a		; clock
+#ENDIF
+	di
+	otir				; load and execute dma
+	ei
+;
+	ld	a,DMA_READ_STATUS_BYTE	; check status
+	out	(DMABASE),a		; of transfer
+	in	a,(DMABASE)		; set non-zero
+	and	%00111011		; if failed
+	sub	%00011011
+;
+#IF (DMA_USEHS)
+	push	af
+	ld	a,(HB_RTCVAL)
+	and	%11110111		; full
+	out	(RTCIO),a		; clock
+	pop	af
+#ENDIF
+	ret
+;
+DMAOutCode  	;.db	DMA_DISABLE	; R6-Command Disable DMA
+		.db	%01111001 	; R0-Transfer mode, B -> A (temp), start address, block length follow	
+DMAOutSource	.dw	0 		; R0-Port A, Start address
+DMAOutLength	.dw	0 		; R0-Block length
+
+		.db	%00010100	; R1-No timing bytes follow, fixed incrementing address, is memory	
+		.db	%00101000 	; R2-No timing bytes follow, address static, is i/o			
+		.db	%10000000 	; R3-DMA, interrupt, stop on match disabled
+
+		.db	%10100101	; R4-Continuous mode, destination port, interrupt and control byte follow
+DMAOutDest	.db	0 		; R4-Port B, Destination port
+;		.db	%00001100	; R4-Pulse byte follows, Pulse generated
+;		.db	0		; R4-Pulse offset
+
+		.db	%10010010+DMA_RDY;R5-Stop on end of block, ce/wait multiplexed, READY active config	
+		.db	DMA_LOAD 	; R6-Command Load							
+		.db	%00000101	; R0-Port A is Source							
+		.db	DMA_LOAD 	; R6-Command Load							
+		.db	DMA_FORCE_READY	; R6-Command Force ready						
+		.db	DMA_ENABLE 	; R6-Command Enable DMA							
+DMAOut_Len 	.equ	$-DMAOutCode
+;
+;==================================================================================================
+; DMA I/O INPUT BLOCK CODE - I/O PORT TO ADDRESS
+;==================================================================================================
+;
+DMAINIR:
+	ld	(DMAInDest),hl		; populate the dma
+	ld	(DMAInSource),a		; register template
+	ld	(DMAInLength),bc	
+;
+	ld	hl,DMAInCode		; program the
+	ld	b,DMAIn_Len		; dma command
+	ld	c,DMABASE		; block
+;
+#IF (DMA_USEHS)
+	ld	a,(HB_RTCVAL)
+	or	%00001000		; half
+	out	(RTCIO),a		; clock
+#ENDIF
+	di
+	otir				; load and execute dma
+	ei
+;
+	ld	a,DMA_READ_STATUS_BYTE	; check status
+	out	(DMABASE),a		; of transfer
+	in	a,(DMABASE)		; set non-zero
+	and	%00111011		; if failed
+	sub	%00011011
+;
+#IF (DMA_USEHS)
+	push	af
+	ld	a,(HB_RTCVAL)
+	and	%11110111		; full
+	out	(RTCIO),a		; clock
+	pop	af
+#ENDIF
+	ret
+;
+DMAInCode 	;.db	DMA_DISABLE	; R6-Command Disable DMA
+		.db	%01111001 	; R0-Transfer mode, B -> A, start address, block length follow		
+DMAInDest	.dw	0 		; R0-Port A, Start address
+DMAInLength	.dw	0 		; R0-Block length
+		.db	%00010100	; R1-No timing bytes follow, address increments, is memory		
+		.db	%00111000 	; R2-No timing bytes follow, address static, is i/o			
+		.db	%10000000 	; R3-DMA, interrupt, stop on match disabled
+		.db	%10100101	; R4-Continuous mode, destination port, no interrupt, control byte.	
+DMAInSource	.db	0 		; R4-Port B, Destination port
+;		.db	%00001100	; R4-Pulse byte follows, Pulse generated
+;		.db	0		; R4-Pulse offset
+		.db	%10010010+DMA_RDY;R5-Stop on end of block, ce/wait multiplexed, READY active config	
+		.db	DMA_LOAD 	; R6-Command Load							
+		.db	DMA_FORCE_READY	; R6-Command Force ready						
+		.db	DMA_ENABLE 	; R6-Command Enable DMA							
+
+DMAIn_Len 	.equ	$-DMAInCode
+;
+;==================================================================================================
+; DEBUG - READ START, DESTINATION AND COUNT REGISTERS
+;==================================================================================================
+;
+;#IF (0)
+;
+DMARegDump:
+	ld	a,DMA_READ_MASK_FOLLOWS
+	out	(DMABASE),a
+	ld	a,%01111110
+	out	(DMABASE),a
+	ld	a,DMA_START_READ_SEQUENCE
+	out	(DMABASE),a
+;
+	in	a,(DMABASE)
+	ld	c,a
+	in	a,(DMABASE)
+	ld	b,a
+	call	PRTHEXWORD
+	ld	a,':'
+	call	COUT
+;
+	in	a,(DMABASE)
+	ld	c,a
+	in	a,(DMABASE)
+	ld	b,a
+	call	PRTHEXWORD
+	ld	a,':'
+	call	COUT
+;
+	in	a,(DMABASE)
+	ld	c,a
+	in	a,(DMABASE)
+	ld	b,a
+	call	PRTHEXWORD
+;
+	call	NEWLINE
+	ret
+;#ENDIF
+
+
+;
+;__COUT_______________________________________________________________________
+;
+;	OUTPUT CHARACTER FROM A
+;_____________________________________________________________________________
+;
+COUT:
+	; SAVE ALL INCOMING REGISTERS
+	PUSH	AF
+	PUSH	BC
+	PUSH	DE
+	PUSH	HL
+;
+	; OUTPUT CHARACTER TO CONSOLE VIA HBIOS
+	LD	E,A			; OUTPUT CHAR TO E
+	LD	C,CIO_CONSOLE		; CONSOLE UNIT TO C
+	LD	B,BF_CIOOUT		; HBIOS FUNC: OUTPUT CHAR
+	CALL	$FFF0			; HBIOS OUTPUTS CHARACTER
+;
+	; RESTORE ALL REGISTERS
+	POP	HL
+	POP	DE
+	POP	BC
+	POP	AF
+	RET
+;
+;__CIN________________________________________________________________________
+;
+;	INPUT CHARACTER TO A
+;_____________________________________________________________________________
+;
+CIN:
+	; SAVE INCOMING REGISTERS (AF IS OUTPUT)
+	PUSH	BC
+	PUSH	DE
+	PUSH	HL
+;
+	; INPUT CHARACTER FROM CONSOLE VIA HBIOS
+	LD	C,CIO_CONSOLE		; CONSOLE UNIT TO C
+	LD	B,BF_CIOIN		; HBIOS FUNC: INPUT CHAR
+	CALL	$FFF0			; HBIOS READS CHARACTER
+	LD	A,E			; MOVE CHARACTER TO A FOR RETURN
+;
+	; RESTORE REGISTERS (AF IS OUTPUT)
+	POP	HL
+	POP	DE
+	POP	BC
+	RET
+;
+;__CST________________________________________________________________________
+;
+;	RETURN INPUT STATUS IN A (0 = NO CHAR, !=0 CHAR WAITING)
+;_____________________________________________________________________________
+;
+CST:
+	; SAVE INCOMING REGISTERS (AF IS OUTPUT)
+	PUSH	BC
+	PUSH	DE
+	PUSH	HL
+;
+	; GET CONSOLE INPUT STATUS VIA HBIOS
+	LD	C,CIO_CONSOLE		; CONSOLE UNIT TO C
+	LD	B,BF_CIOIST		; HBIOS FUNC: INPUT STATUS
+	CALL	$FFF0			; HBIOS RETURNS STATUS IN A
+;
+	; RESTORE REGISTERS (AF IS OUTPUT)
+	POP	HL
+	POP	DE
+	POP	BC
+	RET
+
+SAVSTK:	.DW	2
+	.FILL	64
+STACK:	.EQU	$
+PROEND:	.EQU	$
+;
+	.end
--- a/Source/Apps/TEST/DMAmon/dmamon.bat
+++ b/Source/Apps/TEST/DMAmon/dmamon.bat
@ -0,0 +1,2 @@
+tasm -t80 -b dmamon.asm dmamon.com
+
--- a/Source/Apps/TEST/DMAmon/dmamon.sh
+++ b/Source/Apps/TEST/DMAmon/dmamon.sh
@ -0,0 +1,3 @@
+~/RomWBW-dev/Tools/unix/uz80as/uz80as -t z80 dmamon.asm dmamon.bin
+#srec_cat dmamon.bin -binary -offset 0x0100 --address-length=2 -o dmamon.hex -Intel
+cat dmamon.bin > dmamon.com
--- a/Source/Apps/TEST/DMAmon/hbios.inc
+++ b/Source/Apps/TEST/DMAmon/hbios.inc
@ -0,0 +1,267 @@
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;
+; HBIOS FUNCTIONS
+;
+BF_CIO		.EQU	$00
+BF_CIOIN	.EQU	BF_CIO + 0	; CHARACTER INPUT
+BF_CIOOUT	.EQU	BF_CIO + 1	; CHARACTER OUTPUT
+BF_CIOIST	.EQU	BF_CIO + 2	; CHARACTER INPUT STATUS
+BF_CIOOST	.EQU	BF_CIO + 3	; CHARACTER OUTPUT STATUS
+BF_CIOINIT	.EQU	BF_CIO + 4	; INIT/RESET DEVICE/LINE CONFIG
+BF_CIOQUERY	.EQU	BF_CIO + 5	; REPORT DEVICE/LINE CONFIG
+BF_CIODEVICE	.EQU	BF_CIO + 6	; REPORT DEVICE INFO
+;
+BF_DIO		.EQU	$10
+BF_DIOSTATUS	.EQU	BF_DIO + 0	; DISK STATUS
+BF_DIORESET	.EQU	BF_DIO + 1	; DISK RESET
+BF_DIOSEEK	.EQU	BF_DIO + 2	; DISK SEEK
+BF_DIOREAD	.EQU	BF_DIO + 3	; DISK READ SECTORS
+BF_DIOWRITE	.EQU	BF_DIO + 4	; DISK WRITE SECTORS
+BF_DIOVERIFY	.EQU	BF_DIO + 5	; DISK VERIFY SECTORS
+BF_DIOFORMAT	.EQU	BF_DIO + 6	; DISK FORMAT TRACK
+BF_DIODEVICE	.EQU	BF_DIO + 7	; DISK DEVICE INFO REPORT
+BF_DIOMEDIA	.EQU	BF_DIO + 8	; DISK MEDIA REPORT
+BF_DIODEFMED	.EQU	BF_DIO + 9	; DEFINE DISK MEDIA
+BF_DIOCAP	.EQU	BF_DIO + 10	; DISK CAPACITY REPORT
+BF_DIOGEOM	.EQU	BF_DIO + 11	; DISK GEOMETRY REPORT
+;
+BF_RTC		.EQU	$20
+BF_RTCGETTIM	.EQU	BF_RTC + 0	; GET TIME
+BF_RTCSETTIM	.EQU	BF_RTC + 1	; SET TIME
+BF_RTCGETBYT	.EQU	BF_RTC + 2	; GET NVRAM BYTE BY INDEX
+BF_RTCSETBYT	.EQU	BF_RTC + 3	; SET NVRAM BYTE BY INDEX
+BF_RTCGETBLK	.EQU	BF_RTC + 4	; GET NVRAM DATA BLOCK
+BF_RTCSETBLK	.EQU	BF_RTC + 5	; SET NVRAM DATA BLOCK
+BF_RTCGETALM	.EQU	BF_RTC + 6	; GET ALARM
+BF_RTCSETALM	.EQU	BF_RTC + 7	; SET ALARM
+BF_RTCDEVICE	.EQU	BF_RTC + 8	; RTC DEVICE INFO REPORT
+;
+BF_EMU		.EQU	$30		; DEPRECATED
+;
+BF_VDA		.EQU	$40
+BF_VDAINI	.EQU	BF_VDA + 0	; INITIALIZE VDU
+BF_VDAQRY	.EQU	BF_VDA + 1	; QUERY VDU STATUS
+BF_VDARES	.EQU	BF_VDA + 2	; SOFT RESET VDU
+BF_VDADEV	.EQU	BF_VDA + 3	; DEVICE INFO
+BF_VDASCS	.EQU	BF_VDA + 4	; SET CURSOR STYLE
+BF_VDASCP	.EQU	BF_VDA + 5	; SET CURSOR POSITION
+BF_VDASAT	.EQU	BF_VDA + 6	; SET CHARACTER ATTRIBUTE
+BF_VDASCO	.EQU	BF_VDA + 7	; SET CHARACTER COLOR
+BF_VDAWRC	.EQU	BF_VDA + 8	; WRITE CHARACTER
+BF_VDAFIL	.EQU	BF_VDA + 9	; FILL
+BF_VDACPY	.EQU	BF_VDA + 10	; COPY
+BF_VDASCR	.EQU	BF_VDA + 11	; SCROLL
+BF_VDAKST	.EQU	BF_VDA + 12	; GET KEYBOARD STATUS
+BF_VDAKFL	.EQU	BF_VDA + 13	; FLUSH KEYBOARD BUFFER
+BF_VDAKRD	.EQU	BF_VDA + 14	; READ KEYBOARD
+;
+BF_SND		.EQU	$50
+BF_SNDRESET	.EQU	BF_SND + 0	; RESET SOUND SYSTEM
+BF_SNDVOL	.EQU	BF_SND + 1	; REQUEST SOUND VOL - L CONTAINS VOLUME (255 MAX, 0 SILENT) - SCALED AS REQUIRED BY DRIVER (EG: MAPS TO JUST 4 BIT RESOLUTION FOR SN76489)
+BF_SNDPRD	.EQU	BF_SND + 2	; REQUEST SOUND PERIOD - HL CONTAINS DRIVER SPECIFIC VALUE
+BF_SNDNOTE	.EQU	BF_SND + 3	; REQUEST NOTE - L CONTAINS NOTE - EACH VALUE IS QUARTER NOTE
+BF_SNDPLAY	.EQU	BF_SND + 4	; INITIATE THE REQUESTED SOUND COMMAND
+BF_SNDQUERY	.EQU	BF_SND + 5	; E IS SUBFUNCTION
+BF_SNDDURATION	.EQU	BF_SND + 6	; REQUEST DURATION HL MILLISECONDS
+BF_SNDDEVICE	.EQU	BF_SND + 7	; SOUND DEVICE INFO REQUEST
+;
+; BF_SNDQUERY SUBCOMMANDS
+BF_SNDQ_STATUS		.EQU	0
+BF_SNDQ_CHCNT		.EQU	BF_SNDQ_STATUS + 1	; RETURN COUNT OF CHANNELS
+BF_SNDQ_VOLUME		.EQU	BF_SNDQ_STATUS + 2	; 8 BIT NUMBER
+BF_SNDQ_PERIOD		.EQU	BF_SNDQ_STATUS + 3	; 16 BIT NUMBER
+BF_SNDQ_DEV		.EQU	BF_SNDQ_STATUS + 4	; RETURN DEVICE TYPE CODE AND IO PORTS - TYPE IN B, PORTS IN DE, HL
+;
+BF_SYS		.EQU	$F0
+BF_SYSRESET	.EQU	BF_SYS + 0	; SOFT RESET HBIOS
+BF_SYSVER	.EQU	BF_SYS + 1	; GET HBIOS VERSION
+BF_SYSSETBNK	.EQU	BF_SYS + 2	; SET CURRENT BANK
+BF_SYSGETBNK	.EQU	BF_SYS + 3	; GET CURRENT BANK
+BF_SYSSETCPY	.EQU	BF_SYS + 4	; BANK MEMORY COPY SETUP
+BF_SYSBNKCPY	.EQU	BF_SYS + 5	; BANK MEMORY COPY
+BF_SYSALLOC	.EQU	BF_SYS + 6	; ALLOC HBIOS HEAP MEMORY
+BF_SYSFREE	.EQU	BF_SYS + 7	; FREE HBIOS HEAP MEMORY
+BF_SYSGET	.EQU	BF_SYS + 8	; GET HBIOS INFO
+BF_SYSSET	.EQU	BF_SYS + 9	; SET HBIOS PARAMETERS
+BF_SYSPEEK	.EQU	BF_SYS + 10	; GET A BYTE VALUE FROM ALT BANK
+BF_SYSPOKE	.EQU	BF_SYS + 11	; SET A BYTE VALUE IN ALT BANK
+BF_SYSINT	.EQU	BF_SYS + 12	; MANAGE INTERRUPT VECTORS
+;
+BF_SYSRES_INT		.EQU	$00	; RESET HBIOS INTERNAL
+BF_SYSRES_WARM		.EQU	$01	; WARM START (RESTART BOOT LOADER)
+BF_SYSRES_COLD		.EQU	$02	; COLD START
+BF_SYSRES_USER		.EQU	$03	; USER RESET REQUEST
+;
+BF_SYSGET_CIOCNT	.EQU	$00	; GET CHAR UNIT COUNT
+BF_SYSGET_CIOFN		.EQU	$01	; GET CIO UNIT FN/DATA ADR
+BF_SYSGET_DIOCNT	.EQU	$10	; GET DISK UNIT COUNT
+BF_SYSGET_DIOFN		.EQU	$11	; GET DIO UNIT FN/DATA ADR
+BF_SYSGET_RTCCNT	.EQU	$20	; GET RTC UNIT COUNT
+BF_SYSGET_VDACNT	.EQU	$40	; GET VDA UNIT COUNT
+BF_SYSGET_VDAFN		.EQU	$41	; GET VDA UNIT FN/DATA ADR
+BF_SYSGET_SNDCNT	.EQU	$50	; GET VDA UNIT COUNT
+BF_SYSGET_SNDFN		.EQU	$51	; GET SND UNIT FN/DATA ADR
+BF_SYSGET_TIMER		.EQU	$D0	; GET CURRENT TIMER VALUE
+BF_SYSGET_SECS		.EQU	$D1	; GET CURRENT SECONDS VALUE
+BF_SYSGET_BOOTINFO	.EQU	$E0	; GET BOOT INFORMATION
+BF_SYSGET_CPUINFO	.EQU	$F0	; GET CPU INFORMATION
+BF_SYSGET_MEMINFO	.EQU	$F1	; GET MEMORY CAPACTITY INFO
+BF_SYSGET_BNKINFO	.EQU	$F2	; GET BANK ASSIGNMENT INFO
+;
+BF_SYSSET_TIMER		.EQU	$D0	; SET TIMER VALUE
+BF_SYSSET_SECS		.EQU	$D1	; SET SECONDS VALUE
+BF_SYSSET_BOOTINFO	.EQU	$E0	; SET BOOT INFORMATION
+;
+BF_SYSINT_INFO		.EQU	$00	; GET INTERRUPT SYSTEM INFO
+BF_SYSINT_GET		.EQU	$10	; GET INT VECTOR ADDRESS
+BF_SYSINT_SET		.EQU	$20	; SET INT VECTOR ADDRESS
+;
+CIO_CONSOLE		.EQU	$80	; CIO UNIT NUM FOR CUR CON
+;
+; HBIOS GLOBAL ERROR RETURN VALUES
+;
+ERR_NONE		.EQU	0	; SUCCESS
+;
+ERR_UNDEF		.EQU	-1	; UNDEFINED ERROR
+ERR_NOTIMPL		.EQU	-2	; FUNCTION NOT IMPLEMENTED
+ERR_NOFUNC		.EQU	-3	; INVALID FUNCTION
+ERR_NOUNIT		.EQU	-4	; INVALID UNIT NUMBER
+ERR_NOMEM		.EQU	-5	; OUT OF MEMORY
+ERR_RANGE		.EQU	-6	; PARAMETER OUT OF RANGE
+ERR_NOMEDIA		.EQU	-7	; MEDIA NOT PRESENT
+ERR_NOHW		.EQU	-8	; HARDWARE NOT PRESENT
+ERR_IO			.EQU	-9	; I/O ERROR
+ERR_READONLY		.EQU	-10	; WRITE REQUEST TO READ-ONLY MEDIA
+ERR_TIMEOUT		.EQU	-11	; DEVICE TIMEOUT
+ERR_BADCFG		.EQU	-12	; INVALID CONFIGURATION
+ERR_INTERNAL		.EQU	-13	; INTERNAL ERROR
+;
+; MEDIA ID VALUES
+;
+MID_NONE	.EQU	0
+MID_MDROM	.EQU	1
+MID_MDRAM	.EQU	2
+MID_RF		.EQU	3
+MID_HD		.EQU	4
+MID_FD720	.EQU	5
+MID_FD144	.EQU	6
+MID_FD360	.EQU	7
+MID_FD120	.EQU	8
+MID_FD111	.EQU	9
+MID_HDNEW	.EQU	10
+;
+; CHAR DEVICE IDS
+;
+CIODEV_UART	.EQU	$00
+CIODEV_ASCI	.EQU	$10
+CIODEV_TERM	.EQU	$20
+CIODEV_PRPCON	.EQU	$30
+CIODEV_PPPCON	.EQU	$40
+CIODEV_SIO	.EQU	$50
+CIODEV_ACIA	.EQU	$60
+CIODEV_PIO	.EQU	$70
+CIODEV_UF	.EQU	$80
+CIODEV_DUART	.EQU	$90
+CIODEV_Z2U	.EQU	$A0
+;
+; SUB TYPES OF CHAR DEVICES
+;
+;00 RS-232
+;01 TERMINAL
+;02 PARALLEL PORT
+;03 UNUSED
+;
+; DISK DEVICE IDS
+;
+DIODEV_MD	.EQU	$00
+DIODEV_FD	.EQU	$10
+DIODEV_RF	.EQU	$20
+DIODEV_IDE	.EQU	$30
+DIODEV_ATAPI	.EQU	$40
+DIODEV_PPIDE	.EQU	$50
+DIODEV_SD	.EQU	$60
+DIODEV_PRPSD	.EQU	$70
+DIODEV_PPPSD	.EQU	$80
+DIODEV_HDSK	.EQU	$90
+;
+; RTC DEVICE IDS
+;
+RTCDEV_DS	.EQU	$00		; DS1302
+RTCDEV_BQ	.EQU	$10		; BQ4845P
+RTCDEV_SIMH	.EQU	$20		; SIMH
+RTCDEV_INT	.EQU	$30		; PERIODIC INT TIMER
+RTCDEV_DS7	.EQU	$40		; DS1302 (I2C)
+RTCDEV_RP5	.EQU	$50		; RP5C01
+;
+; VIDEO DEVICE IDS
+;
+VDADEV_VDU	.EQU	$00		; ECB VDU - MOTOROLA 6545
+VDADEV_CVDU	.EQU	$10		; ECB COLOR VDU - MOS 8563
+VDADEV_NEC	.EQU	$20		; ECB UPD7220 - NEC UPD7220
+VDADEV_TMS	.EQU	$30		; N8 ONBOARD VDA SUBSYSTEM - TMS 9918
+VDADEV_VGA	.EQU	$40		; ECB VGA3 - HITACHI HD6445
+;VDADEV_V9958	.EQU	$50		; V9958 VDU
+;
+; SOUND DEVICE IDS
+;
+SNDDEV_SN76489	.EQU	$00
+SNDDEV_AY38910	.EQU	$10
+SNDDEV_BITMODE	.EQU	$20
+;
+; HBIOS CONTROL BLOCK OFFSETS
+; WARNING: THESE OFFSETS WILL CHANGE SIGNIFICANTLY BETWEEN RELEASES
+;          IT IS STRONGLY RECOMMENDED THAT YOU DO NOT USE THEM!
+;
+HCB_LOC		.EQU	$100		; LOCATION OF HCB IN HBIOS BANK
+HCB_SIZ		.EQU	$100		; SIZE OF HCB DATA BLOCK
+;
+HCB_MARKER	.EQU	$03		; MARKER ('W',~'W') (WORD)
+HCB_VERSION	.EQU	$05		; HBIOS VERSION NUM
+HCB_PLATFORM	.EQU	$07		; PLATFORM ID
+HCB_CPUMHZ	.EQU	$08		; CPU SPEED IN MHZ (BYTE)
+HCB_CPUKHZ	.EQU	$09		; CPU SPEED IN KHZ (WORD)
+HCB_RAMBANKS	.EQU	$0B		; TOTAL SIZE OF RAM IN 32K BANKS (BYTE)
+HCB_ROMBANKS	.EQU	$0C		; TOTAL SIZE OF ROM IN 32K BANKS (BYTE)
+HCB_BOOTVOL	.EQU	$0D		; BOOT VOLUME, MSB=DEV/UNIT, LSB=LU (WORD)
+HCB_BOOTBID	.EQU	$0F		; BANK ID OF ROM PAGE BOOTED (BYTE)
+HCB_SERDEV	.EQU	$10		; PRIMARY SERIAL DEVICE/UNIT (BYTE)
+HCB_CRTDEV	.EQU	$11		; CRT DISPLAY DEVICE/UNIT (BYTE)
+HCB_CONDEV	.EQU	$12		; ACTIVE CONSOLE DEVICE/UNIT (BYTE)
+HCB_DIAGLVL	.EQU	$13		; HBIOS DIAGNOSTIC LEVEL (BYTE)
+;
+HCB_HEAP	.EQU	$20		; DWORD ADDRESS OF START OF HEAP
+HCB_HEAPTOP	.EQU	$22		; DWORD ADDRESS OF TOP OF HEAP
+;
+; MEMORY BANK IDS (ONE BYTE EACH)
+HCB_BIDCOM	.EQU	$D8		; COMMON BANK (UPPER 32K)
+HCB_BIDUSR	.EQU	$D9		; USER BANK (TPA)
+HCB_BIDBIOS	.EQU	$DA		; BIOS BANK (HBIOS, UBIOS)
+HCB_BIDAUX	.EQU	$DB		; AUX BANK (BPBIOS)
+HCB_BIDRAMD0	.EQU	$DC		; FIRST BANK OF RAM DRIVE
+HCB_BIDRAMDN	.EQU	$DD		; LAST BANK OF RAM DRIVE
+HCB_BIDROMD0	.EQU	$DE		; FIRST BANK OF ROM DRIVE
+HCB_BIDROMDN	.EQU	$DF		; LAST BANK OF ROM DRIVE
+;
+; HBIOS PROXY COMMON DATA BLOCK
+; EXACTLY 32 BYTES AT $FFE0-$FFFF
+;
+HBX_XFC		.EQU	$10000 - $20		; HBIOS PROXY INTERFACE AREA, 32 BYTES FIXED
+;
+HBX_XFCDAT	.EQU	HBX_XFC			; DATA PORTION OF HBIOS PROXY INTERFACE AREA
+HB_CURBNK	.EQU	HBX_XFCDAT + 0		; CURRENTLY ACTIVE LOW MEMORY BANK ID
+HB_INVBNK	.EQU	HBX_XFCDAT + 1		; BANK ACTIVE AT TIME OF HBIOS CALL INVOCATION
+HB_SRCADR	.EQU	HBX_XFCDAT + 2		; BNKCPY: DESTINATION BANK ID
+HB_SRCBNK	.EQU	HBX_XFCDAT + 4		; BNKCPY: SOURCE BANK ID
+HB_DSTADR	.EQU	HBX_XFCDAT + 5		; BNKCPY: DESTINATION ADDRESS
+HB_DSTBNK	.EQU	HBX_XFCDAT + 7		; BNKCPY: SOURCE ADDRESS
+HB_CPYLEN	.EQU	HBX_XFCDAT + 8		; BNKCPY: COPY LENGTH
+HB_RTCVAL	.EQU	HBX_XFCDAT + 14		; RTC LATCH SHADOW VALUE
+HB_LOCK		.EQU	HBX_XFCDAT + 15		; INVOKE: HBIOS MUTEX LOCK
+;
+HBX_XFCFNS	.EQU	HBX_XFC + $10		; JUMP TABLE PORTION OF HBIOS PROXY INTERFACE AREA
+HB_INVOKE	.EQU	HBX_XFCFNS + (0 * 3)	; INVOKE HBIOS FUNCTION
+HB_BNKSEL	.EQU	HBX_XFCFNS + (1 * 3)	; SELECT LOW MEMORY BANK ID
+HB_BNKCPY	.EQU	HBX_XFCFNS + (2 * 3)	; INTERBANK MEMORY COPY
+HB_BNKCALL	.EQU	HBX_XFCFNS + (3 * 3)	; INTERBANK FUNCTION CALL
+;HB_LOC		.EQU	HBX_XFCFNS + 12		; ADDRESS OF HBIOS PROXY START (DEPRECATED)
+HB_IDENT	.EQU	HBX_XFCFNS + 14		; POINTER TO HBIOS IDENT DATA BLOCK
--- a/Source/Apps/TEST/DMAmon/std.asm
+++ b/Source/Apps/TEST/DMAmon/std.asm
@ -0,0 +1,675 @@
+; The purpose of this file is to define generic symbols and to include
+; the requested build configuraton file to bring in platform specifics.
+
+; There are several hardware platforms supported by SBC.
+; 1.  SBC	Z80 SBC (v1 or v2) w/ ECB interface
+; 2.  ZETA	Standalone Z80 SBC w/ SBC compatibility
+; 3.  ZETA2	Second version of ZETA with enhanced memory bank switching
+; 4.  N8	MSX-ish Z180 SBC w/ onboard video and sound
+; 5.  MK4	Mark IV Z180 based SBC w/ ECB interface
+; 6.  UNA	Any Z80/Z180 computer with UNA BIOS
+; 7.  RCZ80	RC2014 based system with 512K banked RAM/ROM card
+; 8.  RCZ180	RC2014 based system with Z180 CPU
+; 9.  EZZ80	Easy Z80, Z80 SBC w/ RC2014 bus and CTC
+; 10. SCZ180	Steve Cousins Z180 based system
+; 11. DYNO	Steve Garcia's Dyno Micro-ATX Motherboard
+; 12. RCZ280	Z280 CPU on RC2014 or ZZ80MB
+; 13. MBC	Andrew Lynch's Multi Board Computer
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;
+; INCLUDE VERSION
+;
+#INCLUDE "ver.inc"			; ADD BIOSVER
+;
+FALSE		.EQU	0
+TRUE		.EQU	~FALSE
+;
+; DEBUGGING OPTIONS
+;
+USENONE		.EQU	0		; NO DEBUG
+USEXIO		.EQU	1		; BASIC SERIAL DRIVER
+USEMIO		.EQU	2		; MEMORY BUFFER DRIVER
+WBWDEBUG	.EQU	USENONE
+;
+; DIAGNOSTIC LEVEL OPTIONS
+;
+DL_NONE		.EQU	0		; HBIOS DISPLAY NO MESSAGES
+DL_CRITICAL	.EQU	4		; HBIOS DISPLAY CRITICAL ERROR MESSAGES
+DL_ERROR	.EQU	8		; HBIOS DISPLAYS ALL ERROR MESSAGES
+DL_WARNING	.EQU	12		; HBIOS DISPLAYS WARNING MESSAGES
+DL_INFO		.EQU	16		; HBIOS DISPLAYS INFORMATIONAL MESSAGES
+DL_DETAIL	.EQU	20		; HBIOS DISPLAYS DETAILED DIAGNOSTIC MESSAGES
+DL_VERBOSE	.EQU	24		; HBIOS DISPLAYS ANYTHING IT KNOWS HOW TO
+;
+; PRIMARY HARDWARE PLATFORMS
+;
+PLT_SBC		.EQU	1		; SBC ECB Z80 SBC
+PLT_ZETA	.EQU	2		; ZETA Z80 SBC
+PLT_ZETA2	.EQU	3		; ZETA Z80 V2 SBC
+PLT_N8		.EQU	4		; N8 (HOME COMPUTER) Z180 SBC
+PLT_MK4		.EQU	5		; MARK IV
+PLT_UNA		.EQU	6		; UNA BIOS
+PLT_RCZ80	.EQU	7		; RC2014 W/ Z80
+PLT_RCZ180	.EQU	8		; RC2014 W/ Z180
+PLT_EZZ80	.EQU	9		; EASY Z80
+PLT_SCZ180	.EQU	10		; SCZ180
+PLT_DYNO	.EQU	11		; DYNO MICRO-ATX MOTHERBOARD
+PLT_RCZ280	.EQU	12		; RC2014 W/ Z280
+PLT_MBC		.EQU	13		; MULTI BOARD COMPUTER
+;
+; CPU TYPES
+;
+CPU_NONE	.EQU	0		; NO CPU TYPE DEFINED
+CPU_Z80		.EQU	1		; Z80 FAMILY
+CPU_Z180	.EQU	2		; Z180 FAMILY
+CPU_Z280	.EQU	3		; Z280 FAMILY
+;
+; BIOS MODE
+;
+BIOS_NONE	.EQU	0		; NO BIOS TYPE DEFINED
+BIOS_WBW	.EQU	1		; ROMWBW HBIOS
+BIOS_UNA	.EQU	2		; UNA UBIOS
+;
+; DEFAULT HBIOS DIAGNOSTIC LEVEL
+;   WILL ULTIMATELY BE MOVED TO CONFIG FILE
+;
+DIAGLVL		.EQU	DL_CRITICAL
+;
+; MEMORY MANAGERS
+;
+MM_NONE		.EQU	0
+MM_SBC		.EQU	1		; ORIGINAL N8VEM/RBC Z80 SBC BANKED MEMORY
+MM_Z2		.EQU	2		; 16K X 4 BANKED MEMORY INTRODUCED ON ZETA2
+MM_N8		.EQU	3		; Z180 CUSTOMIZED FOR N8 MEMORY EXTENSIONS
+MM_Z180		.EQU	4		; Z180 NATIVE MEMORY MANAGER
+MM_Z280		.EQU	5		; Z280 NATIVE MEMORY MANAGER
+MM_ZRC		.EQU	6		; ZRC BANK SWITCHING
+MM_MBC		.EQU	7		; MBC MEMORY MANAGER
+;
+; BOOT STYLE
+;
+BT_MENU		.EQU	1		; WAIT FOR MENU SELECTION AT LOADER PROMPT
+BT_AUTO		.EQU	2		; AUTO SELECT BOOT_DEFAULT AFTER BOOT_TIMEOUT
+;
+; BOOT RECOVERY METHODS
+;
+BT_REC_NONE	.EQU	0		; NO RECOVERY MODE
+BT_REC_FORCE	.EQU	1		; FORCE BOOT RECOVERY MODE
+BT_REC_SBC01	.EQU	2		; ECB-SBCV2 - BIT 1 RTC HIGH
+BT_REC_SBC1B	.EQU	3		; ECB-SBCV2 - 1-BIT IO PORT
+BT_REC_SBCRI	.EQU	4		; ECB-SBCV2 - 16550 UART RING INDICATOR LINE
+;
+BT_REC_TYPE	.EQU	BT_REC_NONE	; BOOT RECOVERY METHOD TO USE
+;
+; FLOPPY DISK MEDIA SELECTIONS (ID'S MUST BE INDEX OF ENTRY IN FCD_TBL)
+;
+FDM720		.EQU	0		; 3.5" FLOPPY, 720KB, 2 SIDES, 80 TRKS, 9 SECTORS
+FDM144		.EQU	1		; 3.5" FLOPPY, 1.44MB, 2 SIDES, 80 TRKS, 18 SECTORS
+FDM360		.EQU	2		; 5.25" FLOPPY, 360KB, 2 SIDES, 40 TRKS, 9 SECTORS
+FDM120		.EQU	3		; 5.25" FLOPPY, 1.2MB, 2 SIDES, 80 TRKS, 15 SECTORS
+FDM111		.EQU	4		; 8" FLOPPY, 1.11MB, 2 SIDES, 74 TRKS, 15 SECTORS
+;
+; ZILOG CTC MODE SELECTIONS
+;
+CTCMODE_NONE	.EQU	0		; NO CTC
+CTCMODE_CTR	.EQU	1		; CTC COUNTER
+CTCMODE_TIM16	.EQU	2		; CTC TIMER W/ DIV 16
+CTCMODE_TIM256	.EQU	3		; CTC TIMER W/ DIV 256
+;
+; DS1302 RTC MODE SELECTIONS
+;
+DSRTCMODE_NONE	.EQU	0		; NO DSRTC
+DSRTCMODE_STD	.EQU	1		; ORIGINAL DSRTC CIRCUIT (SBC, ZETA, MK4)
+DSRTCMODE_MFPIC	.EQU	2		; MF/PIC VARIANT
+;
+; DS1307 RTC MODE SELECTIONS
+;
+DS7RTCMODE_NONE	.EQU	0		; NO DSRTC
+DS7RTCMODE_PCF	.EQU	1		; PCF8584 I2C
+;
+; SIO MODE SELECTIONS
+;
+SIOMODE_NONE	.EQU	0
+SIOMODE_STD	.EQU	1		; STD SIO REG CFG (EZZ80, KIO)
+SIOMODE_RC	.EQU	2		; RC2014 SIO MODULE (SPENCER OWEN)
+SIOMODE_SMB	.EQU	3		; RC2014 SIO MODULE (SCOTT BAKER)
+SIOMODE_ZP	.EQU	4		; ECB-ZILOG PERIPHERALS BOARD
+;
+; TYPE OF CONSOLE BELL TO USE
+;
+CONBELL_NONE	.EQU	0
+CONBELL_PSG	.EQU	1
+CONBELL_IOBIT	.EQU	2
+;
+; LED MODE SELECTIONS
+;
+LEDMODE_NONE	.EQU	0
+LEDMODE_STD	.EQU	1
+LEDMODE_RTC	.EQU	2
+;
+; DSKY MODE SELECTIONS
+;
+DSKYMODE_NONE	.EQU	0
+DSKYMODE_V1	.EQU	1
+DSKYMODE_NG	.EQU	2
+;
+; FD MODE SELECTIONS
+;
+FDMODE_NONE	.EQU	0
+FDMODE_DIO	.EQU	1		; DISKIO V1
+FDMODE_ZETA	.EQU	2		; ZETA
+FDMODE_ZETA2	.EQU	3		; ZETA V2
+FDMODE_DIDE	.EQU	4		; DUAL IDE
+FDMODE_N8	.EQU	5		; N8
+FDMODE_DIO3	.EQU	6		; DISKIO V3
+FDMODE_RCSMC	.EQU	7		; RC2014 SMC 9266 @ $40 (SCOTT BAKER)
+FDMODE_RCWDC	.EQU	8		; RC2014 WDC 37C65 @ $40 (SCOTT BAKER)
+FDMODE_DYNO	.EQU	9		; DYNO WDC 37C65 @ $84
+FDMODE_EPFDC	.EQU	10		; RC2014 ETCHED PIXELS FDC
+FDMODE_MBC	.EQU	11		; MULTI-BOARD COMPUTER FDC
+;
+; IDE MODE SELECTIONS
+;
+IDEMODE_NONE	.EQU	0
+IDEMODE_DIO	.EQU	1		; DISKIO V1
+IDEMODE_DIDE	.EQU	2		; DUAL IDE
+IDEMODE_MK4	.EQU	3		; MARK IV ONBOARD IDE (8 BIT ONLY)
+IDEMODE_RC	.EQU	4		; RC2014 CF MODULE (8 BIT ONLY)
+;
+; PPIDE MODE SELECTIONS
+;
+PPIDEMODE_NONE	.EQU	0
+PPIDEMODE_SBC	.EQU	1		; STANDARD SBC PARALLEL PORT
+PPIDEMODE_DIO3	.EQU	2		; DISKIO V3 PARALLEL PORT
+PPIDEMODE_MFP	.EQU	3		; MULTIFUNCTION / PIC
+PPIDEMODE_N8	.EQU	4		; MULTIFUNCTION / PIC
+PPIDEMODE_RC	.EQU	5		; RC2014 PPIDE MODULE @ $20 (ED BRINDLEY)
+PPIDEMODE_DYNO	.EQU	6		; DYNO PPIDE @ $4C
+;
+; SD MODE SELECTIONS
+;
+SDMODE_NONE	.EQU	0
+SDMODE_JUHA	.EQU	1		; JUHA MINI BOARD
+SDMODE_N8	.EQU	2		; N8-2511, UNMODIFIED
+SDMODE_CSIO	.EQU	3		; N8-2312 OR N8-2511 MODIFIED
+SDMODE_PPI	.EQU	4		; PPISD MINI BOARD
+SDMODE_UART	.EQU	5		; SD INTERFACE VIA UART
+SDMODE_DSD	.EQU	6		; DUAL SD
+SDMODE_MK4	.EQU	7		; MARK IV
+SDMODE_SC	.EQU	8		; SC (Steve Cousins)
+SDMODE_MT	.EQU	9		; MT (Shift register SPI WIZNET for RC2014)
+;
+; SOUND CHIP MODE SELECTIONS
+;
+AYMODE_NONE	.EQU	0
+AYMODE_N8	.EQU	1		; N8 BUILT-IN SOUND
+AYMODE_SCG	.EQU	2		; SCG ECB BOARD
+AYMODE_RCZ80	.EQU	3		; RC2014 SOUND MODULE BY ED BRINDLEY ON Z80
+AYMODE_RCZ180	.EQU	4		; RC2014 SOUND MODULE BY ED BRINDLEY ON Z180
+AYMODE_MSX	.EQU	5		; RC2014 SOUND MODULE REV6 BY ED BRINDLEY ON Z80/Z180 AT MSX PORTS
+AYMODE_LINC	.EQU	6		; LINC Z50 AY SOUND CARD
+;
+; TMS VIDEO MODE SELECTIONS
+;
+TMSMODE_NONE	.EQU	0
+TMSMODE_SCG	.EQU	1		; SCG ECB BOARD
+TMSMODE_N8	.EQU	2		; N8 BUILT-IN VIDEO
+TMSMODE_RC	.EQU	3		; RC2014 TMS9918 VIDEO BOARD
+TMSMODE_RCV9958	.EQU	4		; RC2014 V9958 VIDEO BOARD
+;
+; DMA MODE SELECTIONS
+;
+DMAMODE_NONE	.EQU	0
+DMAMODE_ECB	.EQU	1		; ECB-DMA WOLFGANG KABATZKE'S Z80 DMA ECB BOARD
+DMAMODE_Z180	.EQU	2		; Z180 INTEGRATED DMA
+DMAMODE_Z280	.EQU	3		; Z280 INTEGRATED DMA
+DMAMODE_RC	.EQU	4		; RC2014 Z80 DMA
+DMAMODE_MBC	.EQU	5		; MBC
+;
+; SERIAL DEVICE CONFIGURATION CONSTANTS
+;
+SER_DATA5	.EQU	0 << 0
+SER_DATA6	.EQU	1 << 0
+SER_DATA7	.EQU	2 << 0
+SER_DATA8	.EQU	3 << 0
+;
+SER_PARNONE	.EQU	0 << 3
+SER_PARODD	.EQU	1 << 3
+SER_PAREVEN	.EQU	3 << 3
+SER_PARMARK	.EQU	5 << 3
+SER_PARSPACE	.EQU	7 << 3
+;
+SER_STOP1	.EQU	0 << 2
+SER_STOP2	.EQU	1 << 2
+;
+; SERIAL BAUD RATES ENCODED AS V = 75 * 2^X * 3^Y
+; AND STORED AS 5 BITS: YXXXX
+;
+SER_BAUD75	.EQU	$00 << 8
+SER_BAUD150	.EQU	$01 << 8
+SER_BAUD300	.EQU	$02 << 8
+SER_BAUD600	.EQU	$03 << 8
+SER_BAUD1200	.EQU	$04 << 8
+SER_BAUD2400	.EQU	$05 << 8
+SER_BAUD4800	.EQU	$06 << 8
+SER_BAUD9600	.EQU	$07 << 8
+SER_BAUD19200	.EQU	$08 << 8
+SER_BAUD38400	.EQU	$09 << 8
+SER_BAUD76800	.EQU	$0A << 8
+SER_BAUD153600	.EQU	$0B << 8
+SER_BAUD307200	.EQU	$0C << 8
+SER_BAUD614400	.EQU	$0D << 8
+SER_BAUD1228800	.EQU	$0E << 8
+SER_BAUD2457600	.EQU	$0F << 8
+SER_BAUD225	.EQU	$10 << 8
+SER_BAUD450	.EQU	$11 << 8
+SER_BAUD900	.EQU	$12 << 8
+SER_BAUD1800	.EQU	$13 << 8
+SER_BAUD3600	.EQU	$14 << 8
+SER_BAUD7200	.EQU	$15 << 8
+SER_BAUD14400	.EQU	$16 << 8
+SER_BAUD28800	.EQU	$17 << 8
+SER_BAUD57600	.EQU	$18 << 8
+SER_BAUD115200	.EQU	$19 << 8
+SER_BAUD230400	.EQU	$1A << 8
+SER_BAUD460800	.EQU	$1B << 8
+SER_BAUD921600	.EQU	$1C << 8
+SER_BAUD1843200	.EQU	$1D << 8
+SER_BAUD3686400	.EQU	$1E << 8
+SER_BAUD7372800	.EQU	$1F << 8
+;
+; UART DIVIDER VALUES
+; STORED AS 5 BITS: YXXXX
+;
+DIV_1		.EQU	$00
+DIV_2		.EQU	$01
+DIV_4		.EQU	$02
+DIV_8		.EQU	$03
+DIV_16		.EQU	$04
+DIV_32		.EQU	$05
+DIV_64		.EQU	$06
+DIV_128		.EQU	$07
+DIV_256		.EQU	$08
+DIV_512		.EQU	$09
+DIV_1024	.EQU	$0A
+DIV_2048	.EQU	$0B
+DIV_4096	.EQU	$0C
+DIV_8192	.EQU	$0D
+DIV_16384	.EQU	$0E
+DIV_32768	.EQU	$0F
+DIV_3		.EQU	$10
+DIV_6		.EQU	$11
+DIV_12		.EQU	$12
+DIV_24		.EQU	$13
+DIV_48		.EQU	$14
+DIV_96		.EQU	$15
+DIV_192		.EQU	$16
+DIV_384		.EQU	$17
+DIV_768		.EQU	$18
+DIV_1536	.EQU	$19
+DIV_3072	.EQU	$1A
+DIV_6144	.EQU	$1B
+DIV_12288	.EQU	$1C
+DIV_24576	.EQU	$1D
+DIV_49152	.EQU	$1E
+DIV_98304	.EQU	$1F
+;
+SER_XON		.EQU	1 << 6
+SER_DTR		.EQU	1 << 7
+SER_RTS		.EQU	1 << 13
+;
+SER_75_8N1	.EQU	SER_BAUD75 | SER_DATA8 | SER_PARNONE | SER_STOP1
+SER_150_8N1	.EQU	SER_BAUD150 | SER_DATA8 | SER_PARNONE | SER_STOP1
+SER_300_8N1	.EQU	SER_BAUD300 | SER_DATA8 | SER_PARNONE | SER_STOP1
+SER_600_8N1	.EQU	SER_BAUD600 | SER_DATA8 | SER_PARNONE | SER_STOP1
+SER_1200_8N1	.EQU	SER_BAUD1200 | SER_DATA8 | SER_PARNONE | SER_STOP1
+SER_2400_8N1	.EQU	SER_BAUD2400 | SER_DATA8 | SER_PARNONE | SER_STOP1
+SER_4800_8N1	.EQU	SER_BAUD4800 | SER_DATA8 | SER_PARNONE | SER_STOP1
+SER_9600_8N1	.EQU	SER_BAUD9600 | SER_DATA8 | SER_PARNONE | SER_STOP1
+SER_19200_8N1	.EQU	SER_BAUD19200 | SER_DATA8 | SER_PARNONE | SER_STOP1
+SER_38400_8N1	.EQU	SER_BAUD38400 | SER_DATA8 | SER_PARNONE | SER_STOP1
+SER_76800_8N1	.EQU	SER_BAUD76800 | SER_DATA8 | SER_PARNONE | SER_STOP1
+SER_153600_8N1	.EQU	SER_BAUD153600 | SER_DATA8 | SER_PARNONE | SER_STOP1
+SER_307200_8N1	.EQU	SER_BAUD307200 | SER_DATA8 | SER_PARNONE | SER_STOP1
+SER_614400_8N1	.EQU	SER_BAUD614400 | SER_DATA8 | SER_PARNONE | SER_STOP1
+SER_1228800_8N1	.EQU	SER_BAUD1228800 | SER_DATA8 | SER_PARNONE | SER_STOP1
+SER_2457600_8N1	.EQU	SER_BAUD2457600 | SER_DATA8 | SER_PARNONE | SER_STOP1
+SER_225_8N1	.EQU	SER_BAUD225 | SER_DATA8 | SER_PARNONE | SER_STOP1
+SER_450_8N1	.EQU	SER_BAUD450 | SER_DATA8 | SER_PARNONE | SER_STOP1
+SER_900_8N1	.EQU	SER_BAUD900 | SER_DATA8 | SER_PARNONE | SER_STOP1
+SER_1800_8N1	.EQU	SER_BAUD1800 | SER_DATA8 | SER_PARNONE | SER_STOP1
+SER_3600_8N1	.EQU	SER_BAUD3600 | SER_DATA8 | SER_PARNONE | SER_STOP1
+SER_7200_8N1	.EQU	SER_BAUD7200 | SER_DATA8 | SER_PARNONE | SER_STOP1
+SER_14400_8N1	.EQU	SER_BAUD14400 | SER_DATA8 | SER_PARNONE | SER_STOP1
+SER_28800_8N1	.EQU	SER_BAUD28800 | SER_DATA8 | SER_PARNONE | SER_STOP1
+SER_57600_8N1	.EQU	SER_BAUD57600 | SER_DATA8 | SER_PARNONE | SER_STOP1
+SER_115200_8N1	.EQU	SER_BAUD115200 | SER_DATA8 | SER_PARNONE | SER_STOP1
+SER_230400_8N1	.EQU	SER_BAUD230400 | SER_DATA8 | SER_PARNONE | SER_STOP1
+SER_460800_8N1	.EQU	SER_BAUD460800 | SER_DATA8 | SER_PARNONE | SER_STOP1
+SER_921600_8N1	.EQU	SER_BAUD921600 | SER_DATA8 | SER_PARNONE | SER_STOP1
+SER_1843200_8N1	.EQU	SER_BAUD1843200 | SER_DATA8 | SER_PARNONE | SER_STOP1
+SER_3686400_8N1	.EQU	SER_BAUD3686400 | SER_DATA8 | SER_PARNONE | SER_STOP1
+SER_7372800_8N1	.EQU	SER_BAUD7372800 | SER_DATA8 | SER_PARNONE | SER_STOP1
+;
+; TERMENABLE CONTROLS INCLUSION OF TERMINAL PSEUDO-DEVICE DRIVER
+; IT IS SET TO TRUE BY THE INCLUSION OF ANY VDA DRIVER.
+;
+TERMENABLE	.EQU	FALSE		; TERM PSEUDO DEVICE, WILL AUTO-ENABLE IF A VDA IS ENABLED
+;
+; VIDEO MODES
+;
+V80X24		.EQU	0	; ECB-VDU
+V80X25		.EQU	1	; ECB-VDU, ECB-VGA3
+V80X30		.EQU	2	; ECB-VDU, ECB-VGA3
+V80X25B		.EQU	3	; ECB-VDU
+V80X24B		.EQU	4	; ECB-VDU
+V80X43		.EQU	5	; ECB-VGA3
+V80X60		.EQU	6	; ECB-VGA3
+;
+; KEYBOARD LAYOUTS
+;
+KBD_US		.EQU	0	; US ENGLISH
+KBD_DE		.EQU	1	; GERMAN
+;
+; EMULATION TYPES
+;
+EMUTYP_NONE	.EQU	0		; NONE
+EMUTYP_TTY	.EQU	1		; TTY
+EMUTYP_ANSI	.EQU	2		; ANSI
+;
+; WATCHDOG TYPES
+;
+WDOG_NONE	.EQU	0		; NONE
+WDOG_EZZ80	.EQU	1		; EASY Z80 WATCHDOG
+WDOG_SKZ	.EQU	2		; SK Z80 CPU W/ 512K
+;
+#INCLUDE "build.inc"		; INCLUDE USER CONFIG, ADD VARIANT, TIMESTAMP, & ROMSIZE
+;
+#IF (BIOS == BIOS_WBW)
+#INCLUDE "hbios.inc"
+#ENDIF
+;
+#IF (BIOS == BIOS_UNA)
+#INCLUDE "../UBIOS/ubios.inc"
+#ENDIF
+;
+;
+; INCLUDE Z180 REGISTER DEFINITIONS
+;
+#IF (BIOS == BIOS_WBW)
+  #IF (CPUFAM == CPU_Z180)
+    #INCLUDE "z180.inc"
+  #ENDIF
+  #IF (CPUFAM == CPU_Z280)
+    #INCLUDE "z280.inc"
+  #ENDIF
+  #IF (EIPCENABLE)
+    #INCLUDE "eipc.inc"
+  #ENDIF
+#ENDIF
+;
+; SETUP DEFAULT CPU SPEED VALUES
+;
+CPUKHZ		.EQU	CPUOSC / 1000	; CPU FREQ IN KHZ
+;
+#IF (BIOS == BIOS_WBW)
+  #IF (CPUFAM == CPU_Z180)
+    #IF (Z180_CLKDIV == 0)
+CPUKHZ		.SET	CPUKHZ / 2	; ADJUST FOR HALF SPEED OPERATION
+    #ENDIF
+    #IF (Z180_CLKDIV == 2)
+CPUKHZ		.SET	CPUKHZ * 2	; ADJUST FOR DOUBLE SPEED OPERATION
+    #ENDIF
+  #ENDIF
+  #IF (CPUFAM == CPU_Z280)
+CPUKHZ		.SET	CPUKHZ / 2	; Z180 PHI IS ALWAYS 1/2 OSC
+  #ENDIF
+#ENDIF
+;
+CPUMHZ		.EQU	CPUKHZ / 1000	; CPU FREQ IN MHZ
+;
+; SYSTEM PERIODIC TIMER MODE
+;
+#IF (BIOS == BIOS_WBW)
+;
+TM_NONE	.EQU	0
+TM_CTC	.EQU	1
+TM_TMS	.EQU	2
+TM_SIMH	.EQU	3
+TM_Z180	.EQU	4
+TM_Z280	.EQU	5
+;
+	.ECHO "SYSTEM TIMER:"
+SYSTIM	.EQU	TM_NONE
+;
+  #IF (CTCENABLE & (INTMODE == 2))
+    #IF (CTCTIMER)
+SYSTIM	.SET	TM_CTC
+	.ECHO	" CTC"
+    #ENDIF
+  #ENDIF
+;
+  #IF (TMSENABLE & (INTMODE == 1))
+    #IF (TMSTIMENABLE)
+SYSTIM	.SET	TM_TMS
+	.ECHO	" TMS9918/V9958"
+    #ENDIF
+  #ENDIF
+;
+  #IF ((PLATFORM == PLT_SBC) & (INTMODE == 1))
+    #IF (HTIMENABLE)
+SYSTIM	.SET	TM_SIMH
+	.ECHO	" SIMH"
+    #ENDIF
+  #ENDIF
+;
+  #IF ((CPUFAM == CPU_Z180) & (INTMODE == 2))
+    #IF (Z180_TIMER)
+SYSTIM	.SET	TM_Z180
+	.ECHO	" Z180"
+    #ENDIF
+  #ENDIF
+;
+  #IF ((CPUFAM == CPU_Z280) & (MEMMGR == MM_Z280))
+    #IF (Z280_TIMER)
+SYSTIM	.SET	TM_Z280
+	.ECHO	" Z280"
+    #ENDIF
+  #ENDIF
+;
+  #IF SYSTIM == TM_NONE
+	.ECHO " NONE"
+  #ENDIF
+;
+	.ECHO	"\n"
+;
+#ENDIF
+;
+; MEMORY BANK CONFIGURATION
+;
+#IF (BIOS == BIOS_UNA)
+BID_ROM0	.EQU	$0000 + (ROM_RESERVE / 32)
+BID_RAM0	.EQU	$8000 + (RAM_RESERVE / 32)
+#ENDIF
+;
+#IF (BIOS == BIOS_WBW)
+BID_ROM0	.EQU	$00 + (ROM_RESERVE / 32)
+BID_RAM0	.EQU	$80 + (RAM_RESERVE / 32)
+#ENDIF
+
+BID_ROMN	.EQU	(BID_ROM0 + ((ROMSIZE / 32) - 1))
+BID_RAMN	.EQU	(BID_RAM0 + ((RAMSIZE / 32) - 1))
+
+BID_BOOT	.EQU	BID_ROM0	; BOOT BANK
+BID_IMG0	.EQU	BID_ROM0 + 1	; ROM LOADER AND FIRST IMAGES BANK
+BID_IMG1	.EQU	BID_ROM0 + 2	; SECOND IMAGES BANK
+;BID_FSFAT	.EQU	BID_ROM0 + 3	; FAT FILESYSTEM DRIVER BANK
+BID_IMG2	.EQU	BID_ROM0 + 3	; NETWORK BOOT
+BID_ROMD0	.EQU	BID_ROM0 + 4	; FIRST ROM DRIVE BANK
+BID_ROMDN	.EQU	BID_ROMN	; LAST ROM DRIVE BANK
+
+BID_RAMD0	.EQU	BID_RAM0	; FIRST RAM DRIVE BANK
+BID_RAMDN	.EQU	BID_RAMN - 4	; LAST RAM DRIVE BANK
+BID_AUX		.EQU	BID_RAMN - 3	; AUX BANK (BPBIOS, ETC.)
+BID_BIOS	.EQU	BID_RAMN - 2	; BIOS BANK
+BID_USR		.EQU	BID_RAMN - 1	; USER BANK (CP/M TPA, ETC.)
+BID_COM		.EQU	BID_RAMN	; COMMON BANK, UPPER 32K
+;
+; MEMORY LAYOUT
+;
+SYS_SIZ		.EQU	$3000			; COMBINED SIZE OF SYSTEM AREA (OS + HBIOS PROXY)
+HBBUF_SIZ	.EQU	1024			; INVARIANT HBIOS PHYSICAL DISK BUFFER, 1K
+HBX_SIZ		.EQU	$200			; HBIOS PROXY SIZE (SUBJECT TO CHANGE)
+CPM_SIZ		.EQU	SYS_SIZ - HBX_SIZ	; NET SIZE OF ALL OS COMPONENTS (EXCLUDING HBIOS PROXY)
+CCP_SIZ		.EQU	$800			; INVARIANT SIZE OF CCP
+BDOS_SIZ	.EQU	$E00			; INVARIANT SIZE OF BDOS
+CBIOS_SIZ	.EQU	CPM_SIZ - CCP_SIZ - BDOS_SIZ	; CBIOS IS THE REMAINDER
+
+MEMTOP		.EQU	$10000			; INVARIANT TOP OF Z80 ADDRESSABLE MEMORY
+BNKTOP		.EQU	$8000			; BANK MEMORY BARRIER
+
+HBX_IMG		.EQU	$200			; LOC OF HBX IMAGE IN HBIOS IMAGE BANK
+
+HBBUF_END	.EQU	BNKTOP			; END OF PHYSICAL DISK BUFFER IN HBIOS
+HBBUF_LOC	.EQU	HBBUF_END - HBBUF_SIZ	; START OF PHYSICAL DISK BUFFER
+HBX_END		.EQU	MEMTOP			; END OF HBIOS PROXY
+HBX_LOC		.EQU	HBX_END - HBX_SIZ	; START OF HBIOS PROXY
+CPM_END		.EQU	HBX_LOC			; END OF CPM COMPONENTS (INCLUDING CBIOS)
+CPM_LOC		.EQU	CPM_END - CPM_SIZ	; START OF CPM COMPONENTS
+CBIOS_END	.EQU	HBX_LOC			; END OF CBIOS
+CBIOS_LOC	.EQU	CBIOS_END - CBIOS_SIZ	; START OF CBIOS
+
+CPM_ENT		.EQU	CBIOS_LOC		; CPM ENTRY POINT (IN CBIOS)
+
+CPM_IMGSIZ	.EQU	$3000
+
+; ROM BANK 1
+
+LDR_LOC		.EQU	$0000
+LDR_SIZ		.EQU	$1000
+LDR_END		.EQU	LDR_LOC +LDR_SIZ
+LDR_IMGLOC	.EQU	$0000
+
+MON_LOC		.EQU	$EE00			; LOCATION OF MONITOR FOR RUNNING SYSTEM
+MON_SIZ		.EQU	$1000			; SIZE OF MONITOR BINARY IMAGE
+MON_END		.EQU	MON_LOC + MON_SIZ	; END OF MONITOR
+MON_IMGLOC	.EQU	LDR_IMGLOC + LDR_SIZ
+
+ZSYS_IMGLOC	.EQU	MON_IMGLOC + MON_SIZ
+
+CPM_IMGLOC	.EQU	ZSYS_IMGLOC + CPM_IMGSIZ
+
+; ROM BANK 2
+
+FTH_LOC		.EQU	$0200			; CAMEL FORTH
+FTH_SIZ		.EQU	$1700
+FTH_END		.EQU	FTH_LOC + FTH_SIZ
+FTH_IMGLOC	.EQU	$0000
+
+BAS_LOC		.EQU	$0200			; NASCOM BASIC
+BAS_SIZ		.EQU	$2000
+BAS_END		.EQU	BAS_LOC + BAS_SIZ
+BAS_IMGLOC	.EQU	FTH_IMGLOC + FTH_SIZ
+
+TBC_LOC		.EQU	$0A00			; TASTYBASIC
+TBC_SIZ		.EQU	$0900
+TBC_END		.EQU	TBC_LOC + TBC_SIZ
+TBC_IMGLOC	.EQU	BAS_IMGLOC + BAS_SIZ
+
+GAM_LOC		.EQU	$0200			; GAME 2048
+GAM_SIZ		.EQU	$0900
+GAM_END		.EQU	GAM_LOC + GAM_SIZ
+GAM_IMGLOC	.EQU	TBC_IMGLOC + TBC_SIZ
+
+EGG_LOC		.EQU	$F000			; EASTER EGG
+EGG_SIZ		.EQU	$0200
+EGG_END		.EQU	EGG_LOC + EGG_SIZ
+EGG_IMGLOC	.EQU	GAM_IMGLOC + GAM_SIZ
+
+NET_LOC		.EQU	$0100			; NETWORK BOOT
+NET_SIZ		.EQU	$1000
+NET_END		.EQU	NET_LOC + NET_SIZ
+NET_IMGLOC	.EQU	EGG_IMGLOC + EGG_SIZ
+
+UPD_LOC		.EQU	$0200			; ROM UPDATER
+UPD_SIZ		.EQU	$0D00
+UPD_END		.EQU	UPD_LOC + UPD_SIZ
+UPD_IMGLOC	.EQU	NET_IMGLOC + NET_SIZ
+
+USR_LOC		.EQU	$0200			; USER
+USR_SIZ		.EQU	BNKTOP - UPD_IMGLOC - UPD_SIZ
+USR_END		.EQU	USR_LOC + USR_SIZ
+USR_IMGLOC	.EQU	UPD_IMGLOC + UPD_SIZ
+
+MON_DSKY	.EQU	MON_LOC + (0 * 3)	; MONITOR ENTRY (DSKY)
+MON_SERIAL	.EQU	MON_LOC + (1 * 3)	; MONITOR ENTRY (SERIAL PORT)
+;
+; INTERRUPT MODE 2 SLOT ASSIGNMENTS
+;
+#IF ((INTMODE == 2) | (INTMODE == 3))
+
+  #IF ((CPUFAM == CPU_Z180) | (CPUFAM == CPU_Z280))
+
+; Z180-BASED SYSTEMS
+
+INT_INT1	.EQU	0	; Z180 INT 1
+INT_INT2	.EQU	1	; Z180 INT 2
+INT_TIM0	.EQU	2	; Z180 TIMER 0
+INT_TIM1	.EQU	3	; Z180 TIMER 1
+INT_DMA0	.EQU	4	; Z180 DMA 0
+INT_DMA1	.EQU	5	; Z180 DMA 1
+INT_CSIO	.EQU	6	; Z180 CSIO
+INT_SER0	.EQU	7	; Z180 SERIAL 0
+INT_SER1	.EQU	8	; Z180 SERIAL 0
+INT_PIO0A	.EQU	9	; ZILOG PIO 0, CHANNEL A
+INT_PIO0B	.EQU	10	; ZILOG PIO 0, CHANNEL B
+INT_PIO1A	.EQU	11	; ZILOG PIO 1, CHANNEL A
+INT_PIO1B	.EQU	12	; ZILOG PIO 1, CHANNEL B
+INT_SIO0	.EQU	13	; ZILOG SIO 0, CHANNEL A & B
+INT_SIO1	.EQU	14	; ZILOG SIO 1, CHANNEL A & B
+
+  #ELSE
+
+; Z80-BASED SYSTEMS
+
+INT_CTC0A	.EQU	0	; ZILOG CTC 0, CHANNEL A
+INT_CTC0B	.EQU	1	; ZILOG CTC 0, CHANNEL B
+INT_CTC0C	.EQU	2	; ZILOG CTC 0, CHANNEL C
+INT_CTC0D	.EQU	3	; ZILOG CTC 0, CHANNEL D
+INT_UART0	.EQU	4	; MBC UART 0
+INT_UART1	.EQU	5	; MBC UART 1
+INT_SIO0	.EQU	7	; ZILOG SIO 0, CHANNEL A & B
+INT_SIO1	.EQU	8	; ZILOG SIO 1, CHANNEL A & B
+INT_PIO0A	.EQU	9	; ZILOG PIO 0, CHANNEL A
+INT_PIO0B	.EQU	10	; ZILOG PIO 0, CHANNEL B
+INT_PIO1A	.EQU	11	; ZILOG PIO 1, CHANNEL A
+INT_PIO1B	.EQU	12	; ZILOG PIO 1, CHANNEL B
+
+  #ENDIF
+
+#DEFINE IVT(INTX) HB_IVT+(INTX * 4)+1
+#DEFINE VEC(INTX) INTX*2
+
+#ENDIF
+
+; SET DEFAULT CSIO SPEED (INTERNAL CLOCK, SLOW AS POSSIBLE)
+; DIV 1280, 14KHZ @ 18MHZ CLK
+
+#IF (BIOS == BIOS_WBW)
+  #IF (CPUFAM == CPU_Z180)
+Z180_CNTR_DEF	.EQU	$06	; DEFAULT VALUE FOR Z180 CSIO CONFIG
+  #ENDIF
+#ENDIF
+
+;
+; HELPER MACROS
+;
+#DEFINE	PRTC(C)	CALL PRTCH \ .DB C			; PRINT CHARACTER C TO CONSOLE - PRTC('X')
+#DEFINE	PRTS(S)	CALL PRTSTRD \ .TEXT S			; PRINT STRING S TO CONSOLE - PRTD("HELLO")
+#DEFINE	PRTX(X) CALL PRTSTRI \ .DW X			; PRINT STRING AT ADDRESS X TO CONSOLE - PRTI(STR_HELLO)
+#DEFINE DEBUG(S) CALL PRTSTRD \ .TEXT S \ .TEXT "$"	; $$$$$$ PRINT STRING S TO CONSOLE - PRTD("HELLO") - NO TRAILING $ REQUIRED
+;
+#DEFINE	XIO_PRTC(C)	CALL XIO_PRTCH \ .DB C		; PRINT CHARACTER C TO CONSOLE - PRTC('X')
+#DEFINE	XIO_PRTS(S)	CALL XIO_PRTSTRD \ .DB S	; PRINT STRING S TO CONSOLE - PRTD("HELLO")
+#DEFINE	XIO_PRTX(X)	CALL XIO_PRTSTRI \ .DW X	; PRINT STRING AT ADDRESS X TO CONSOLE - PRTI(STR_HELLO)
--- a/Source/Apps/TEST/DMAmon/util.asm
+++ b/Source/Apps/TEST/DMAmon/util.asm
@ -0,0 +1,969 @@
+;
+;==================================================================================================
+; UTILITY FUNCTIONS
+;==================================================================================================
+;
+;
+CHR_BEL		.EQU	07H
+CHR_CR		.EQU	0DH
+CHR_LF		.EQU	0AH
+CHR_BS		.EQU	08H
+CHR_ESC		.EQU	1BH
+;
+;__________________________________________________________________________________________________
+;
+; UTILITY PROCS TO PRINT SINGLE CHARACTERS WITHOUT TRASHING ANY REGISTERS
+;
+PC_SPACE:
+	PUSH	AF
+	LD	A,' '
+	JR	PC_PRTCHR
+
+PC_PERIOD:
+	PUSH	AF
+	LD	A,'.'
+	JR	PC_PRTCHR
+
+PC_COLON:
+	PUSH	AF
+	LD	A,':'
+	JR	PC_PRTCHR
+
+PC_COMMA:
+	PUSH	AF
+	LD	A,','
+	JR	PC_PRTCHR
+
+PC_LBKT:
+	PUSH	AF
+	LD	A,'['
+	JR	PC_PRTCHR
+
+PC_RBKT:
+	PUSH	AF
+	LD	A,']'
+	JR	PC_PRTCHR
+
+PC_LT:
+	PUSH	AF
+	LD	A,'<'
+	JR	PC_PRTCHR
+
+PC_GT:
+	PUSH	AF
+	LD	A,'>'
+	JR	PC_PRTCHR
+
+PC_LPAREN:
+	PUSH	AF
+	LD	A,'('
+	JR	PC_PRTCHR
+
+PC_RPAREN:
+	PUSH	AF
+	LD	A,')'
+	JR	PC_PRTCHR
+
+PC_ASTERISK:
+	PUSH	AF
+	LD	A,'*'
+	JR	PC_PRTCHR
+
+PC_CR:
+	PUSH	AF
+	LD	A,CHR_CR
+	JR	PC_PRTCHR
+
+PC_LF:
+	PUSH	AF
+	LD	A,CHR_LF
+	JR	PC_PRTCHR
+
+PC_PRTCHR:
+	CALL	COUT
+	POP	AF
+	RET
+
+NEWLINE2:
+	CALL	NEWLINE
+NEWLINE:
+	CALL	PC_CR
+	CALL	PC_LF
+	RET
+;
+; PRINT A CHARACTER REFERENCED BY POINTER AT TOP OF STACK
+; USAGE:
+;   CALL PRTCH
+;   .DB  'X'
+;
+PRTCH:
+	EX	(SP),HL
+	PUSH	AF
+	LD	A,(HL)
+	CALL	COUT
+	POP	AF
+	INC	HL
+	EX	(SP),HL
+	RET
+;
+; PRINT A STRING AT ADDRESS SPECIFIED IN HL
+; STRING MUST BE TERMINATED BY '$'
+; USAGE:
+;   LD	HL,MYSTR
+;   CALL PRTSTR
+;   ...
+;   MYSTR: .DB  "HELLO$"
+;
+PRTSTR:
+	LD	A,(HL)
+	INC	HL
+	CP	'$'
+	RET	Z
+	CALL	COUT
+	JR	PRTSTR
+;
+; PRINT A STRING DIRECT: REFERENCED BY POINTER AT TOP OF STACK
+; STRING MUST BE TERMINATED BY '$'
+; USAGE:
+;   CALL PRTSTRD
+;   .DB  "HELLO$"
+;   ...
+;
+PRTSTRD:
+	EX	(SP),HL
+	PUSH	AF
+	CALL	PRTSTR
+	POP	AF
+	EX	(SP),HL
+	RET
+;
+; PRINT A STRING INDIRECT: REFERENCED BY INDIRECT POINTER AT TOP OF STACK
+; STRING MUST BE TERMINATED BY '$'
+; USAGE:
+;   CALL PRTSTRI(MYSTRING)
+;   MYSTRING	.DB	"HELLO$"
+;
+PRTSTRI:
+	EX	(SP),HL
+	PUSH	AF
+	LD	A,(HL)
+	INC	HL
+	PUSH	HL
+	LD	H,(HL)
+	LD	L,A
+	CALL	PRTSTR
+	POP	HL
+	INC	HL
+	POP	AF
+	EX	(SP),HL
+	RET
+;
+; PRINT THE HEX BYTE VALUE IN A
+;
+PRTHEXBYTE:
+	PUSH	AF
+	PUSH	DE
+	CALL	HEXASCII
+	LD	A,D
+	CALL	COUT
+	LD	A,E
+	CALL	COUT
+	POP	DE
+	POP	AF
+	RET
+;
+; PRINT THE HEX WORD VALUE IN BC
+;
+PRTHEXWORD:
+	PUSH	AF
+	LD	A,B
+	CALL	PRTHEXBYTE
+	LD	A,C
+	CALL	PRTHEXBYTE
+	POP	AF
+	RET
+;
+; PRINT THE HEX WORD VALUE IN HL
+;
+PRTHEXWORDHL:
+	PUSH	AF
+	LD	A,H
+	CALL	PRTHEXBYTE
+	LD	A,L
+	CALL	PRTHEXBYTE
+	POP	AF
+	RET
+;
+; PRINT THE HEX DWORD VALUE IN DE:HL
+;
+PRTHEX32:
+	PUSH	BC
+	PUSH	DE
+	POP	BC
+	CALL	PRTHEXWORD
+	PUSH	HL
+	POP	BC
+	CALL	PRTHEXWORD
+	POP	BC
+	RET
+;
+; CONVERT BINARY VALUE IN A TO ASCII HEX CHARACTERS IN DE
+;
+HEXASCII:
+	LD	D,A
+	CALL	HEXCONV
+	LD	E,A
+	LD	A,D
+	RLCA
+	RLCA
+	RLCA
+	RLCA
+	CALL	HEXCONV
+	LD	D,A
+	RET
+;
+; CONVERT LOW NIBBLE OF A TO ASCII HEX
+;
+HEXCONV:
+	AND	0FH	     ;LOW NIBBLE ONLY
+	ADD	A,90H
+	DAA
+	ADC	A,40H
+	DAA
+	RET
+;
+; PRINT A BYTE BUFFER IN HEX POINTED TO BY DE
+; REGISTER A HAS SIZE OF BUFFER
+;
+PRTHEXBUF:
+	OR	A
+	RET	Z		; EMPTY BUFFER
+;
+	LD	B,A
+PRTHEXBUF1:
+	CALL	PC_SPACE
+	LD	A,(DE)
+	CALL	PRTHEXBYTE
+	INC	DE
+	DJNZ	PRTHEXBUF1
+	RET
+;
+; PRINT A BLOCK OF MEMORY NICELY FORMATTED
+;  DE=BUFFER ADDRESS
+;
+DUMP_BUFFER:
+	CALL	NEWLINE
+
+	PUSH	DE
+	POP	HL
+	INC	D
+	INC	D
+
+DB_BLKRD:
+	PUSH	BC
+	PUSH	HL
+	POP	BC
+	CALL	PRTHEXWORD		; PRINT START LOCATION
+	POP	BC
+	CALL	PC_SPACE		;
+	LD	C,16			; SET FOR 16 LOCS
+	PUSH	HL			; SAVE STARTING HL
+DB_NXTONE:
+	LD	A,(HL)			; GET BYTE
+	CALL	PRTHEXBYTE		; PRINT IT
+	CALL	PC_SPACE		;
+DB_UPDH:
+	INC	HL			; POINT NEXT
+	DEC	C			; DEC. LOC COUNT
+	JR	NZ,DB_NXTONE		; IF LINE NOT DONE
+					; NOW PRINT 'DECODED' DATA TO RIGHT OF DUMP
+DB_PCRLF:
+	CALL	PC_SPACE		; SPACE IT
+	LD	C,16			; SET FOR 16 CHARS
+	POP	HL			; GET BACK START
+DB_PCRLF0:
+	LD	A,(HL)			; GET BYTE
+	AND	060H			; SEE IF A 'DOT'
+	LD	A,(HL)			; O.K. TO GET
+	JR	NZ,DB_PDOT		;
+DB_DOT:
+	LD	A,2EH			; LOAD A DOT
+DB_PDOT:
+	CALL	COUT			; PRINT IT
+	INC	HL			;
+	LD	A,D			;
+	CP	H			;
+	JR	NZ,DB_UPDH1		;
+	LD	A,E			;
+	CP	L			;
+	JP	Z,DB_END		;
+DB_UPDH1:
+; IF BLOCK NOT DUMPED, DO NEXT CHARACTER OR LINE
+	DEC	C			; DEC. CHAR COUNT
+	JR	NZ,DB_PCRLF0		; DO NEXT
+DB_CONTD:
+	CALL	NEWLINE			;
+	JP	DB_BLKRD		;
+
+DB_END:
+	RET
+;
+; PRINT THE nTH STRING IN A LIST OF STRINGS WHERE EACH IS TERMINATED BY $
+; C REGISTER CONTAINS THE INDEX TO THE STRING TO BE DISPLAYED.
+; A REGISTER CONTAINS A MASK TO BE APPLIED TO THE INDEX
+; THE INDEX IS NORMALIZED TO A RANGE 0..N USING THE MASK AND THEN THE nTH
+; STRING IS PRINTED IN A LIST DEFINED BY DE
+;
+; C = ATTRIBUTE
+; A = MASK
+; DE = STRING LIST
+;
+PRTIDXMSK:
+	PUSH	BC
+PRTIDXMSK0:
+	BIT	0,A
+	JR	NZ,PRTIDXMSK1
+	SRL	A
+	SRL	C
+	JR	PRTIDXMSK0
+PRTIDXMSK1:
+	LD	B,A
+	LD	A,C
+	AND	B
+	POP	BC
+;
+; PRINT THE nTH STRING IN A LIST OF STRINGS WHERE EACH IS TERMINATED BY $
+; A REGISTER DEFINES THE nTH STRING IN THE LIST TO PRINT AND DE POINTS
+; TO THE START OF THE STRING LIST.
+;
+; SLOW BUT IMPROVES CODE SIZE, READABILITY AND ELIMINATES THE NEED HAVE
+; LIST OF POINTERS OR A LIST OF CONDITIONAL CHECKS.
+;
+PRTIDXDEA:
+	PUSH	BC
+	LD	C,A			; INDEX COUNT
+	OR	A
+	LD	A,0
+	LD	(PRTIDXCNT),A		; RESET CHARACTER COUNT
+PRTIDXDEA1:
+	JR	Z,PRTIDXDEA3
+PRTIDXDEA2:
+	LD	A,(DE)			; LOOP UNIT
+	INC	DE			; WE REACH
+	CP	'$'			; END OF STRING
+	JR	NZ,PRTIDXDEA2
+	DEC	C			; AT STRING END. SO GO
+	JR	PRTIDXDEA1		; CHECK FOR INDEX MATCH
+PRTIDXDEA3:
+	POP	BC
+;	CALL	WRITESTR		; FALL THROUGH TO WRITESTR
+;	RET
+;
+; OUTPUT A '$' TERMINATED STRING AT DE
+;
+WRITESTR:
+	PUSH	AF
+WRITESTR1:
+	LD	A,(DE)
+	CP	'$'			; TEST FOR STRING TERMINATOR
+	JP	Z,WRITESTR2
+	CALL	COUT
+	LD	A,(PRTIDXCNT)
+	INC	A
+	LD	(PRTIDXCNT),A
+	INC	DE
+	JP	WRITESTR1
+WRITESTR2:
+	POP	AF
+	RET
+;
+PRTIDXCNT:
+	.DB	0			; CHARACTER COUNT
+;
+;
+;
+TSTPT:
+	PUSH	DE
+	LD	DE,STR_TSTPT
+	CALL	WRITESTR
+	POP	DE
+	JR	REGDMP			; DUMP REGISTERS AND RETURN
+;
+;
+;
+REGDMP:
+	CALL	XREGDMP
+	RET
+;
+XREGDMP:
+	EX	(SP),HL			; RET ADR TO HL, SAVE HL ON TOS
+	LD	(REGDMP_RET),HL		; SAVE RETURN ADDRESS
+	POP	HL			; RESTORE HL AND BURN STACK ENTRY
+
+	EX	(SP),HL			; PC TO HL, SAVE HL ON TOS
+	LD	(REGDMP_PC),HL		; SAVE PC VALUE
+	EX	(SP),HL			; BACK THE WAY IT WAS
+
+	LD	(REGDMP_SP),SP		; SAVE STACK POINTER
+
+	;LD	(RD_STKSAV),SP		; SAVE ORIGINAL STACK POINTER
+	;LD	SP,RD_STACK		; SWITCH TO PRIVATE STACK
+
+	PUSH	AF
+	PUSH	BC
+	PUSH	DE
+	PUSH	HL
+
+	PUSH	AF
+	LD	A,'@'
+	CALL	COUT
+	POP	AF
+
+	PUSH	BC
+	LD	BC,(REGDMP_PC)
+	CALL	PRTHEXWORD		; PC
+	POP	BC
+	CALL	PC_LBKT
+	PUSH	BC
+	PUSH	AF
+	POP	BC
+	CALL	PRTHEXWORD		; AF
+	POP	BC
+	CALL	PC_COLON
+	CALL	PRTHEXWORD		; BC
+	CALL	PC_COLON
+	PUSH	DE
+	POP	BC
+	CALL	PRTHEXWORD		; DE
+	CALL	PC_COLON
+	PUSH	HL
+	POP	BC
+	CALL	PRTHEXWORD		; HL
+	CALL	PC_COLON
+	LD	BC,(REGDMP_SP)
+	CALL	PRTHEXWORD		; SP
+
+	CALL	PC_COLON
+	PUSH	IX
+	POP	BC
+	CALL	PRTHEXWORD		; IX
+
+	CALL	PC_COLON
+	PUSH	IY
+	POP	BC
+	CALL	PRTHEXWORD		; IY
+
+	CALL	PC_RBKT
+	CALL	PC_SPACE
+
+	POP	HL
+	POP	DE
+	POP	BC
+	POP	AF
+
+	;LD	SP,(RD_STKSAV)		; BACK TO ORIGINAL STACK FRAME
+
+	JP	$FFFF			; RETURN, $FFFF IS DYNAMICALLY UPDATED
+REGDMP_RET	.EQU	$-2		; RETURN ADDRESS GOES HERE
+;
+REGDMP_PC	.DW	0
+REGDMP_SP	.DW	0
+;
+;RD_STKSAV	.DW	0
+;		.FILL	$FF,16*2	; 16 LEVEL PRIVATE STACK
+;RD_STACK	.EQU	$
+;
+;
+;
+;
+;
+STR_HALT	.TEXT	"\r\n\r\n*** System Halted ***$"
+STR_TSTPT	.TEXT	"\r\n+++ TSTPT: $"
+;STR_AF		.DB	" AF=$"
+;STR_BC		.DB	" BC=$"
+;STR_DE		.DB	" DE=$"
+;STR_HL		.DB	" HL=$"
+;STR_PC		.DB	" PC=$"
+;STR_SP		.DB	" SP=$"
+;
+; INDIRECT JUMP TO ADDRESS IN HL
+;
+;   MOSTLY USEFUL TO PERFORM AN INDIRECT CALL LIKE:
+;     LD	HL,xxxx
+;     CALL	JPHL
+;
+JPHL:	JP	(HL)
+;
+; ADD HL,A
+;
+;   A REGISTER IS DESTROYED!
+;
+ADDHLA:
+	ADD	A,L
+	LD	L,A
+	RET	NC
+	INC	H
+	RET
+;
+;****************************
+;	A(BCD) => A(BIN)
+;	[00H..99H] -> [0..99]
+;****************************
+;
+BCD2BYTE:
+	PUSH	BC
+	LD	C,A
+	AND	0F0H
+	SRL	A
+	LD	B,A
+	SRL	A
+	SRL	A
+	ADD	A,B
+	LD	B,A
+	LD	A,C
+	AND	0FH
+	ADD	A,B
+	POP	BC
+	RET
+;
+;*****************************
+;	 A(BIN) =>  A(BCD)
+;	[0..99] => [00H..99H]
+;*****************************
+;
+BYTE2BCD:
+	PUSH	BC
+	LD	B,10
+	LD	C,-1
+BYTE2BCD1:
+	INC	C
+	SUB	B
+	JR	NC,BYTE2BCD1
+	ADD	A,B
+	LD	B,A
+	LD	A,C
+	ADD	A,A
+	ADD	A,A
+	ADD	A,A
+	ADD	A,A
+	OR	B
+	POP	BC
+	RET
+
+#IFDEF USEDELAY
+
+;
+; DELAY 16US (CPU SPEED COMPENSATED) INCUDING CALL/RET INVOCATION
+; REGISTER A AND FLAGS DESTROYED
+; NO COMPENSATION FOR Z180 MEMORY WAIT STATES
+; THERE IS AN OVERHEAD OF 3TS PER INVOCATION
+;   IMPACT OF OVERHEAD DIMINISHES AS CPU SPEED INCREASES
+;
+; CPU SCALER (CPUSCL) = (CPUHMZ - 2) FOR 16US + 3TS DELAY
+;   NOTE: CPUSCL MUST BE >= 1!
+;
+; EXAMPLE: 8MHZ CPU (DELAY GOAL IS 16US)
+;   LOOP = ((6 * 16) - 5) = 91TS
+;   TOTAL COST = (91 + 40) = 131TS
+;   ACTUAL DELAY = (131 / 8) = 16.375US
+;
+	; --- TOTAL COST = (LOOP COST + 40) TS -----------------+
+DELAY:				; 17TS (FROM INVOKING CALL)	|
+	LD	A,(CPUSCL)	; 13TS				|
+;								|
+DELAY1:				;				|
+	; --- LOOP = ((CPUSCL * 16) - 5) TS ------------+	|
+	DEC	A		; 4TS			|	|
+  #IF (BIOS == BIOS_WBW)	;			|	|
+    #IF (CPUFAM == CPU_Z180)	;			|	|
+	OR	A		; +4TS FOR Z180		|	|
+    #ENDIF			;			|	|
+  #ENDIF			;			|	|
+	JR	NZ,DELAY1	; 12TS (NZ) / 7TS (Z)	|	|
+	; ----------------------------------------------+	|
+;								|
+	RET			; 10TS (RETURN)			|
+	;-------------------------------------------------------+
+;
+; DELAY 16US * DE (CPU SPEED COMPENSATED)
+; REGISTER DE, A, AND FLAGS DESTROYED
+; NO COMPENSATION FOR Z180 MEMORY WAIT STATES
+; THERE IS A 27TS OVERHEAD FOR CALL/RET PER INVOCATION
+;   IMPACT OF OVERHEAD DIMINISHES AS DE AND/OR CPU SPEED INCREASES
+;
+; CPU SCALER (CPUSCL) = (CPUHMZ - 2) FOR 16US OUTER LOOP COST
+;   NOTE: CPUSCL MUST BE > 0!
+;
+; EXAMPLE: 8MHZ CPU, DE=6250 (DELAY GOAL IS .1 SEC OR 100,000US)
+;   INNER LOOP = ((16 * 6) - 5) = 91TS
+;   OUTER LOOP = ((91 + 37) * 6250) = 800,000TS
+;   ACTUAL DELAY = ((800,000 + 27) / 8) = 100,003US
+;
+	; --- TOTAL COST = (OUTER LOOP + 27) TS ------------------------+
+VDELAY:				; 17TS (FROM INVOKING CALL)		|
+;									|
+	; --- OUTER LOOP = ((INNER LOOP + 37) * DE) TS ---------+	|
+	LD	A,(CPUSCL)	; 13TS				|	|
+;								|	|
+VDELAY1:			;				|	|
+	; --- INNER LOOP = ((CPUSCL * 16) - 5) TS ------+	|	|
+  #IF (BIOS == BIOS_WBW)	;			|	|	|
+    #IF (CPUFAM == CPU_Z180)	;			|	|	|
+	OR	A		; +4TS FOR Z180		|	|	|
+    #ENDIF			;			|	|	|
+  #ENDIF			;			|	|	|
+	DEC	A		; 4TS			|	|	|
+	JR	NZ,VDELAY1	; 12TS (NZ) / 7TS (Z)	|	|	|
+	; ----------------------------------------------+	|	|
+;								|	|
+	DEC	DE		; 6TS				|	|
+  #IF (BIOS == BIOS_WBW)	;			|	|	|
+    #IF (CPUFAM == CPU_Z180)	;				|	|
+	OR	A		; +4TS FOR Z180			|	|
+    #ENDIF			;				|	|
+  #ENDIF			;				|	|
+	LD	A,D		; 4TS				|	|
+	OR	E		; 4TS				|	|
+	JP	NZ,VDELAY	; 10TS				|	|
+	;-------------------------------------------------------+	|
+;									|
+	RET			; 10TS (FINAL RETURN)			|
+	;---------------------------------------------------------------+
+;
+; DELAY ABOUT 0.5 SECONDS
+; 500000US / 16US = 31250
+;
+LDELAY:
+	PUSH	AF
+	PUSH	DE
+	LD	DE,31250
+	CALL	VDELAY
+	POP	DE
+	POP	AF
+	RET
+;
+; INITIALIZE DELAY SCALER BASED ON OPERATING CPU SPEED
+; ENTER WITH A = CPU SPEED IN MHZ
+;
+DELAY_INIT:
+	CP	3			; TEST FOR <= 2 (SPECIAL HANDLING)
+	JR	C,DELAY_INIT1		; IF <= 2, SPECIAL PROCESSING
+	SUB	2			; ADJUST AS REQUIRED BY DELAY FUNCTIONS
+	JR	DELAY_INIT2		; AND CONTINUE
+DELAY_INIT1:
+	LD	A,1			; USE THE MIN VALUE OF 1
+DELAY_INIT2:
+	LD	(CPUSCL),A		; UPDATE CPU SCALER VALUE
+	RET
+
+  #IF (CPUMHZ < 3)
+CPUSCL	.DB	1			; CPU SCALER MUST BE > 0
+  #ELSE
+CPUSCL	.DB	CPUMHZ - 2		; OTHERWISE 2 LESS THAN PHI MHZ
+  #ENDIF
+;
+#ENDIF
+;
+; SHORT DELAY FUNCTIONS.  NO CLOCK SPEED COMPENSATION, SO THEY
+; WILL RUN LONGER ON SLOWER SYSTEMS.  THE NUMBER INDICATES THE
+; NUMBER OF CALL/RET INVOCATIONS.  A SINGLE CALL/RET IS
+; 27 T-STATES ON A Z80, 25 T-STATES ON A Z180
+;
+;			; Z80	Z180
+;			; ----	----
+DLY64:	CALL	DLY32	; 1728	1600
+DLY32:	CALL	DLY16	; 864	800
+DLY16:	CALL	DLY8	; 432	400
+DLY8:	CALL	DLY4	; 216	200
+DLY4:	CALL	DLY2	; 108	100
+DLY2:	CALL	DLY1	; 54	50
+DLY1:	RET		; 27	25
+;
+; MULTIPLY 8-BIT VALUES
+; IN:  MULTIPLY H BY E
+; OUT: HL = RESULT, E = 0, B = 0
+;
+MULT8:
+	LD D,0
+	LD L,D
+	LD B,8
+MULT8_LOOP:
+	ADD HL,HL
+	JR NC,MULT8_NOADD
+	ADD HL,DE
+MULT8_NOADD:
+	DJNZ MULT8_LOOP
+	RET
+;
+; MULTIPLY A 16 BIT BY 8 BIT INTO 16 BIT
+; IN: MULTIPLY DE BY A
+; OUT: HL = RESULT, B=0, A, C, DE UNCHANGED
+;
+MULT8X16:
+	LD	B,8
+	LD	HL,0
+MULT8X16_1:
+	ADD	HL,HL
+	RLCA
+	JR	NC,MULT8X16_2
+	ADD	HL,DE
+MULT8X16_2:
+	DJNZ	MULT8X16_1
+	RET
+;;
+;; COMPUTE HL / DE
+;; RESULT IN BC, REMAINDER IN HL, AND SET ZF DEPENDING ON REMAINDER
+;; A, DE DESTROYED
+;;
+;DIV:
+;	XOR	A
+;	LD	BC,0
+;DIV1:
+;	SBC	HL,DE
+;	JR	C,DIV2
+;	INC	BC
+;	JR	DIV1
+;DIV2:
+;	XOR	A
+;	ADC	HL,DE		; USE ADC SO ZF IS SET
+;	RET
+;===============================================================
+;
+; COMPUTE HL / DE = BC W/ REMAINDER IN HL & ZF
+;
+DIV16:
+	LD	A,H			; HL -> AC
+	LD	C,L			; ...
+	LD	HL,0			; INIT HL
+	LD	B,16			; INIT LOOP COUNT
+DIV16A:
+	SCF
+	RL	C
+	RLA
+	ADC	HL,HL
+	SBC	HL,DE
+	JR	NC,DIV16B
+	ADD	HL,DE
+	DEC	C
+DIV16B:
+	DJNZ	DIV16A			; LOOP AS NEEDED
+	LD	B,A			; AC -> BC
+	LD	A,H			; SET ZF
+	OR	L			; ... BASED ON REMAINDER
+	RET				; DONE
+;
+; INTEGER DIVIDE DE:HL BY C
+; RESULT IN DE:HL, REMAINDER IN A
+; CLOBBERS F, B
+;
+DIV32X8:
+	XOR	A
+	LD	B,32
+DIV32X8A:
+ 	ADD	HL,HL
+	RL	E
+	RL	D
+	RLA
+	CP	C
+	JR	C,DIV32X8B
+	SUB	C
+	INC	L
+DIV32X8B:
+ 	DJNZ	DIV32X8A
+	RET
+;
+; FILL MEMORY AT HL WITH VALUE A, LENGTH IN BC, ALL REGS USED
+; LENGTH *MUST* BE GREATER THAN 1 FOR PROPER OPERATION!!!
+;
+FILL:
+	LD	D,H		; SET DE TO HL
+	LD	E,L		; SO DESTINATION EQUALS SOURCE
+	LD	(HL),A		; FILL THE FIRST BYTE WITH DESIRED VALUE
+	INC	DE		; INCREMENT DESTINATION
+	DEC	BC		; DECREMENT THE COUNT
+	LDIR			; DO THE REST
+	RET			; RETURN
+;
+; SET A BIT IN BYTE ARRAY AT HL, INDEX IN A
+;
+BITSET:
+	CALL	BITLOC		; LOCATE THE BIT
+	OR	(HL)		; SET THE SPECIFIED BIT
+	LD	(HL),A		; SAVE IT
+	RET			; RETURN
+;
+; CLEAR A BIT IN BYTE ARRAY AT HL, INDEX IN A
+;
+BITCLR:
+	CALL	BITLOC		; LOCATE THE BIT
+	CPL			; INVERT ALL BITS
+	AND	(HL)		; CLEAR SPECIFIED BIT
+	LD	(HL),A		; SAVE IT
+	RET			; RETURN
+;
+; GET VALUE OF A BIT IN BYTE ARRAY AT HL, INDEX IN A
+;
+BITTST:
+	CALL	BITLOC		; LOCATE THE BIT
+	AND	(HL)		; SET Z FLAG BASED ON BIT
+	RET			; RETURN
+;
+; LOCATE A BIT IN BYTE ARRAY AT HL, INDEX IN A
+; RETURN WITH HL POINTING TO BYTE AND A WITH MASK FOR SPECIFIC BIT
+;
+BITLOC:
+	PUSH	AF		; SAVE BIT INDEX
+	SRL	A		; DIVIDE BY 8 TO GET BYTE INDEX
+	SRL	A		; "
+	SRL	A		; "
+	LD	C,A		; MOVE TO BC
+	LD	B,0		; "
+	ADD	HL,BC		; HL NOW POINTS TO BYTE CONTAINING BIT
+	POP	AF		; RECOVER A (INDEX)
+	AND	$07		; ISOLATE REMAINDER, Z SET IF ZERO
+	LD	B,A		; SETUP SHIFT COUNTER
+	LD	A,1		; SETUP A WITH MASK
+	RET	Z		; DONE IF ZERO
+BITLOC1:
+	SLA	A		; SHIFT
+	DJNZ	BITLOC1		; LOOP AS NEEDED
+	RET			; DONE
+;
+; PRINT VALUE OF A IN DECIMAL WITH LEADING ZERO SUPPRESSION
+;
+PRTDECB:
+	PUSH	HL
+	PUSH	AF
+	LD	L,A
+	LD	H,0
+	CALL	PRTDEC
+	POP	AF
+	POP	HL
+	RET
+;
+; PRINT VALUE OF HL IN DECIMAL WITH LEADING ZERO SUPPRESSION
+;
+PRTDEC:
+	PUSH	BC
+	PUSH	DE
+	PUSH	HL
+	LD	E,'0'
+	LD	BC,-10000
+	CALL	PRTDEC1
+	LD	BC,-1000
+	CALL	PRTDEC1
+	LD	BC,-100
+	CALL	PRTDEC1
+	LD	C,-10
+	CALL	PRTDEC1
+	LD	E,0
+	LD	C,-1
+	CALL	PRTDEC1
+	POP	HL
+	POP	DE
+	POP	BC
+	RET
+PRTDEC1:
+	LD	A,'0' - 1
+PRTDEC2:
+	INC	A
+	ADD	HL,BC
+	JR	C,PRTDEC2
+	SBC	HL,BC
+	CP	E
+	JR	Z,PRTDEC3
+	LD	E,0
+	CALL	COUT
+PRTDEC3:
+	RET
+;
+; SHIFT HL:DE BY B BITS
+;
+SRL32:
+	; ROTATE RIGHT 32 BITS, HIGH ORDER BITS BECOME ZERO
+	SRL	D
+	RR	E
+	RR	H
+	RR	L
+	DJNZ	SRL32
+	RET
+;
+SLA32:
+	; ROTATE LEFT 32 BITS, LOW ORDER BITS BECOME ZERO
+	SLA	L
+	RL	H
+	RL	E
+	RL	D
+	DJNZ	SLA32
+	RET
+;
+; LOAD OR STORE DE:HL
+;
+LD32:
+	; LD DE:HL,(HL)
+	PUSH	AF
+	LD	E,(HL)
+	INC	HL
+	LD	D,(HL)
+	INC	HL
+	LD	A,(HL)
+	INC	HL
+	LD	H,(HL)
+	LD	L,A
+	POP	AF
+	EX	DE,HL
+	RET
+;
+ST32:
+	; LD (BC),DE:HL
+	PUSH	AF
+	LD	A,L
+	LD	(BC),A
+	INC	BC
+	LD	A,H
+	LD	(BC),A
+	INC	BC
+	LD	A,E
+	LD	(BC),A
+	INC	BC
+	LD	A,D
+	LD	(BC),A
+	POP	AF
+	RET
+;
+; INC/ADD/DEC/SUB 32 BIT VALUE IN DE:HL
+; FOR ADD/SUB, OPERAND IS IN BC
+;
+INC32:
+	LD	BC,1
+ADD32:
+	ADD	HL,BC
+	RET	NC
+	INC	DE
+	RET
+;
+DEC32:
+	LD	BC,1
+SUB32:
+	OR	A
+	SBC	HL,BC
+	RET	NC
+	DEC	DE
+	RET
+;
+; INC32 (HL)
+; INCREMENT 32 BIT BINARY AT ADDRESS
+;
+INC32HL:
+	INC	(HL)
+	RET	NZ
+	INC	HL
+	INC	(HL)
+	RET	NZ
+	INC	HL
+	INC	(HL)
+	RET	NZ
+	INC	HL
+	INC	(HL)
+	RET
+
--- a/Source/Apps/TEST/DMAmon/ver.inc
+++ b/Source/Apps/TEST/DMAmon/ver.inc
@ -0,0 +1,5 @@
+#DEFINE	RMJ	3
+#DEFINE	RMN	1
+#DEFINE	RUP	1
+#DEFINE	RTP	03
+#DEFINE BIOSVER	"3.1.1-pre.111"
--- a/Source/Apps/TEST/MBC/button2.asm
+++ b/Source/Apps/TEST/MBC/button2.asm
--- a/Source/Apps/TEST/MBC/leds2.asm
+++ b/Source/Apps/TEST/MBC/leds2.asm
--- a/Source/Apps/TEST/MBC/tone3.asm
+++ b/Source/Apps/TEST/MBC/tone3.asm
--- a/Source/Apps/TEST/dskyng/Build.cmd
+++ b/Source/Apps/TEST/dskyng/Build.cmd
@ -0,0 +1,11 @@
+@echo off
+setlocal
+
+set TOOLS=../../../../Tools
+set PATH=%TOOLS%\tasm32;%PATH%
+set TASMTABS=%TOOLS%\tasm32
+
+tasm -t180 -g3 -fFF tstdskng.asm tstdskng.com tstdskng.lst || exit /b
+
+copy /Y tstdskng.com ..\..\..\..\Binary\Apps\ || exit /b
+
--- a/Source/Apps/TEST/dskyng/Clean.cmd
+++ b/Source/Apps/TEST/dskyng/Clean.cmd
@ -0,0 +1,6 @@
+@echo off
+setlocal
+
+if exist *.com del *.com
+if exist *.lst del *.lst
+if exist *.bin del *.bin
--- a/Source/Apps/TEST/dskyng/tstdskng.asm
+++ b/Source/Apps/TEST/dskyng/tstdskng.asm
--- a/Source/Apps/TEST/inttst/Build.cmd
+++ b/Source/Apps/TEST/inttst/Build.cmd
@ -0,0 +1,11 @@
+@echo off
+setlocal
+
+set TOOLS=../../../../Tools
+set PATH=%TOOLS%\tasm32;%PATH%
+set TASMTABS=%TOOLS%\tasm32
+
+tasm -t180 -g3 -fFF inttest.asm inttest.com inttest.lst || exit /b
+
+copy /Y inttest.com ..\..\..\..\Binary\Apps\ || exit /b
+
--- a/Source/Apps/TEST/inttst/Clean.cmd
+++ b/Source/Apps/TEST/inttst/Clean.cmd
@ -0,0 +1,6 @@
+@echo off
+setlocal
+
+if exist *.com del *.com
+if exist *.lst del *.lst
+if exist *.bin del *.bin
--- a/Source/Apps/TEST/inttst/inttest.asm
+++ b/Source/Apps/TEST/inttst/inttest.asm
--- a/Source/Apps/TEST/ppidetst/Build.cmd
+++ b/Source/Apps/TEST/ppidetst/Build.cmd
@ -0,0 +1,11 @@
+@echo off
+setlocal
+
+set TOOLS=../../../../Tools
+set PATH=%TOOLS%\tasm32;%PATH%
+set TASMTABS=%TOOLS%\tasm32
+
+tasm -t180 -g3 -fFF ppidetst.asm ppidetst.com ppidetst.lst || exit /b
+
+copy /Y ppidetst.com ..\..\..\..\Binary\Apps\ || exit /b
+
--- a/Source/Apps/TEST/ppidetst/Clean.cmd
+++ b/Source/Apps/TEST/ppidetst/Clean.cmd
@ -0,0 +1,6 @@
+@echo off
+setlocal
+
+if exist *.com del *.com
+if exist *.lst del *.lst
+if exist *.bin del *.bin
--- a/Source/Apps/TEST/ppidetst/ppidetst.asm
+++ b/Source/Apps/TEST/ppidetst/ppidetst.asm
--- a/Source/Apps/TEST/ramtest/Build.cmd
+++ b/Source/Apps/TEST/ramtest/Build.cmd
@ -1,7 +1,7 @@
@echo off
 setlocal

-set TOOLS=../../../Tools
+set TOOLS=../../../../Tools
 set PATH=%TOOLS%\tasm32;%PATH%
 set TASMTABS=%TOOLS%\tasm32

@ -10,4 +10,4 @@ tasm -t80 -b -fFF dbgmon.asm dbgmon.bin dbgmon.lst || exit /b

 copy /Y /b loader.bin+dbgmon.bin ramtest.com || exit /b

-copy /Y ramtest.com ..\..\..\Binary\Apps\ || exit /b
+copy /Y ramtest.com ..\..\..\..\Binary\Apps\ || exit /b
--- a/Source/Apps/TEST/ramtest/Clean.cmd
+++ b/Source/Apps/TEST/ramtest/Clean.cmd
--- a/Source/Apps/TEST/ramtest/Makefile
+++ b/Source/Apps/TEST/ramtest/Makefile
--- a/Source/Apps/TEST/ramtest/dbgmon.asm
+++ b/Source/Apps/TEST/ramtest/dbgmon.asm
--- a/Source/Apps/TEST/ramtest/loader.asm
+++ b/Source/Apps/TEST/ramtest/loader.asm
--- a/Source/Apps/TEST/ramtest/ramtest.bat
+++ b/Source/Apps/TEST/ramtest/ramtest.bat
--- a/Source/Apps/TEST/ramtest/ramtest.sh
+++ b/Source/Apps/TEST/ramtest/ramtest.sh
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@ -1313,7 +1313,7 @@ Z280_INITZ:
 ; MBC RUNTIME MEMORY SIZE ADJUSTMENT
 ;
 ; THE MBC RAM BOARD CAN CONTAIN 1 OR 2 RAM CHIPS.  THEY CAN BE
-; EITHER 128K OR 512K EACH.  SO THE MBC RAM BAORD CAN HAVE A
+; EITHER 128K OR 512K EACH.  SO THE MBC RAM BOARD CAN HAVE A
 ; TOTAL OF 128K, 256K, 512K, OR 1024K.  THE COMMON (HIMEM) RAM
 ; IS ALWAYS MAPPED TO THE LAST 32K OF THE FIRST CHIP ON THE BOARD.
 ; IF THERE ARE TWO CHIPS ON THE BOARD, THIS MEANS THE COMMON
--- a/Source/HBIOS/md.asm
+++ b/Source/HBIOS/md.asm
@ -376,7 +376,7 @@ MD_SECM:
 	ADD	HL,DE			; WANT TO COPY
 	LD	DE,(MD_DSKBUF)
 ;
-#IF (DMAENABLE & (DMAMODE=DMAMODE_ECB))
+#IF (DMAENABLE & (DMAMODE!DMAMODE_NONE))
 #IF (DMA_FBACK)
 	LD	A,(DMA_FAIL_FLAG)
 	OR	A
@ -386,7 +386,7 @@ MD_SECM:
 	JP	DMALDIR			; 4K SECTOR TO THE DISK BUFFER
 #ENDIF
 MD_NODMA:
-#IF (!(DMAENABLE & (DMAMODE=DMAMODE_ECB)))	
+#IF (!(DMAENABLE & (DMAMODE!DMAMODE_NONE)))	
 	LD	BC,512			; COPY ONE 512B SECTOR FROM THE
 	LDIR				; 4K SECTOR TO THE DISK BUFFER
 	XOR	A
@ -510,7 +510,7 @@ MD_SECM1:				; DESIRED SECTOR IS IN BUFFER
 	EX	DE,HL
 ;
 	LD	HL,(MD_DSKBUF)
-#IF (DMAENABLE & (DMAMODE=DMAMODE_ECB))
+#IF (DMAENABLE & (DMAMODE!DMAMODE_NONE))
 #IF (DMA_FBACK)
 	LD	A,(DMA_FAIL_FLAG)
 	OR	A
@ -522,7 +522,7 @@ MD_SECM1:				; DESIRED SECTOR IS IN BUFFER
 	JR	MD_NODMAERR
 #ENDIF
 MD_NODMA1:
-#IF (!(DMAENABLE & (DMAMODE=DMAMODE_ECB)))
+#IF (!(DMAENABLE & (DMAMODE!DMAMODE_NONE)))
 	LD	BC,512			; COPY ONE 512B SECTOR FROM THE
 	LDIR
 #ELSE