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@ -41,6 +41,9 @@ |
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; 2018-01-08: V5.2 ADDED RC2014 SUPPORT FOR: |
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; 2018-01-08: V5.2 ADDED RC2014 SUPPORT FOR: |
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; - SCOTT BAKER (SMB) SMC 9266 FDC |
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; - SCOTT BAKER (SMB) SMC 9266 FDC |
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; - SCOTT BAKER (SMB) WDC 37C65 FDC |
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; - SCOTT BAKER (SMB) WDC 37C65 FDC |
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; 2018-09-05: v5.3 ADDED SUPPORT FOR SMALLZ80 |
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; - USE EOT=R TO END R/W AFTER ONE SECTOR INSTEAD |
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; OF USING PULSE TC |
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; |
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; |
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;_______________________________________________________________________________ |
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;_______________________________________________________________________________ |
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; |
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; |
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@ -60,6 +63,11 @@ |
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;_______________________________________________________________________________ |
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;_______________________________________________________________________________ |
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; |
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; |
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; |
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; |
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FALSE .EQU 0 |
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TRUE .EQU ~FALSE |
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; |
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; FDC ID |
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; |
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FDC_DIO .EQU 0 |
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FDC_DIO .EQU 0 |
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FDC_DIO3 .EQU 1 |
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FDC_DIO3 .EQU 1 |
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FDC_ZETA .EQU 2 |
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FDC_ZETA .EQU 2 |
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@ -68,18 +76,15 @@ FDC_DIDE .EQU 4 |
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FDC_N8 .EQU 5 |
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FDC_N8 .EQU 5 |
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FDC_RCSMC .EQU 6 |
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FDC_RCSMC .EQU 6 |
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FDC_RCWDC .EQU 7 |
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FDC_RCWDC .EQU 7 |
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FDC_SMZ80 .EQU 8 |
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; |
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; |
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_DIO .EQU 1 << FDC_DIO |
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_DIO3 .EQU 1 << FDC_DIO3 |
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_ZETA .EQU 1 << FDC_ZETA |
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_ZETA2 .EQU 1 << FDC_ZETA2 |
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_DIDE .EQU 1 << FDC_DIDE |
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_N8 .EQU 1 << FDC_N8 |
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_RCSMC .EQU 1 << FDC_RCSMC |
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_RCWDC .EQU 1 << FDC_RCWDC |
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; FDC MODE |
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; |
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; |
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FALSE .EQU 0 |
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TRUE .EQU ~FALSE |
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_DIO .EQU $01 ; CUSTOM FOR DIO BOARD |
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_DIO3 .EQU $02 ; CUSTOM FOR DIO3 BOARD |
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_ZETA .EQU $04 ; CUSTOM FOR ZETA |
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_RCSMC .EQU $08 ; CUSTOM FOR RC2014 SMB SMC MODULE |
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_PCAT .EQU $10 ; PC/AT MODE IN NEWER CONTROLLERS |
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; |
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; |
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;=============================================================================== |
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;=============================================================================== |
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; MAIN PROGRAM PROCEDURE |
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; MAIN PROGRAM PROCEDURE |
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@ -177,11 +182,13 @@ INIT1: |
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JR INIT3 ; AND DONE |
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JR INIT3 ; AND DONE |
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INIT2: |
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INIT2: |
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; NO KNOWN BIOS DETECTED, BAIL OUT W/ ERROR |
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LD DE,STR_BIOERR |
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CALL WRITESTR |
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OR 0FFH |
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RET |
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;; NO KNOWN BIOS DETECTED, BAIL OUT W/ ERROR |
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;LD DE,STR_BIOERR |
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;CALL WRITESTR |
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;OR 0FFH |
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;RET |
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LD A,20 |
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LD (CPUSPD),A |
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INIT3: |
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INIT3: |
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; COMPUTE CPU SCALER FOR DELAY LOOPS |
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; COMPUTE CPU SCALER FOR DELAY LOOPS |
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@ -204,8 +211,8 @@ INIT5: |
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XOR A |
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XOR A |
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RET |
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RET |
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STR_BANNER .DB "Floppy Disk Utility (FDU) v5.2, 08-Jan-2018$" |
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STR_BANNER2 .DB "Copyright (C) 2017, Wayne Warthen, GNU GPL v3","$" |
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STR_BANNER .DB "Floppy Disk Utility (FDU) v5.3, 28-Sep-2018$" |
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STR_BANNER2 .DB "Copyright (C) 2018, Wayne Warthen, GNU GPL v3","$" |
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STR_HBIOS .DB " [HBIOS]$" |
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STR_HBIOS .DB " [HBIOS]$" |
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STR_UBIOS .DB " [UBIOS]$" |
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STR_UBIOS .DB " [UBIOS]$" |
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; |
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; |
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@ -238,20 +245,7 @@ FDCSEL1: |
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FDCSEL2: |
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FDCSEL2: |
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; SAVE SELECTED FDC IDENTIFIER |
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; SAVE SELECTED FDC IDENTIFIER |
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DEC A ; CONVERT TO ZERO-BASED FDC ID |
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DEC A ; CONVERT TO ZERO-BASED FDC ID |
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LD (FDCID),A ; RECORD THE FDC ID |
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PUSH AF ; SAVE IT |
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; |
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; CREATE AND SAVE A BIT MAPPED VALUE |
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INC A ; PREPARE LOOP COUNT |
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LD B,A ; AND PUT IN B |
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XOR A ; START WITH ALL BITS OFF |
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SCF ; ... AND CF SET |
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FDCSEL3: |
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RLA ; ROTATE BIT TO NEXT POSITION |
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DJNZ FDCSEL3 ; AND CONTINUE TILL DONE |
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LD (FDCBM),A ; SAVE BITMAP VALUE |
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; |
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POP AF ; RESTORE FDC ID |
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LD (FDCID),A ; RECORD THE FDC ID |
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RLCA ; TIMES 4 |
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RLCA ; TIMES 4 |
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RLCA ; ... FOR 4 BYTE ENTRIES |
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RLCA ; ... FOR 4 BYTE ENTRIES |
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LD HL,FDCTBL ; POINT TO FDC INSTANCE TABLE |
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LD HL,FDCTBL ; POINT TO FDC INSTANCE TABLE |
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@ -266,6 +260,8 @@ FDCSEL3: |
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LD D,(HL) ; ... |
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LD D,(HL) ; ... |
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LD (FDCCFG),DE ; SAVE CFG PTR |
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LD (FDCCFG),DE ; SAVE CFG PTR |
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LD IY,(FDCCFG) ; AND INIT A WORKING COPY |
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LD IY,(FDCCFG) ; AND INIT A WORKING COPY |
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LD A,(IY+CFG_MODE) ; GET MODE BITMAP BYTE |
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LD (FDCBM),A ; SAVE IT TO ACTIVE WORKING COPY |
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; |
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; |
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LD DE,(FDCLBL) ; GET LABEL POINTER |
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LD DE,(FDCLBL) ; GET LABEL POINTER |
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CALL WRITESTR ; AND DISPLAY IT |
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CALL WRITESTR ; AND DISPLAY IT |
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@ -285,6 +281,7 @@ FDCTBL: ; LABEL CONFIG DATA |
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.DW STR_N8, CFG_N8 |
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.DW STR_N8, CFG_N8 |
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.DW STR_RCSMC, CFG_RCSMC |
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.DW STR_RCSMC, CFG_RCSMC |
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.DW STR_RCWDC, CFG_RCWDC |
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.DW STR_RCWDC, CFG_RCWDC |
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.DW STR_SMZ80, CFG_SMZ80 |
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FDCCNT .EQU ($-FDCTBL)/4 ; FD CONTROLLER COUNT |
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FDCCNT .EQU ($-FDCTBL)/4 ; FD CONTROLLER COUNT |
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; |
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; |
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; FDC LABEL STRINGS |
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; FDC LABEL STRINGS |
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@ -297,6 +294,7 @@ STR_DIDE .TEXT "D-IDE$" |
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STR_N8 .TEXT "N8$" |
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STR_N8 .TEXT "N8$" |
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STR_RCSMC .TEXT "RC-SMC$" |
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STR_RCSMC .TEXT "RC-SMC$" |
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STR_RCWDC .TEXT "RC-WDC$" |
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STR_RCWDC .TEXT "RC-WDC$" |
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STR_SMZ80 .TEXT "SMZ80$" |
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; |
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; |
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; FDC CONFIGURATION BLOCKS |
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; FDC CONFIGURATION BLOCKS |
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; |
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; |
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@ -308,9 +306,28 @@ CFG_DCR .EQU 4 |
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CFG_DACK .EQU 5 |
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CFG_DACK .EQU 5 |
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CFG_TC .EQU 6 |
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CFG_TC .EQU 6 |
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CFG_DMA .EQU 7 |
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CFG_DMA .EQU 7 |
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CFG_MODE .EQU 8 |
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; |
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; |
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CFG_DIO: |
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CFG_DIO: |
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.DB 036H ; FDC MAIN STATUS REGISTER |
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.DB 037H ; FDC DATA PORT |
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.DB 038H ; DATA INPUT REGISTER |
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.DB 03AH ; DIGITAL OUTPUT REGISTER (LATCH) |
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.DB 0FFH ; DCR |
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.DB 0FFH ; DACK |
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.DB 0FFH ; TERMINAL COUNT (W/ DACK) |
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.DB 03CH ; PSEUDO DMA DATA PORT |
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.DB _DIO ; MODE= |
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CFG_DIO3: |
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CFG_DIO3: |
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.DB 036H ; FDC MAIN STATUS REGISTER |
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.DB 037H ; FDC DATA PORT |
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.DB 038H ; DATA INPUT REGISTER |
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.DB 03AH ; DIGITAL OUTPUT REGISTER (LATCH) |
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.DB 0FFH ; DCR |
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.DB 0FFH ; DACK |
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.DB 0FFH ; TERMINAL COUNT (W/ DACK) |
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.DB 03CH ; PSEUDO DMA DATA PORT |
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.DB _DIO3 ; MODE= |
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CFG_ZETA: |
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CFG_ZETA: |
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.DB 036H ; FDC MAIN STATUS REGISTER |
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.DB 036H ; FDC MAIN STATUS REGISTER |
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.DB 037H ; FDC DATA PORT |
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.DB 037H ; FDC DATA PORT |
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@ -320,6 +337,7 @@ CFG_ZETA: |
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.DB 0FFH ; DACK |
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.DB 0FFH ; DACK |
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.DB 0FFH ; TERMINAL COUNT (W/ DACK) |
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.DB 0FFH ; TERMINAL COUNT (W/ DACK) |
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.DB 03CH ; PSEUDO DMA DATA PORT |
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.DB 03CH ; PSEUDO DMA DATA PORT |
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.DB _ZETA ; MODE= |
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; |
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; |
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CFG_ZETA2: |
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CFG_ZETA2: |
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.DB 030H ; FDC MAIN STATUS REGISTER |
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.DB 030H ; FDC MAIN STATUS REGISTER |
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@ -330,6 +348,7 @@ CFG_ZETA2: |
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.DB 0FFH ; DACK |
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.DB 0FFH ; DACK |
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.DB 038H ; TERMINAL COUNT (W/ DACK) |
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.DB 038H ; TERMINAL COUNT (W/ DACK) |
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.DB 0FFH ; NOT USED BY ZETA SBC V2 |
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.DB 0FFH ; NOT USED BY ZETA SBC V2 |
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.DB _PCAT ; MODE= |
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; |
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; |
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CFG_DIDE: |
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CFG_DIDE: |
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.DB 02AH ; FDC MAIN STATUS REGISTER |
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.DB 02AH ; FDC MAIN STATUS REGISTER |
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@ -340,6 +359,7 @@ CFG_DIDE: |
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.DB 03CH ; DACK |
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.DB 03CH ; DACK |
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.DB 03DH ; TERMINAL COUNT (W/ DACK) |
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.DB 03DH ; TERMINAL COUNT (W/ DACK) |
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.DB 0FFH ; NOT USED BY DIDE |
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.DB 0FFH ; NOT USED BY DIDE |
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.DB _PCAT ; MODE= |
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; |
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; |
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CFG_N8: |
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CFG_N8: |
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.DB 08CH ; FDC MAIN STATUS REGISTER |
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.DB 08CH ; FDC MAIN STATUS REGISTER |
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@ -350,6 +370,7 @@ CFG_N8: |
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.DB 090H ; DACK |
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.DB 090H ; DACK |
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.DB 093H ; TERMINAL COUNT (W/ DACK) |
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.DB 093H ; TERMINAL COUNT (W/ DACK) |
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.DB 0FFH ; NOT USED BY N8 |
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.DB 0FFH ; NOT USED BY N8 |
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.DB _PCAT ; MODE= |
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; |
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; |
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CFG_RCSMC: |
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CFG_RCSMC: |
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.DB 050H ; FDC MAIN STATUS REGISTER |
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.DB 050H ; FDC MAIN STATUS REGISTER |
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@ -360,6 +381,7 @@ CFG_RCSMC: |
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.DB 0FFH ; DACK |
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.DB 0FFH ; DACK |
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.DB 0FFH ; TERMINAL COUNT (W/ DACK) |
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.DB 0FFH ; TERMINAL COUNT (W/ DACK) |
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.DB 0FFH ; PSEUDO DMA DATA PORT |
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.DB 0FFH ; PSEUDO DMA DATA PORT |
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.DB _RCSMC ; MODE= |
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; |
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; |
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CFG_RCWDC: |
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CFG_RCWDC: |
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.DB 050H ; FDC MAIN STATUS REGISTER |
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.DB 050H ; FDC MAIN STATUS REGISTER |
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@ -370,6 +392,18 @@ CFG_RCWDC: |
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.DB 0FFH ; DACK |
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.DB 0FFH ; DACK |
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.DB 058H ; TERMINAL COUNT (W/ DACK) |
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.DB 058H ; TERMINAL COUNT (W/ DACK) |
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.DB 0FFH ; PSEUDO DMA DATA PORT |
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.DB 0FFH ; PSEUDO DMA DATA PORT |
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.DB _PCAT ; MODE= |
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; |
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CFG_SMZ80: |
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.DB 044H ; FDC MAIN STATUS REGISTER |
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.DB 045H ; FDC DATA PORT |
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.DB 0FFH ; DATA INPUT REGISTER |
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.DB 042H ; DIGITAL OUTPUT REGISTER (LATCH) |
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.DB 047H ; DCR |
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.DB 0FFH ; DACK |
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.DB 0FFH ; TERMINAL COUNT (W/ DACK) |
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.DB 0FFH ; PSEUDO DMA DATA PORT |
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.DB _PCAT ; MODE= |
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; |
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; |
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FDCID .DB 0 ; FDC IDENTIFIER (0 INDEXED) |
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FDCID .DB 0 ; FDC IDENTIFIER (0 INDEXED) |
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FDCBM .DB 0 ; FDC ID BITMAP |
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FDCBM .DB 0 ; FDC ID BITMAP |
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@ -388,6 +422,7 @@ FSS_MENU: |
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.TEXT " (6) N8 Onboard FDC\r\n" |
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.TEXT " (6) N8 Onboard FDC\r\n" |
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.TEXT " (7) RC2014 SMC (SMB)\r\n" |
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.TEXT " (7) RC2014 SMC (SMB)\r\n" |
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.TEXT " (8) RC2014 WDC (SMB)\r\n" |
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.TEXT " (8) RC2014 WDC (SMB)\r\n" |
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.TEXT " (9) SmallZ80 Expansion\r\n" |
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.TEXT "=== OPTION ===> $\r\n" |
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.TEXT "=== OPTION ===> $\r\n" |
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; |
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; |
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;=============================================================================== |
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;=============================================================================== |
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@ -1464,7 +1499,8 @@ MD_MAP: |
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.DB %00000001 ; DIDE POLL |
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.DB %00000001 ; DIDE POLL |
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.DB %00000001 ; N8 POLL |
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.DB %00000001 ; N8 POLL |
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.DB %00000001 ; RCSMC POLL |
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.DB %00000001 ; RCSMC POLL |
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.DB %00000001 ; RCWDC POLL |
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; .DB %00000001 ; RCWDC POLL |
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.DB %00000001 ; SMZ80 POLL |
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; |
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; |
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; MEDIA DESCRIPTION BLOCK |
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; MEDIA DESCRIPTION BLOCK |
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; |
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; |
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@ -1810,7 +1846,7 @@ FM_DRAW: |
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AND _ZETA | _DIO3 |
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AND _ZETA | _DIO3 |
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JR NZ,FM_DRAW0B |
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JR NZ,FM_DRAW0B |
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LD A,(HL) |
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LD A,(HL) |
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AND _DIDE | _N8 | _ZETA2 | _RCWDC |
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AND _PCAT |
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JR NZ,FM_DRAW0C |
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JR NZ,FM_DRAW0C |
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LD A,(HL) |
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LD A,(HL) |
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AND _RCSMC |
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AND _RCSMC |
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@ -1825,7 +1861,7 @@ FM_DRAW0B: ; ZETA, DIO3 |
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LD A,(FST_DOR) |
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LD A,(FST_DOR) |
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AND 00000010B |
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AND 00000010B |
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JR FM_DRAW1 |
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JR FM_DRAW1 |
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FM_DRAW0C: ; DIDE, N8, ZETA2, RCWDC |
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FM_DRAW0C: ; DIDE, N8, ZETA2, RCWDC, SMZ80 |
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LD A,(FST_DOR) |
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LD A,(FST_DOR) |
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AND 11110000B |
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AND 11110000B |
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JR FM_DRAW1 |
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JR FM_DRAW1 |
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@ -1963,7 +1999,7 @@ FM_MOTOR: |
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AND _ZETA | _DIO3 |
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AND _ZETA | _DIO3 |
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JR NZ,FM_MOTOR0B |
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JR NZ,FM_MOTOR0B |
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LD A,(HL) |
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LD A,(HL) |
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AND _DIDE | _N8 | _ZETA2 | _RCWDC |
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AND _PCAT |
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JR NZ,FM_MOTOR0C |
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JR NZ,FM_MOTOR0C |
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LD A,(HL) |
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LD A,(HL) |
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AND _RCSMC |
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AND _RCSMC |
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@ -1978,7 +2014,7 @@ FM_MOTOR0B: ; ZETA, DIO3 |
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LD A,(FST_DOR) |
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LD A,(FST_DOR) |
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AND 00000010B |
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AND 00000010B |
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JR FM_MOTOR1 |
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JR FM_MOTOR1 |
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FM_MOTOR0C: ; DIDE, N8, ZETA2, RCWDC |
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FM_MOTOR0C: ; DIDE, N8, ZETA2, RCWDC, SMZ80 |
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LD A,(FST_DOR) |
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LD A,(FST_DOR) |
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AND 11110000B |
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AND 11110000B |
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JR FM_MOTOR1 |
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JR FM_MOTOR1 |
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@ -2515,7 +2551,9 @@ FC_SETUPIO: |
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LD (DE),A |
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LD (DE),A |
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INC DE |
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INC DE |
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LD A,(FCD_EOT) |
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; V5.3, USE EOT=R TO R/W ONLY ONE SECTOR |
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;LD A,(FCD_EOT) |
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LD A,(FCD_R) |
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LD (DE),A |
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LD (DE),A |
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INC DE |
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INC DE |
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@ -2703,7 +2741,7 @@ FC_INIT: |
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AND _ZETA | _DIO3 |
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AND _ZETA | _DIO3 |
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JR NZ,FC_INIT2 |
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JR NZ,FC_INIT2 |
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LD A,(HL) |
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LD A,(HL) |
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AND _DIDE | _N8 | _ZETA2 | _RCWDC |
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AND _PCAT |
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JR NZ,FC_INIT3 |
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JR NZ,FC_INIT3 |
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LD A,(HL) |
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LD A,(HL) |
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AND _RCSMC |
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AND _RCSMC |
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@ -2715,7 +2753,7 @@ FC_INIT1: ; DIO |
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FC_INIT2: ; ZETA, DIO3 |
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FC_INIT2: ; ZETA, DIO3 |
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LD A,(FCD_DORB) |
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LD A,(FCD_DORB) |
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JR FC_INIT5 |
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JR FC_INIT5 |
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FC_INIT3: ; DIDE, N8, ZETA2, RCWDC |
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FC_INIT3: ; DIDE, N8, ZETA2, RCWDC, SMZ80 |
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LD A,(FCD_DORC) |
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LD A,(FCD_DORC) |
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JR FC_INIT5 |
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JR FC_INIT5 |
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FC_INIT4: ; WDSMC |
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FC_INIT4: ; WDSMC |
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@ -2747,7 +2785,7 @@ FC_RESETFDC: |
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AND _ZETA | _DIO3 | _RCSMC |
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AND _ZETA | _DIO3 | _RCSMC |
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JR NZ,FC_RESETFDC1 |
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JR NZ,FC_RESETFDC1 |
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LD A,(HL) |
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LD A,(HL) |
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AND _DIDE | _N8 | _ZETA2 | _RCWDC |
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AND _PCAT |
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JR NZ,FC_RESETFDC2 |
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JR NZ,FC_RESETFDC2 |
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RET |
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RET |
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FC_RESETFDC1: ; ZETA, DIO3, RCSMC |
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FC_RESETFDC1: ; ZETA, DIO3, RCSMC |
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@ -2759,7 +2797,7 @@ FC_RESETFDC1: ; ZETA, DIO3, RCSMC |
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POP AF |
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POP AF |
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OUT (C),A |
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OUT (C),A |
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JR FC_RESETFDC3 |
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JR FC_RESETFDC3 |
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FC_RESETFDC2: ; DIDE, N8, ZETA2, RCWDC |
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FC_RESETFDC2: ; DIDE, N8, ZETA2, RCWDC, SMZ80 |
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LD A,0 |
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LD A,0 |
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OUT (C),A |
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OUT (C),A |
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LD A,(FST_DOR) |
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LD A,(FST_DOR) |
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@ -2774,22 +2812,23 @@ FC_RESETFDC3: |
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; PULSE TERMCT TO TERMINATE ANY ACTIVE EXECUTION PHASE |
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; PULSE TERMCT TO TERMINATE ANY ACTIVE EXECUTION PHASE |
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; |
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; |
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FC_PULSETC: |
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FC_PULSETC: |
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LD A,(FDCBM) |
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AND _DIDE | _N8 | _ZETA2 | _RCWDC |
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JR NZ,FC_PULSETC1 |
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; NOT DIDE, N8, ZETA2 |
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LD C,(IY+CFG_DOR) |
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LD A,(FST_DOR) |
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SET 0,A |
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OUT (C),A |
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RES 0,A |
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OUT (C),A |
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JR FC_PULSETC2 |
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FC_PULSETC1: ; DIDE, N8, ZETA2, RCWDC |
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LD C,(IY+CFG_TC) |
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IN A,(C) |
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JR FC_PULSETC2 |
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FC_PULSETC2: |
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; V5.3, USE EOT=R TO R/W ONLY ONE SECTOR |
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;LD A,(FDCBM) |
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;AND _PCAT |
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;JR NZ,FC_PULSETC1 |
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;; NOT DIDE, N8, ZETA2, RCSMC, SMZ80 |
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;LD C,(IY+CFG_DOR) |
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;LD A,(FST_DOR) |
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;SET 0,A |
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;OUT (C),A |
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;RES 0,A |
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;OUT (C),A |
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;JR FC_PULSETC2 |
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;FC_PULSETC1: ; DIDE, N8, ZETA2, RCWDC, SMZ80 |
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;LD C,(IY+CFG_TC) |
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;IN A,(C) |
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;JR FC_PULSETC2 |
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;FC_PULSETC2: |
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RET |
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RET |
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; |
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; |
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; SET FST_DOR FOR MOTOR CONTROL ON |
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; SET FST_DOR FOR MOTOR CONTROL ON |
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@ -2803,7 +2842,7 @@ FC_MOTORON: |
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AND _ZETA | _DIO3 |
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AND _ZETA | _DIO3 |
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JR NZ,FC_MOTORON2 |
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JR NZ,FC_MOTORON2 |
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LD A,(HL) |
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LD A,(HL) |
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AND _DIDE | _N8 | _ZETA2 | _RCWDC |
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AND _PCAT |
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JR NZ,FC_MOTORON3 |
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JR NZ,FC_MOTORON3 |
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LD A,(HL) |
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LD A,(HL) |
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AND _RCSMC |
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AND _RCSMC |
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@ -2817,7 +2856,7 @@ FC_MOTORON2: ; ZETA, DIO3 |
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LD HL,FST_DOR ; POINT TO FDC_DOR |
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|
LD HL,FST_DOR ; POINT TO FDC_DOR |
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|
SET 1,(HL) |
|
|
SET 1,(HL) |
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|
JR FC_MOTORON5 |
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|
JR FC_MOTORON5 |
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FC_MOTORON3: ; DIDE, N8, ZETA2, RCWDC |
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FC_MOTORON3: ; DIDE, N8, ZETA2, RCWDC, SMZ80 |
|
|
LD HL,FST_DOR ; POINT TO FDC_DOR |
|
|
LD HL,FST_DOR ; POINT TO FDC_DOR |
|
|
LD A,(HL) ; START WITH CURRENT DOR |
|
|
LD A,(HL) ; START WITH CURRENT DOR |
|
|
AND 11111100B ; GET RID OF ANY ACTIVE DS BITS |
|
|
AND 11111100B ; GET RID OF ANY ACTIVE DS BITS |
|
|
@ -2849,7 +2888,7 @@ FC_MOTORON5: |
|
|
CALL FC_SETDOR ; OUTPUT TO CONTROLLER |
|
|
CALL FC_SETDOR ; OUTPUT TO CONTROLLER |
|
|
CALL LDELAY ; WAIT 1/2 SEC ON MOTOR START FOR SPIN-UP |
|
|
CALL LDELAY ; WAIT 1/2 SEC ON MOTOR START FOR SPIN-UP |
|
|
LD A,(FDCBM) |
|
|
LD A,(FDCBM) |
|
|
AND _DIDE | _N8 | _ZETA2 | _RCWDC |
|
|
|
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|
|
AND _PCAT |
|
|
RET Z |
|
|
RET Z |
|
|
LD A,(FCD_DCR) |
|
|
LD A,(FCD_DCR) |
|
|
LD C,(IY+CFG_DCR) |
|
|
LD C,(IY+CFG_DCR) |
|
|
@ -2867,7 +2906,7 @@ FC_MOTOROFF: |
|
|
AND _ZETA | _DIO3 |
|
|
AND _ZETA | _DIO3 |
|
|
JR NZ,FC_MOTOROFF2 |
|
|
JR NZ,FC_MOTOROFF2 |
|
|
LD A,(HL) |
|
|
LD A,(HL) |
|
|
AND _DIDE | _N8 | _ZETA2 | _RCWDC |
|
|
|
|
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|
|
AND _PCAT |
|
|
JR NZ,FC_MOTOROFF3 |
|
|
JR NZ,FC_MOTOROFF3 |
|
|
LD A,(HL) |
|
|
LD A,(HL) |
|
|
AND _RCSMC |
|
|
AND _RCSMC |
|
|
@ -2881,7 +2920,7 @@ FC_MOTOROFF2: ; ZETA, DIO3 |
|
|
LD HL,FST_DOR ; POINT TO FDC_DOR |
|
|
LD HL,FST_DOR ; POINT TO FDC_DOR |
|
|
RES 1,(HL) |
|
|
RES 1,(HL) |
|
|
JR FC_MOTOROFF5 |
|
|
JR FC_MOTOROFF5 |
|
|
FC_MOTOROFF3: ; DIDE, N8, ZETA2, RCWDC |
|
|
|
|
|
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|
|
FC_MOTOROFF3: ; DIDE, N8, ZETA2, RCWDC, SMZ80 |
|
|
LD HL,FST_DOR ; POINT TO FDC_DOR |
|
|
LD HL,FST_DOR ; POINT TO FDC_DOR |
|
|
LD A,DORC_INIT |
|
|
LD A,DORC_INIT |
|
|
LD (HL),A |
|
|
LD (HL),A |
|
|
@ -3120,8 +3159,10 @@ FOP_EVALST1: |
|
|
JP FOP_EXIT |
|
|
JP FOP_EXIT |
|
|
|
|
|
|
|
|
FOP_ENDCYL: |
|
|
FOP_ENDCYL: |
|
|
LD A,FRC_ENDCYL |
|
|
|
|
|
JP FOP_SETFST |
|
|
|
|
|
|
|
|
; V5.3, USE EOT=R TO R/W ONLY ONE SECTOR |
|
|
|
|
|
;LD A,FRC_ENDCYL |
|
|
|
|
|
;JP FOP_SETFST |
|
|
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|
|
JP FOP_EXIT |
|
|
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|
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|
|
FOP_DATAERR: |
|
|
FOP_DATAERR: |
|
|
LD A,FRC_DATAERR |
|
|
LD A,FRC_DATAERR |
|
|
@ -3745,7 +3786,7 @@ DORB_BR500 .EQU 10100000B ; 500KBPS |
|
|
; |
|
|
; |
|
|
DORB_INIT .EQU DORB_BR250 |
|
|
DORB_INIT .EQU DORB_BR250 |
|
|
; |
|
|
; |
|
|
; *** DIDE/N8/ZETA2/RCWDC *** |
|
|
|
|
|
|
|
|
; *** DIDE/N8/ZETA2/RCWDC/SMZ80 *** |
|
|
; |
|
|
; |
|
|
DORC_INIT .EQU 00001100B ; SOFT RESET INACTIVE, DMA ENABLED |
|
|
DORC_INIT .EQU 00001100B ; SOFT RESET INACTIVE, DMA ENABLED |
|
|
; |
|
|
; |
|
|
|