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ez80: updated ch.asm driver to support ez80

SD Card not supported yet
pull/424/head
Dean Netherton 2 years ago
parent
commit
bc68674ce2
  1. 14
      Source/HBIOS/cfg_rcez80.asm
  2. 4
      Source/HBIOS/ch.asm
  3. 2
      Source/HBIOS/chsd.asm

14
Source/HBIOS/cfg_rcez80.asm

@ -262,16 +262,16 @@ SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
SDMTSWAP .EQU FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011 SDMTSWAP .EQU FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
; ;
CHENABLE .EQU FALSE ; CH: ENABLE CH375/376 USB SUPPORT
CHTRACE .EQU 1 ; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
CHUSBTRACE .EQU 1 ; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
CHSDTRACE .EQU 1 ; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
CHCNT .EQU 2 ; CH: NUMBER OF BOARDS TO DETECT (1-2)
CH0BASE .EQU $3E ; CH 0: BASE I/O ADDRESS
CHENABLE .EQU TRUE ; CH: ENABLE CH375/376 USB SUPPORT
CHTRACE .EQU 2 ; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
CHUSBTRACE .EQU 2 ; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
CHSDTRACE .EQU 2 ; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
CHCNT .EQU 1 ; CH: NUMBER OF BOARDS TO DETECT (1-2)
CH0BASE .EQU $88 ; CH 0: BASE I/O ADDRESS
CH0USBENABLE .EQU TRUE ; CH 0: ENABLE USB DISK CH0USBENABLE .EQU TRUE ; CH 0: ENABLE USB DISK
CH0SDENABLE .EQU FALSE ; CH 0: ENABLE SD DISK CH0SDENABLE .EQU FALSE ; CH 0: ENABLE SD DISK
CH1BASE .EQU $3C ; CH 1: BASE I/O ADDRESS CH1BASE .EQU $3C ; CH 1: BASE I/O ADDRESS
CH1USBENABLE .EQU TRUE ; CH 1: ENABLE USB DISK
CH1USBENABLE .EQU FALSE ; CH 1: ENABLE USB DISK
CH1SDENABLE .EQU FALSE ; CH 1: ENABLE SD DISK CH1SDENABLE .EQU FALSE ; CH 1: ENABLE SD DISK
; ;
PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)

4
Source/HBIOS/ch.asm

@ -236,6 +236,7 @@ CH_INIT4:
CH_CMD: CH_CMD:
LD C,(IY+CH_IOBASE) ; BASE PORT LD C,(IY+CH_IOBASE) ; BASE PORT
INC C ; BUMP TO CMD PORT INC C ; BUMP TO CMD PORT
EZ80_IO
OUT (C),A ; SEND COMMAND OUT (C),A ; SEND COMMAND
CALL CH_NAP ; *DEBUG* CALL CH_NAP ; *DEBUG*
RET RET
@ -245,6 +246,7 @@ CH_CMD:
CH_STAT: CH_STAT:
LD C,(IY+CH_IOBASE) ; BASE PORT LD C,(IY+CH_IOBASE) ; BASE PORT
INC C ; BUMP TO CMD PORT INC C ; BUMP TO CMD PORT
EZ80_IO
IN A,(C) ; READ STATUS IN A,(C) ; READ STATUS
RET RET
; ;
@ -252,6 +254,7 @@ CH_STAT:
; ;
CH_RD: CH_RD:
LD C,(IY+CH_IOBASE) ; BASE PORT LD C,(IY+CH_IOBASE) ; BASE PORT
EZ80_IO
IN A,(C) ; READ BYTE IN A,(C) ; READ BYTE
RET RET
; ;
@ -259,6 +262,7 @@ CH_RD:
; ;
CH_WR: CH_WR:
LD C,(IY+CH_IOBASE) ; BASE PORT LD C,(IY+CH_IOBASE) ; BASE PORT
EZ80_IO
OUT (C),A ; READ BYTE OUT (C),A ; READ BYTE
RET RET
; ;

2
Source/HBIOS/chsd.asm

@ -196,6 +196,7 @@ CHSD_READ1:
#IF (CHSD_FASTIO) #IF (CHSD_FASTIO)
LD B,A ; BYTE COUNT TO READ LD B,A ; BYTE COUNT TO READ
LD C,(IY+CH_IOBASE) ; BASE PORT LD C,(IY+CH_IOBASE) ; BASE PORT
EZ80_IO ;!! NOT SUPPORT INIR YET
INIR ; DO IT FAST INIR ; DO IT FAST
#ELSE #ELSE
LD B,A ; SAVE IT LD B,A ; SAVE IT
@ -263,6 +264,7 @@ CHSD_WRITE1:
#IF (CHSD_FASTIO) #IF (CHSD_FASTIO)
LD B,A ; BYTE COUNT TO WRITE LD B,A ; BYTE COUNT TO WRITE
LD C,(IY+CH_IOBASE) ; BASE PORT LD C,(IY+CH_IOBASE) ; BASE PORT
EZ80_IO ;!! NOT SUPPORT OTIR YET
OTIR ; DO IT FAST OTIR ; DO IT FAST
#ELSE #ELSE
LD B,A ; SAVE IT LD B,A ; SAVE IT

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