mirror of https://github.com/wwarthen/RomWBW.git
doug
13 years ago
1 changed files with 294 additions and 0 deletions
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; std-n8.inc 1/19/2013 dwg - |
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CIODEV_BAT .EQU $E0 |
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;CIODEV_NUL .EQU $F0 |
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; |
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; DISK DEVICES (ONLY FIRST NIBBLE RELEVANT, SECOND NIBBLE RESERVED FOR UNIT) |
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; |
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;DIODEV_MD .EQU $00 |
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DIODEV_FD .EQU $10 |
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DIODEV_IDE .EQU $20 |
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DIODEV_ATAPI .EQU $30 |
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DIODEV_PPIDE .EQU $40 |
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DIODEV_SD .EQU $50 |
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DIODEV_PRPSD .EQU $60 |
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DIODEV_PPPSD .EQU $70 |
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DIODEV_HDSK .EQU $80 |
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; |
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; RAM DISK INITIALIZATION OPTIONS |
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; |
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;CLR_NEVER .EQU 0 ; NEVER CLEAR RAM DISK |
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;CLR_AUTO .EQU 1 ; CLEAR RAM DISK IF INVALID DIR ENTRIES |
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;;CLR_ALWAYS .EQU 2 ; ALWAYS CLEAR RAM DISK |
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; |
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; DISK MAP SELECTION OPTIONS |
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; |
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;DM_ROM .EQU 1 ; ROM DRIVE PRIORITY |
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;DM_RAM .EQU 2 ; RAM DRIVE PRIORITY |
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;DM_FD .EQU 3 ; FLOPPY DRIVE PRIORITY |
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;DM_IDE .EQU 4 ; IDE DRIVE PRIORITY |
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;DM_PPIDE .EQU 5 ; PPIDE DRIVE PRIORITY |
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:DM_SD .EQU 6 ; SD DRIVE PRIORITY |
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;DM_PRPSD .EQU 7 ; PROPIO SD DRIVE PRIORITY |
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;DM_PPPSD .EQU 8 ; PROPIO SD DRIVE PRIORITY |
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;DM_HDSK .EQU 9 ; SIMH HARD DISK DRIVE PRIORITY |
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; |
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; FLOPPY DISK MEDIA SELECTIONS (ID'S MUST BE INDEX OF ENTRY IN FCD_TBL) |
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; |
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;FDM720 .EQU 0 ; 3.5" FLOPPY, 720KB, 2 SIDES, 80 TRKS, 9 SECTORS |
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;FDM144 .EQU 1 ; 3.5" FLOPPY, 1.44MB, 2 SIDES, 80 TRKS, 18 SECTORS |
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;FDM360 .EQU 2 ; 5.25" FLOPPY, 360KB, 2 SIDES, 40 TRKS, 9 SECTORS |
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;FDM120 .EQU 3 ; 5.25" FLOPPY, 1.2MB, 2 SIDES, 80 TRKS, 15 SECTORS |
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;FDM111 .EQU 4 ; 8" FLOPPY, 1.11MB, 2 SIDES, 74 TRKS, 15 SECTORS |
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; |
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; MEDIA ID VALUES |
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; |
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;MID_NONE .EQU 0 |
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;MID_MDROM .EQU 1 |
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;MID_MDRAM .EQU 2 |
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;MID_HD .EQU 3 |
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;MID_FD720 .EQU 4 |
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;MID_FD144 .EQU 5 |
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;MID_FD360 .EQU 6 |
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;MID_FD120 .EQU 7 |
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;MID_FD111 .EQU 8 |
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; |
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; FD MODE SELECTIONS |
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; |
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;FDMODE_DIO .EQU 1 ; DISKIO V1 |
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;FDMODE_ZETA .EQU 2 ; ZETA |
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;FDMODE_DIDE .EQU 3 ; DUAL IDE |
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;FDMODE_N8 .EQU 4 ; N8 |
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;FDMODE_DIO3 .EQU 5 ; DISKIO V3 |
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; |
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; IDE MODE SELECTIONS |
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; |
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;IDEMODE_DIO .EQU 1 ; DISKIO V1 |
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;IDEMODE_DIDE .EQU 2 ; DUAL IDE |
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; |
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; PPIDE MODE SELECTIONS |
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; |
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;PPIDEMODE_STD .EQU 1 ; STANDARD N8VEM PARALLEL PORT |
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;PPIDEMODE_DIO3 .EQU 2 ; DISKIO V3 PARALLEL PORT |
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; |
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; CONSOLE TERMINAL TYPE CHOICES |
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; |
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;TERM_TTY .EQU 0 |
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;TERM_ANSI .EQU 1 |
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;TERM_WYSE .EQU 2 |
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;TERM_VT52 .EQU 3 |
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; |
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; EMULATION TYPES |
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; |
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;EMUTYP_NONE .EQU 0 |
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;EMUTYP_TTY .EQU 1 |
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;EMUTYP_ANSI .EQU 2 |
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; |
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; SYSTEM GENERATION SETTINGS |
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; |
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;SYS_CPM .EQU 1 ; CPM (IMPLIES BDOS + CCP) |
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;SYS_ZSYS .EQU 2 ; ZSYSTEM OS (IMPLIES ZSDOS + ZCPR) |
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; |
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;DOS_BDOS .EQU 1 ; BDOS |
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;DOS_ZDDOS .EQU 2 ; ZDDOS VARIANT OF ZSDOS |
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;DOS_ZSDOS .EQU 3 ; ZSDOS |
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; |
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;CP_CCP .EQU 1 ; CCP COMMAND PROCESSOR |
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;CP_ZCPR .EQU 2 ; ZCPR COMMAND PROCESSOR |
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; |
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; CONFIGURE DOS (DOS) AND COMMAND PROCESSOR (CP) BASED ON SYSTEM SETTING (SYS) |
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; |
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;#IFNDEF BLD_SYS |
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;SYS .EQU SYS_CPM |
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;#ELSE |
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;SYS .EQU BLD_SYS |
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;#ENDIF |
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; |
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#IF (SYS == SYS_CPM) |
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;DOS .EQU DOS_BDOS |
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;CP .EQU CP_CCP |
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#DEFINE OSLBL "CP/M-80 2.2" |
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#ENDIF |
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; |
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#IF (SYS == SYS_ZSYS) |
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DOS .EQU DOS_ZSDOS |
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CP .EQU CP_ZCPR |
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#DEFINE OSLBL "ZSDOS 1.1" |
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#ENDIF |
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; |
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; INCLUDE VERSION AND BUILD SETTINGS |
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; |
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;#INCLUDE "ver.inc" ; ADD BIOSVER |
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; |
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;#INCLUDE "build.inc" ; INCLUDE USER CONFIG, ADD VARIANT, TIMESTAMP, & ROMSIZE |
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; |
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
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; Support for S100COMPUTERS.COM Hardware ; |
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; Phase One Support - Minimum Board Set ; |
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
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#IF (PLATFORM == PLT_S100) |
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; |
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#IFDEF S100_CPU |
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#INCLUDE "S100CPU.INC" |
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#ENDIF |
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; |
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#IFDEF S100_IOB |
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#INCLUDE "S100IOB.INC" |
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#ENDIF |
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; |
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#IFDEF S100_RRF |
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#INCLUDE "S100RRF.INC" |
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#ENDIF |
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#IFDEF S100_DIDE |
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#INCLUDE "S100DIDE.INC" |
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#ENDIF |
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; |
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#ENDIF |
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#IF (PLATFORM != PLT_N8) |
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; |
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; N8VEM HARDWARE IO PORT ADDRESSES AND MEMORY LOCATIONS |
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; |
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MPCL_RAM .EQU 78H ; BASE IO ADDRESS OF RAM MEMORY PAGER CONFIGURATION LATCH |
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MPCL_ROM .EQU 7CH ; BASE IO ADDRESS OF ROM MEMORY PAGER CONFIGURATION LATCH |
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RTC .EQU 70H ; ADDRESS OF RTC LATCH AND INPUT PORT |
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;__HARDWARE_INTERFACES________________________________________________________________________________________________________________ |
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; |
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; PPI 82C55 I/O IS DECODED TO PORT 60-67 |
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; |
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#IF (PLATFORM == PLT_S2I) |
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PPIBASE .EQU 80H |
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#ELSE |
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PPIBASE .EQU 60H |
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#ENDIF |
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PPIA .EQU PPIBASE + 0 ; PORT A |
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PPIB .EQU PPIBASE + 1 ; PORT B |
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PPIC .EQU PPIBASE + 2 ; PORT C |
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PPIX .EQU PPIBASE + 3 ; PPI CONTROL PORT |
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; |
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; 16C550 SERIAL LINE UART |
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; |
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#IF (PLATFORM == PLT_S2I) |
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SIO_BASE .EQU 90H |
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#ELSE |
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SIO_BASE .EQU 68H |
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#ENDIF |
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SIO_RBR .EQU SIO_BASE + 0 ; DLAB=0: RCVR BUFFER REG (READ ONLY) |
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SIO_THR .EQU SIO_BASE + 0 ; DLAB=0: XMIT HOLDING REG (WRITE ONLY) |
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SIO_IER .EQU SIO_BASE + 1 ; DLAB=0: INT ENABLE REG |
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SIO_IIR .EQU SIO_BASE + 2 ; INT IDENT REGISTER (READ ONLY) |
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SIO_FCR .EQU SIO_BASE + 2 ; FIFO CONTROL REG (WRITE ONLY) |
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SIO_LCR .EQU SIO_BASE + 3 ; LINE CONTROL REG |
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SIO_MCR .EQU SIO_BASE + 4 ; MODEM CONTROL REG |
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SIO_LSR .EQU SIO_BASE + 5 ; LINE STATUS REG |
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SIO_MSR .EQU SIO_BASE + 6 ; MODEM STATUS REG |
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SIO_SCR .EQU SIO_BASE + 7 ; SCRATCH REGISTER |
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SIO_DLL .EQU SIO_BASE + 0 ; DLAB=1: DIVISOR LATCH (LS) |
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SIO_DLM .EQU SIO_BASE + 1 ; DLAB=1: DIVISOR LATCH (MS) |
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; |
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#ENDIF ; (PLATFORM != PLT_N8) |
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; |
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#IF (PLATFORM == PLT_N8) |
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; |
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; Z180 REGISTERS |
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; |
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CPU_IOBASE .EQU 40H ; ONLY RELEVANT FOR Z180 |
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; |
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CPU_CNTLA0: .EQU CPU_IOBASE+$00 ;ASCI0 control A |
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CPU_CNTLA1: .EQU CPU_IOBASE+$01 ;ASCI1 control A |
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CPU_CNTLB0: .EQU CPU_IOBASE+$02 ;ASCI0 control B |
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CPU_CNTLB1: .EQU CPU_IOBASE+$03 ;ASCI1 control B |
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CPU_STAT0: .EQU CPU_IOBASE+$04 ;ASCI0 status |
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CPU_STAT1: .EQU CPU_IOBASE+$05 ;ASCI1 status |
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CPU_TDR0: .EQU CPU_IOBASE+$06 ;ASCI0 transmit |
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CPU_TDR1: .EQU CPU_IOBASE+$07 ;ASCI1 transmit |
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CPU_RDR0: .EQU CPU_IOBASE+$08 ;ASCI0 receive |
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CPU_RDR1: .EQU CPU_IOBASE+$09 ;ASCI1 receive |
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CPU_CNTR: .EQU CPU_IOBASE+$0A ;CSI/O control |
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CPU_TRDR: .EQU CPU_IOBASE+$0B ;CSI/O transmit/receive |
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CPU_TMDR0L: .EQU CPU_IOBASE+$0C ;Timer 0 data lo |
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CPU_TMDR0H: .EQU CPU_IOBASE+$0D ;Timer 0 data hi |
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CPU_RLDR0L: .EQU CPU_IOBASE+$0E ;Timer 0 reload lo |
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CPU_RLDR0H: .EQU CPU_IOBASE+$0F ;Timer 0 reload hi |
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CPU_TCR: .EQU CPU_IOBASE+$10 ;Timer control |
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; |
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CPU_ASEXT0: .EQU CPU_IOBASE+$12 ;ASCI0 extension control (Z8S180) |
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CPU_ASEXT1: .EQU CPU_IOBASE+$13 ;ASCI1 extension control (Z8S180) |
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; |
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CPU_TMDR1L: .EQU CPU_IOBASE+$14 ;Timer 1 data lo |
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CPU_TMDR1H: .EQU CPU_IOBASE+$15 ;Timer 1 data hi |
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CPU_RLDR1L: .EQU CPU_IOBASE+$16 ;Timer 1 reload lo |
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CPU_RLDR1H: .EQU CPU_IOBASE+$17 ;Timer 1 reload hi |
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CPU_FRC: .EQU CPU_IOBASE+$18 ;Free running counter |
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CPU_ASTC0L: .EQU CPU_IOBASE+$1A ;ASCI0 Time constant lo (Z8S180) |
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CPU_ASTC0H: .EQU CPU_IOBASE+$1B ;ASCI0 Time constant hi (Z8S180) |
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CPU_ASTC1L: .EQU CPU_IOBASE+$1C ;ASCI1 Time constant lo (Z8S180) |
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CPU_ASTC1H: .EQU CPU_IOBASE+$1D ;ASCI1 Time constant hi (Z8S180) |
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CPU_CMR: .EQU CPU_IOBASE+$1E ;Clock multiplier (latest Z8S180) |
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CPU_CCR: .EQU CPU_IOBASE+$1F ;CPU control (Z8S180) |
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; |
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CPU_SAR0L: .EQU CPU_IOBASE+$20 ;DMA0 source addr lo |
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CPU_SAR0H: .EQU CPU_IOBASE+$21 ;DMA0 source addr hi |
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CPU_SAR0B: .EQU CPU_IOBASE+$22 ;DMA0 source addr bank |
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CPU_DAR0L: .EQU CPU_IOBASE+$23 ;DMA0 dest addr lo |
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CPU_DAR0H: .EQU CPU_IOBASE+$24 ;DMA0 dest addr hi |
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CPU_DAR0B: .EQU CPU_IOBASE+$25 ;DMA0 dest addr bank |
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CPU_BCR0L: .EQU CPU_IOBASE+$26 ;DMA0 byte count lo |
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CPU_BCR0H: .EQU CPU_IOBASE+$27 ;DMA0 byte count hi |
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CPU_MAR1L: .EQU CPU_IOBASE+$28 ;DMA1 memory addr lo |
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CPU_MAR1H: .EQU CPU_IOBASE+$29 ;DMA1 memory addr hi |
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CPU_MAR1B: .EQU CPU_IOBASE+$2A ;DMA1 memory addr bank |
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CPU_IAR1L: .EQU CPU_IOBASE+$2B ;DMA1 I/O addr lo |
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CPU_IAR1H: .EQU CPU_IOBASE+$2C ;DMA1 I/O addr hi |
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CPU_IAR1B: .EQU CPU_IOBASE+$2D ;DMA1 I/O addr bank (Z8S180) |
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CPU_BCR1L: .EQU CPU_IOBASE+$2E ;DMA1 byte count lo |
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CPU_BCR1H: .EQU CPU_IOBASE+$2F ;DMA1 byte count hi |
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CPU_DSTAT: .EQU CPU_IOBASE+$30 ;DMA status |
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CPU_DMODE: .EQU CPU_IOBASE+$31 ;DMA mode |
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CPU_DCNTL: .EQU CPU_IOBASE+$32 ;DMA/WAIT control |
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CPU_IL: .EQU CPU_IOBASE+$33 ;Interrupt vector load |
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CPU_ITC: .EQU CPU_IOBASE+$34 ;INT/TRAP control |
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; |
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CPU_RCR: .EQU CPU_IOBASE+$36 ;Refresh control |
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; |
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CPU_CBR: .EQU CPU_IOBASE+$38 ;MMU common base register |
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CPU_BBR: .EQU CPU_IOBASE+$39 ;MMU bank base register |
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CPU_CBAR .EQU CPU_IOBASE+$3A ;MMU common/bank area register |
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; |
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CPU_OMCR: .EQU CPU_IOBASE+$3E ;Operation mode control |
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CPU_ICR: .EQU $3F ;I/O control register (not relocated!!!) |
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; |
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; N8 ONBOARD I/O REGISTERS |
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; |
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N8_IOBASE .EQU $80 |
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; |
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PPI .EQU N8_IOBASE+$00 |
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PPIA .EQU PPI+$00 ; PORT A |
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PPIB .EQU PPI+$01 ; PORT B |
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PPIC .EQU PPI+$02 ; PORT C |
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PPIX .EQU PPI+$03 ; PPI CONTROL PORT |
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; |
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PPI2 .EQU N8_IOBASE+$04 |
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PPI2A .EQU PPI2+$00 ; PORT A |
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PPI2B .EQU PPI2+$01 ; PORT B |
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PPI2C .EQU PPI2+$02 ; PORT C |
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PPI2X .EQU PPI2+$03 ; PPI CONTROL PORT |
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; |
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RTC: .EQU N8_IOBASE+$08 ;RTC latch and buffer |
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;FDC: .EQU N8_IOBASE+$0C ;Floppy disk controller |
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;UTIL: .EQU N8_IOBASE+$10 ;Floppy disk utility |
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ACR: .EQU N8_IOBASE+$14 ;auxillary control register |
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RMAP: .EQU N8_IOBASE+$16 ;ROM page register |
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VDP: .EQU N8_IOBASE+$18 ;Video Display Processor (TMS9918A) |
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PSG: .EQU N8_IOBASE+$1C ;Programmable Sound Generator (AY-3-8910) |
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; |
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DEFACR .EQU $1B |
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; |
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#ENDIF |
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